[flashrom] [PATCH] MCP67 SPI detection/debugging

Carl-Daniel Hailfinger c-d.hailfinger.devel.2006 at gmx.net
Fri Dec 4 18:16:27 CET 2009

On 04.12.2009 17:48, Alessandro Polverini wrote:
> I got latest sources from trunk, applied the provided patch,
> cold-booted and saved the output of flashrom -V (attached).
> flashrom v0.9.1-r791
> No coreboot table found.
> Found chipset "NVIDIA MCP67", enabling flash write... ISA bridge reg 0x8a contents: 0x40, bit 6 is 1, bit 5 is 0

Interesting. Apparently these bits are already set exactly the way we
would have set them according to the spec. Maybe we can use this to
differentiate between LPC/SPI flash.

> GPIO BAR is at 0xfec80000, after clearing low bits BAR is at 0xfec80000


> SPI control is 0xc01a, enable=0, idle=0

As expected.

> I hope this helps,

Yes, it helps a lot. Thank you!

Now we just have to find people who can run this patch on MCP67 with LPC
flash (or can at least send full lspci for such boards). If ISA bridge
reg 0x8a differs there, we can investigate further. If you or someone
else have a machine with similar chipset which can be rebooted a few
times, it would be very interesting to mess with the ISA bridge regs
(may cause a crash, should automatically recover after a full poweroff).


Developer quote of the month: 
"We are juggling too many chainsaws and flaming arrows and tigers."

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