[flashrom] [PATCH] Updated vt823x "set all writes to lpc".

Carl-Daniel Hailfinger c-d.hailfinger.devel.2006 at gmx.net
Tue Dec 22 03:48:38 CET 2009

On 16.12.2009 12:14, Luc Verhaegen wrote:
> Chipset/Board: vt8237: Set All mem cycles to LPC in chipset enable.

I don't have the datasheet, so I can't cross-check. I'm very interested
why this would be needed, though. If mem cycles don't go to LPC and we
have flash on LPC, the board won't boot anyway. If we force mem cycles
to LPC although we have parallel ROM, this will break. Does VT8237R
support parallel ROMs?

> Only done for VT8237R (possibly needed for VT8237 too), VT8235 does
> not need this (even if the original bios does so: Asus A7V8X-MX SE,
> MSI KT4V were verified).

Yes, the VT8235 datasheet says those bits are reserved.

How about VT8237A and VT8237S?

> This then opens a floodgate of cleanups in the board enables.
> * EPIA SP board enable vanishes, taking EPIA CN match with it.

Those should be moved to the "known good" list in print.c or they will
end up not being listed as supported.

> * Asus A7V8X-MX/Tyan S2498 board enable then equals
>   w836xx_memw_enable_2e
> * AOpen vKM400Am-S board enable then equals it8705_rom_write_enable
> * Epia M board enable becomes via_vt823x_gpio15_raise
> * Epia N board enable becomes via_vt823x_gpio9_raise
> * Asus M2V-MX board enable becomes via_vt823x_gpio5_raise
> * vt823x_gpio_set becomes via_vt823x_gpio_set, and now detects ISA
>   bridge itself, in concordance with intel ich and nvidia mcp gpio.

I do like the GPIO cleanups. They make the board enables shorter and
more readable.

> --- a/chipset_enable.c
> +++ b/chipset_enable.c
> @@ -603,6 +603,13 @@  static int enable_flash_vt823x(struct pci_dev *dev, const char *name)
>  		return -1;
>  	}
> +	if (dev->device_id == 0x3227) { /* VT8237 */

Should say VT8237R, not VT8237 (at least according to your comments in
other places in the code).

> +	    /* All memory cycles, not just ROM ones, go to LPC. */
> +	    val = pci_read_byte(dev, 0x59);
> +	    val &= ~0x80;
> +	    pci_write_byte(dev, 0x59, val);
> +	}
> +
>  	return 0;
>  }

Side note: Should we read the ROMCS# strap on VT8235 to check whether
the ROM is LPC or Parallel? Does this strap exist for other VT823x as well?

I found a bug and two weirdnesses (at least when using VT8235 datasheet
as reference) in the original code for vt823x_gpio_set():
GPIO 9 on VT8235 needs val |= 0x08, not val |= 0x20. Not sure whether a
fix here would break some board enables.
For GPIOs 9,12-13 we have to make sure that PCI config reg 0x53 bit 7
(PCI DMA Pair A and Pair B) is 0.
For GPIOs 12-15 we have to make sure that PCI config reg 0x5b bit 1
(INTE#, INTF#, INTG#, INTH#) is 0.

If you have a good explanation for the mem cycle question and if you'll
add the removed boards to the known good list either as followup patch
or right now, this is
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>

A bugfix for the GPIO function would be appreciated, but that's a
separate issue. I don't have VT8237* datasheets, so I can't do that myself.


Developer quote of the month: 
"We are juggling too many chainsaws and flaming arrows and tigers."

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