[flashrom] [RFC] JEDEC refactor w/ conversion notes and file eliminations

[Michael Karcher]

Am Donnerstag, den 24.12.2009, 22:03 -0800 schrieb Sean Nelson:

I cross-checked data sheets for chips where flashrom uses a reduced
number of address bits (non-reduced being 0x5555/0x2AAA).

Regards,
  Michael Karcher

> List of chips that use a specific addressing for command codes:
> 0x2AA based chips:
(that means 11 address bits, A0..A10 bits used)
>   * am29f040b
>   * mx29f002
>   * pm29f002

11 bits maybe needed:
=====================
AMD Am29F010B:
http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/am29f010b_00_c4.pdf
Datasheet does not tell anything about ignored address lines in
commands.

PMC PM29F002B/PM29F002T:
http://www.datasheetarchive.com/pdf-datasheets/Datasheets-26/DSA-508503.pdf
Datasheet does not tell anything about ignored address lines.

AMIC A29002B/AM29002T: [Listed here because 0xAAA would have A11 set
which is not marked as don't care. Currently, it uses write_jedec_1
which will fail if the datasheet is correct about A11 being used.]
http://www.amictechnology.com/pdf/A29002.pdf
Page 11, Note 4 "Address bits A17 - A12 are don't cares for unlock and
command cycles, unless SA or PA required."

Macronix MX29LV040: [Currently uses write_jedec_1 which will fail if the
higher address lines are not ignored.]
http://www.datasheetcatalog.org/datasheet/macronix/MX29LV040TI-70.pdf
Datasheet does not tell anything about ignored address lines.

more bits OK according to data sheet:
=====================================
AMD Am29F016D: 
http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/21444e3.pdf
Page 21, Note 4 "Address bits A20-A11 are don't cares for unlock and
command cycles, unless SA or PA required", SA and PA meaning "sector
address" and "programmed address"

AMD Am29F040B:
http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/21445.pdf
Page 14, Note 4 "Address bits A18-A11 are don't cares for unlock and
command cycles, unless SA or PA required"

AMD Am29F080B:
http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/21503g2.pdf
Page 18, Note 8 "Unless otherwise noted, address bits A19-A11 are don't
care."

AMD Am29LV040B:
http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/21354e2.pdf
Page 17, Note 4 "Address bits A18-A11 are don't cares for unlock and
command cycles."

AMD Am29LV081B:
http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/21525.pdf
Page 17, Note 4 "All address bits are don't cares for unlock and command
cycles, except where SA or PA required."

AMIC A29040B:
http://www.amictechnology.com/pdf/A29040B.pdf
Page 14, Note 4 "Address bits A18-A11 are don't cares for unlock and
command cycles, unless SA or PA required"

Macronix MX29F001T/B
http://www.datasheetcatalog.org/datasheet/macronix/MX29F001TQC-90.pdf
Page 5, Note 3 "The system should generate the following address
patterns: 555H or 2AAH to Address A0-A10. Address bit A11-A17 = X =
Don't care for all address commands except for Programm Address (PA) and
Sector Address (SA). Write Sequence may be initiated with A11-A17 in
either state."

Macronix MX29F002T/B
http://pdf.dzsc.net.cn/20090603/200903281341143638.pdf
Page 5, Note 3 "The system should generate the following address
patterns: 555H or 2AAH to Address A0-A10. Address bit A11-A17 = X =
Don't care for all address commands except for Programm Address (PA) and
Sector Address (SA). Write Sequence may be initiated with A11-A17 in
either state."

ST M29F040B:
http://www.datasheetcatalog.org/datasheet/SGSThomsonMicroelectronics/mXyxzsz.pdf
Page 7: "The command interface only uses the address bits A0-A10 to
verify the commands, the upper address bits are Don't Care."

Am29F010A/B:
http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/am29f010b_00_c4.pdf
Datasheet does not tell anything about ignored address lines in
commands.
PM29F0002L/PM29F0002B - Chip name contains a type, it should be
PM29F002L/PM29F002B
http://www.alldatasheet.co.kr/datasheet-pdf/pdf_kor/118671/PMC/PM29F002B-55JC.html
Datasheet does not tell anything about ignored address lines.

> 0xAAA based chips:
(i.e. Address bits up to A0-A11 used)
>   * m29f002

more bits OK according to data sheet:
=====================================
ST M29F002B/M29F002NT/M29F002T:
http://www.datasheetcatalog.org/datasheet/stmicroelectronics/5166.pdf
Page 8, Note 7: "For Coded cycles address inputs A12-A17 are don't
care."
 
>   * m29f400bt
this Chip is not standard 0xAAA based at all. Please carefully read the
comment in the file.