[flashrom] Support for flash mx1635d success
c-d.hailfinger.devel.2006 at gmx.net
Thu Oct 21 18:16:19 CEST 2010
thank you for testing those chips.
flashrom 0.9.3 has dynamic ICH SPI reprogramming and should be able to
use all erase methods on your machine.
Current flashrom svn HEAD has some partial write functionality, and the
latest partial write patch is available at
On 21.10.2010 15:14, stephan.guilloux at free.fr wrote:
> We successfully tested of flashrom 0.9.2 (SVN 1185) on flash Macronix MX1635d.
> As required, the output of -V, -VE, -Vr and -vw are given below and in
> [root at xa000000 root]# flashrom -Vw /DHS3bin/downbin/bioscs2.rom
> flashrom vV092.1185 on unknown machine, built with libpci 3.1.7, GCC 2.95.3
> 20010315 (release), little endian
> Calibrating delay loop... OK.
> Initializing internal programmer
> Found chipset "Intel EP80579", enabling flash write... chipset PCI ID is 8086:5031,
> BIOS Lock Enable: disabled, BIOS Write Enable: enabled, BIOS_CNTL is 0x1
> GCS = 0xd70260: BIOS Interface Lock-Down: disabled, BOOT BIOS Straps: 0x0
> Programming OPCODES...
> program_opcodes: preop=5006 optype=463b opmenu=05d80302c79f0190
> SPI Read Configuration: prefetching disabled, caching enabled, OK.
> This chipset supports the following protocols: SPI.
> Probing for Macronix MX25L1635D, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2415
> Chip status register is 00
> Found chip "Macronix MX25L1635D" (2048 KB, SPI) at physical address 0xffe00000.
> This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE
> Writing flash chip... Erasing flash before programming... Erasing flash chip...
> Looking at blockwise erase function 0
> ... trying... 0x000000-0x000fff, ich_spi_send_multicommand: FIXME: Add
> on-the-fly reprogramming of the chipset opcode
> Invalid OPCODE 0x20
> spi_block_erase_20 failed during command execution at address 0x0
Yes, the invalid opcode message should not appear anymore in flashrom 0.9.3.
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