From c-d.hailfinger.devel.2006 at gmx.net Wed Nov 2 02:44:17 2011 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Wed, 02 Nov 2011 02:44:17 +0100 Subject: [flashrom] [PATCH 1/2] ichspi: remove dependency on spi_programmer from generate_opcodes and program_opcodes In-Reply-To: <1319636118-15878-2-git-send-email-stefan.tauner@student.tuwien.ac.at> References: <1319636118-15878-1-git-send-email-stefan.tauner@student.tuwien.ac.at> <1319636118-15878-2-git-send-email-stefan.tauner@student.tuwien.ac.at> Message-ID: <4EB0A071.8020506@gmx.net> Am 26.10.2011 15:35 schrieb Stefan Tauner: > This allows them to be called before programmer registration. > --- > i think it might be a good idea to get rid of the whole > switch(spi_programmer->type) > pattern and create a file-scope static ich_generation variable instead > of using the type member and the ich_generation parameters everywhere. Absolutely agreed. The only possible generic problem with that approach would be the registration of multiple ICH-style SPI programmers, but unless we see boards with two active ICH-style southbridges I think we can assume the static variable handles it well. (Note that boards with multiple MCP55 southbridges exist, but only one southbridge has an attached flash chip.) There might be an issue for those who want to use flashrom as a standalone tool (e.g. on top of libpayload) where heap allocations for static variables are unwanted, but that's a huge can of worms and I'd rather ignore that issue until either static variables work well in that environment or until someone hacks a way around static variables being a problem there. > the type member is enough most of the time to derive the wanted > information, but > - not always (e.g. ich_set_bbar) > - only available after registration, which we want to delay till the end > of init. > - we really want to distinguish between chipset version-grained > attributes which are not reflected by the registered programmer. Indeed. So if you could rework the patch to use your static variable suggestion, it would reduce patch size and make the code more readable. Regards, Carl-Daniel > Signed-off-by: Stefan Tauner > --- > ichspi.c | 44 +++++++++++++++++++++++++++----------------- > 1 files changed, 27 insertions(+), 17 deletions(-) > > diff --git a/ichspi.c b/ichspi.c > index afa420b..bc03554 100644 > --- a/ichspi.c > +++ b/ichspi.c > @@ -225,8 +225,8 @@ static uint16_t REGREAD8(int X) > /* Common SPI functions */ > static int find_opcode(OPCODES *op, uint8_t opcode); > static int find_preop(OPCODES *op, uint8_t preop); > -static int generate_opcodes(OPCODES * op); > -static int program_opcodes(OPCODES *op, int enable_undo); > +static int generate_opcodes(int ich_generation, OPCODES * op); > +static int program_opcodes(int ich_generation, OPCODES *op, int enable_undo); > static int run_opcode(OPCODE op, uint32_t offset, > uint8_t datalength, uint8_t * data); > > @@ -410,7 +410,18 @@ static int reprogram_opcode_on_the_fly(uint8_t opcode, unsigned int writecnt, un > int oppos=2; // use original JEDEC_BE_D8 offset > curopcodes->opcode[oppos].opcode = opcode; > curopcodes->opcode[oppos].spi_type = spi_type; > - program_opcodes(curopcodes, 0); > + switch (spi_programmer->type) { > + case SPI_CONTROLLER_ICH7: > + case SPI_CONTROLLER_VIA: > + program_opcodes(7, curopcodes, 0); > + break; > + case SPI_CONTROLLER_ICH9: > + program_opcodes(9, curopcodes, 0); > + break; > + default: > + msg_perr("%s: unsupported chipset\n", __func__); > + return -1; > + } > oppos = find_opcode(curopcodes, opcode); > msg_pdbg ("on-the-fly OPCODE (0x%02X) re-programmed, op-pos=%d\n", opcode, oppos); > return oppos; > @@ -443,7 +454,7 @@ static int find_preop(OPCODES *op, uint8_t preop) > } > > /* Create a struct OPCODES based on what we find in the locked down chipset. */ > -static int generate_opcodes(OPCODES * op) > +static int generate_opcodes(int ich_generation, OPCODES * op) > { > int a; > uint16_t preop, optype; > @@ -498,7 +509,7 @@ static int generate_opcodes(OPCODES * op) > return 0; > } > > -static int program_opcodes(OPCODES *op, int enable_undo) > +static int program_opcodes(int ich_generation, OPCODES *op, int enable_undo) > { > uint8_t a; > uint16_t preop, optype; > @@ -529,9 +540,8 @@ static int program_opcodes(OPCODES *op, int enable_undo) > } > > msg_pdbg("\n%s: preop=%04x optype=%04x opmenu=%08x%08x\n", __func__, preop, optype, opmenu[0], opmenu[1]); > - switch (spi_programmer->type) { > - case SPI_CONTROLLER_ICH7: > - case SPI_CONTROLLER_VIA: > + switch (ich_generation) { > + case 7: > /* Register undo only for enable_undo=1, i.e. first call. */ > if (enable_undo) { > rmmio_valw(ich_spibar + ICH7_REG_PREOP); > @@ -544,7 +554,10 @@ static int program_opcodes(OPCODES *op, int enable_undo) > mmio_writel(opmenu[0], ich_spibar + ICH7_REG_OPMENU); > mmio_writel(opmenu[1], ich_spibar + ICH7_REG_OPMENU + 4); > break; > - case SPI_CONTROLLER_ICH9: > + case 8: > + case 9: > + case 10: > + default: /* Future version might behave the same */ > /* Register undo only for enable_undo=1, i.e. first call. */ > if (enable_undo) { > rmmio_valw(ich_spibar + ICH9_REG_PREOP); > @@ -557,9 +570,6 @@ static int program_opcodes(OPCODES *op, int enable_undo) > mmio_writel(opmenu[0], ich_spibar + ICH9_REG_OPMENU); > mmio_writel(opmenu[1], ich_spibar + ICH9_REG_OPMENU + 4); > break; > - default: > - msg_perr("%s: unsupported chipset\n", __func__); > - return -1; > } > > return 0; > @@ -652,7 +662,7 @@ static void ich_fill_data(const uint8_t *data, int len, int reg0_off) > * > * It should be called before ICH sends any spi command. > */ > -static int ich_init_opcodes(void) > +static int ich_init_opcodes(int ich_generation) > { > int rc = 0; > OPCODES *curopcodes_done; > @@ -663,11 +673,11 @@ static int ich_init_opcodes(void) > if (ichspi_lock) { > msg_pdbg("Reading OPCODES... "); > curopcodes_done = &O_EXISTING; > - rc = generate_opcodes(curopcodes_done); > + rc = generate_opcodes(ich_generation, curopcodes_done); > } else { > msg_pdbg("Programming OPCODES... "); > curopcodes_done = &O_ST_M25P; > - rc = program_opcodes(curopcodes_done, 1); > + rc = program_opcodes(ich_generation, curopcodes_done, 1); > } > > if (rc) { > @@ -1343,6 +1353,7 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, > > /* Assign Virtual Address */ > ich_spibar = rcrb + spibar_offset; > + ich_init_opcodes(ich_generation); > > switch (ich_generation) { > case 7: > @@ -1383,7 +1394,6 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, > } > ich_set_bbar(ich_generation, 0); > register_spi_programmer(&spi_programmer_ich7); > - ich_init_opcodes(); > break; > case 8: > case 9: > @@ -1557,7 +1567,7 @@ int via_init_spi(struct pci_dev *dev) > } > > ich_set_bbar(7, 0); > - ich_init_opcodes(); > + ich_init_opcodes(7); > > return 0; > } -- http://www.hailfinger.org/ From c-d.hailfinger.devel.2006 at gmx.net Wed Nov 2 04:36:03 2011 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Wed, 02 Nov 2011 04:36:03 +0100 Subject: [flashrom] [PATCH] Register opaque and parallel/LPC/FWH programmers Message-ID: <4EB0BAA3.2090308@gmx.net> Just to show how it should look like once all type-specific programmer registration patches are applied. The generic programmer registration patch will live on top of this. Signed-off-by: Carl-Daniel Hailfinger Index: flashrom-register_all_programmers/flash.h =================================================================== --- flashrom-register_all_programmers/flash.h (Revision 1457) +++ flashrom-register_all_programmers/flash.h (Arbeitskopie) @@ -62,8 +62,9 @@ BUS_LPC = 1 << 1, BUS_FWH = 1 << 2, BUS_SPI = 1 << 3, + BUS_PROG = 1 << 4, BUS_NONSPI = BUS_PARALLEL | BUS_LPC | BUS_FWH, - BUS_UNKNOWN = BUS_PARALLEL | BUS_LPC | BUS_FWH | BUS_SPI, + BUS_UNKNOWN = BUS_PARALLEL | BUS_LPC | BUS_FWH | BUS_SPI | BUS_PROG, }; /* Index: flashrom-register_all_programmers/drkaiser.c =================================================================== --- flashrom-register_all_programmers/drkaiser.c (Revision 1457) +++ flashrom-register_all_programmers/drkaiser.c (Arbeitskopie) @@ -39,6 +39,19 @@ static uint8_t *drkaiser_bar; +static const struct par_programmer par_programmer_drkaiser = { + .chip_readb = drkaiser_chip_readb, + .chip_readw = fallback_chip_readw, + .chip_readl = fallback_chip_readl, + .chip_readn = fallback_chip_readn, + .chip_writeb = drkaiser_chip_writeb, + .chip_writew = fallback_chip_writew, + .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, + .map_flash_region = fallback_map, + .unmap_flash_region = fallback_unmap, +}; + static int drkaiser_shutdown(void *data) { physunmap(drkaiser_bar, DRKAISER_MEMMAP_SIZE); @@ -64,7 +77,8 @@ drkaiser_bar = physmap("Dr. Kaiser PC-Waechter flash memory", addr, DRKAISER_MEMMAP_SIZE); - buses_supported = BUS_PARALLEL; + register_par_programmer(&par_programmer_drkaiser, BUS_PARALLEL); + max_rom_decode.parallel = 131072; if (register_shutdown(drkaiser_shutdown, NULL)) return 1; Index: flashrom-register_all_programmers/it87spi.c =================================================================== --- flashrom-register_all_programmers/it87spi.c (Revision 1457) +++ flashrom-register_all_programmers/it87spi.c (Arbeitskopie) @@ -192,7 +192,7 @@ free(portpos); exit_conf_mode_ite(port); it8716f_flashport = flashport; - if (buses_supported & BUS_SPI) + if (internal_buses_supported & BUS_SPI) msg_pdbg("Overriding chipset SPI with IT87 SPI.\n"); /* FIXME: Add the SPI bus or replace the other buses with it? */ register_spi_programmer(&spi_programmer_it87xx); Index: flashrom-register_all_programmers/gfxnvidia.c =================================================================== --- flashrom-register_all_programmers/gfxnvidia.c (Revision 1457) +++ flashrom-register_all_programmers/gfxnvidia.c (Arbeitskopie) @@ -61,6 +61,19 @@ {}, }; +static const struct par_programmer par_programmer_gfxnvidia = { + .chip_readb = gfxnvidia_chip_readb, + .chip_readw = fallback_chip_readw, + .chip_readl = fallback_chip_readl, + .chip_readn = fallback_chip_readn, + .chip_writeb = gfxnvidia_chip_writeb, + .chip_writew = fallback_chip_writew, + .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, + .map_flash_region = fallback_map, + .unmap_flash_region = fallback_unmap, +}; + static int gfxnvidia_shutdown(void *data) { physunmap(nvidia_bar, GFXNVIDIA_MEMMAP_SIZE); @@ -94,7 +107,7 @@ reg32 &= ~(1 << 0); rpci_write_long(pcidev_dev, 0x50, reg32); - buses_supported = BUS_PARALLEL; + register_par_programmer(&par_programmer_gfxnvidia, BUS_PARALLEL); /* Write/erase doesn't work. */ programmer_may_write = 0; Index: flashrom-register_all_programmers/serprog.c =================================================================== --- flashrom-register_all_programmers/serprog.c (Revision 1457) +++ flashrom-register_all_programmers/serprog.c (Arbeitskopie) @@ -309,6 +309,21 @@ .write_256 = default_spi_write_256, }; +static const struct par_programmer par_programmer_serprog = { + .chip_readb = serprog_chip_readb, + .chip_readw = fallback_chip_readw, + .chip_readl = fallback_chip_readl, + .chip_readn = serprog_chip_readn, + .chip_writeb = serprog_chip_writeb, + .chip_writew = fallback_chip_writew, + .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, + .map_flash_region = fallback_map, + .unmap_flash_region = fallback_unmap, +}; + +static enum chipbustype serprog_buses_supported = BUS_NONE; + int serprog_init(void) { uint16_t iface; @@ -400,11 +415,13 @@ if (sp_docommand(S_CMD_Q_IFACE, 0, NULL, 2, &iface)) { msg_perr("Error: NAK to query interface version\n"); + // FIXME: Clean up and return an error instead. exit(1); } if (iface != 1) { msg_perr("Error: Unknown interface version: %d\n", iface); + // FIXME: Clean up and return an error instead. exit(1); } @@ -412,28 +429,34 @@ if (sp_docommand(S_CMD_Q_CMDMAP, 0, NULL, 32, sp_cmdmap)) { msg_perr("Error: query command map not supported\n"); + // FIXME: Clean up and return an error instead. exit(1); } sp_check_avail_automatic = 1; - + /* FIXME: This assumes that serprog device bustypes are always + * identical with flashrom bustype enums and that they all fit + * in a single byte. + */ if (sp_docommand(S_CMD_Q_BUSTYPE, 0, NULL, 1, &c)) { msg_perr("Warning: NAK to query supported buses\n"); c = BUS_NONSPI; /* A reasonable default for now. */ } - buses_supported = c; + serprog_buses_supported = c; + msg_pdbg(MSGHEADER "Bus support: parallel=%s, LPC=%s, FWH=%s, SPI=%s\n", (c & BUS_PARALLEL) ? "on" : "off", (c & BUS_LPC) ? "on" : "off", (c & BUS_FWH) ? "on" : "off", (c & BUS_SPI) ? "on" : "off"); /* Check for the minimum operational set of commands. */ - if (buses_supported & BUS_SPI) { + if (serprog_buses_supported & BUS_SPI) { uint8_t bt = BUS_SPI; if (sp_check_commandavail(S_CMD_O_SPIOP) == 0) { msg_perr("Error: SPI operation not supported while the " "bustype is SPI\n"); + // FIXME: Clean up and return an error instead. exit(1); } /* Success of any of these commands is optional. We don't need @@ -461,21 +484,22 @@ spi_programmer_serprog.max_data_read = v; msg_pdbg(MSGHEADER "Maximum read-n length is %d\n", v); } - bt = buses_supported; + bt = serprog_buses_supported; sp_docommand(S_CMD_S_BUSTYPE, 1, &bt, 0, NULL); - register_spi_programmer(&spi_programmer_serprog); } - if (buses_supported & BUS_NONSPI) { + if (serprog_buses_supported & BUS_NONSPI) { if (sp_check_commandavail(S_CMD_O_INIT) == 0) { msg_perr("Error: Initialize operation buffer " "not supported\n"); + // FIXME: Clean up and return an error instead. exit(1); } if (sp_check_commandavail(S_CMD_O_DELAY) == 0) { msg_perr("Error: Write to opbuf: " "delay not supported\n"); + // FIXME: Clean up and return an error instead. exit(1); } @@ -483,17 +507,20 @@ if (sp_check_commandavail(S_CMD_R_BYTE) == 0) { msg_perr("Error: Single byte read not supported\n"); + // FIXME: Clean up and return an error instead. exit(1); } /* This could be translated to single byte reads (if missing), * but now we don't support that. */ if (sp_check_commandavail(S_CMD_R_NBYTES) == 0) { msg_perr("Error: Read n bytes not supported\n"); + // FIXME: Clean up and return an error instead. exit(1); } if (sp_check_commandavail(S_CMD_O_WRITEB) == 0) { msg_perr("Error: Write to opbuf: " "write byte not supported\n"); + // FIXME: Clean up and return an error instead. exit(1); } @@ -513,6 +540,7 @@ if (!sp_write_n_buf) { msg_perr("Error: cannot allocate memory for " "Write-n buffer\n"); + // FIXME: Clean up and return an error instead. exit(1); } sp_write_n_bytes = 0; @@ -551,11 +579,13 @@ if (sp_check_commandavail(S_CMD_O_EXEC) == 0) { msg_perr("Error: Execute operation buffer not " "supported\n"); + // FIXME: Clean up and return an error instead. exit(1); } if (sp_docommand(S_CMD_O_INIT, 0, NULL, 0, NULL)) { msg_perr("Error: NAK to initialize operation buffer\n"); + // FIXME: Clean up and return an error instead. exit(1); } @@ -572,6 +602,11 @@ sp_streamed_transmit_ops = 0; sp_streamed_transmit_bytes = 0; sp_opbuf_usage = 0; + if (serprog_buses_supported & BUS_SPI) + register_spi_programmer(&spi_programmer_serprog); + if (serprog_buses_supported & BUS_NONSPI) + register_par_programmer(&par_programmer_serprog, + serprog_buses_supported & BUS_NONSPI); return 0; } Index: flashrom-register_all_programmers/nicrealtek.c =================================================================== --- flashrom-register_all_programmers/nicrealtek.c (Revision 1457) +++ flashrom-register_all_programmers/nicrealtek.c (Arbeitskopie) @@ -36,6 +36,19 @@ {}, }; +static const struct par_programmer par_programmer_nicrealtek = { + .chip_readb = nicrealtek_chip_readb, + .chip_readw = fallback_chip_readw, + .chip_readl = fallback_chip_readl, + .chip_readn = fallback_chip_readn, + .chip_writeb = nicrealtek_chip_writeb, + .chip_writew = fallback_chip_writew, + .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, + .map_flash_region = fallback_map, + .unmap_flash_region = fallback_unmap, +}; + static int nicrealtek_shutdown(void *data) { /* FIXME: We forgot to disable software access again. */ @@ -50,7 +63,7 @@ io_base_addr = pcidev_init(PCI_BASE_ADDRESS_0, nics_realtek); - buses_supported = BUS_PARALLEL; + register_par_programmer(&par_programmer_nicrealtek, BUS_PARALLEL); if (register_shutdown(nicrealtek_shutdown, NULL)) return 1; Index: flashrom-register_all_programmers/satamv.c =================================================================== --- flashrom-register_all_programmers/satamv.c (Revision 1457) +++ flashrom-register_all_programmers/satamv.c (Arbeitskopie) @@ -41,6 +41,19 @@ #define PCI_BAR2_CONTROL 0x00c08 #define GPIO_PORT_CONTROL 0x104f0 +static const struct par_programmer par_programmer_satamv = { + .chip_readb = satamv_chip_readb, + .chip_readw = fallback_chip_readw, + .chip_readl = fallback_chip_readl, + .chip_readn = fallback_chip_readn, + .chip_writeb = satamv_chip_writeb, + .chip_writew = fallback_chip_writew, + .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, + .map_flash_region = fallback_map, + .unmap_flash_region = fallback_unmap, +}; + static int satamv_shutdown(void *data) { physunmap(mv_bar, 0x20000); @@ -137,7 +150,7 @@ mv_iobar = tmp & 0xffff; msg_pspew("Activating I/O BAR at 0x%04x\n", mv_iobar); - buses_supported = BUS_PARALLEL; + register_par_programmer(&par_programmer_satamv, BUS_PARALLEL); /* 512 kByte with two 8-bit latches, and * 4 MByte with additional 3-bit latch. */ Index: flashrom-register_all_programmers/Makefile =================================================================== --- flashrom-register_all_programmers/Makefile (Revision 1457) +++ flashrom-register_all_programmers/Makefile (Arbeitskopie) @@ -242,7 +242,7 @@ CHIP_OBJS = jedec.o stm50flw0x0x.o w39.o w29ee011.o \ sst28sf040.o m29f400bt.o 82802ab.o pm49fl00x.o \ sst49lfxxxc.o sst_fwhub.o flashchips.o spi.o spi25.o sharplhf00l04.o \ - a25.o at25.o + a25.o at25.o opaque.o LIB_OBJS = layout.o Index: flashrom-register_all_programmers/dummyflasher.c =================================================================== --- flashrom-register_all_programmers/dummyflasher.c (Revision 1457) +++ flashrom-register_all_programmers/dummyflasher.c (Arbeitskopie) @@ -75,6 +75,21 @@ .write_256 = dummy_spi_write_256, }; +static const struct par_programmer par_programmer_dummy = { + .chip_readb = dummy_chip_readb, + .chip_readw = dummy_chip_readw, + .chip_readl = dummy_chip_readl, + .chip_readn = dummy_chip_readn, + .chip_writeb = dummy_chip_writeb, + .chip_writew = dummy_chip_writew, + .chip_writel = dummy_chip_writel, + .chip_writen = dummy_chip_writen, + .map_flash_region = dummy_map, + .unmap_flash_region = dummy_unmap, +}; + +enum chipbustype dummy_buses_supported = BUS_NONE; + static int dummy_shutdown(void *data) { msg_pspew("%s\n", __func__); @@ -108,24 +123,29 @@ /* Convert the parameters to lowercase. */ tolower_string(bustext); - buses_supported = BUS_NONE; + dummy_buses_supported = BUS_NONE; if (strstr(bustext, "parallel")) { - buses_supported |= BUS_PARALLEL; + dummy_buses_supported |= BUS_PARALLEL; msg_pdbg("Enabling support for %s flash.\n", "parallel"); } if (strstr(bustext, "lpc")) { - buses_supported |= BUS_LPC; + dummy_buses_supported |= BUS_LPC; msg_pdbg("Enabling support for %s flash.\n", "LPC"); } if (strstr(bustext, "fwh")) { - buses_supported |= BUS_FWH; + dummy_buses_supported |= BUS_FWH; msg_pdbg("Enabling support for %s flash.\n", "FWH"); } + if (dummy_buses_supported & (BUS_PARALLEL | BUS_LPC | BUS_FWH)) + register_par_programmer(&par_programmer_dummy, + dummy_buses_supported & + (BUS_PARALLEL | BUS_LPC | + BUS_FWH)); if (strstr(bustext, "spi")) { register_spi_programmer(&spi_programmer_dummyflasher); msg_pdbg("Enabling support for %s flash.\n", "SPI"); } - if (buses_supported == BUS_NONE) + if (dummy_buses_supported == BUS_NONE) msg_pdbg("Support for all flash bus types disabled.\n"); free(bustext); Index: flashrom-register_all_programmers/cli_classic.c =================================================================== --- flashrom-register_all_programmers/cli_classic.c (Revision 1457) +++ flashrom-register_all_programmers/cli_classic.c (Arbeitskopie) @@ -443,7 +443,10 @@ ret = 1; goto out_shutdown; } + msg_pdbg("This programmer supports the following protocols: %s.\n", + flashbuses_to_text(buses_supported)); + for (i = 0; i < ARRAY_SIZE(flashes); i++) { startchip = probe_flash(startchip, &flashes[i], 0); if (startchip == -1) Index: flashrom-register_all_programmers/internal.c =================================================================== --- flashrom-register_all_programmers/internal.c (Revision 1457) +++ flashrom-register_all_programmers/internal.c (Arbeitskopie) @@ -127,6 +127,21 @@ int is_laptop = 0; int laptop_ok = 0; +static const struct par_programmer par_programmer_internal = { + .chip_readb = internal_chip_readb, + .chip_readw = internal_chip_readw, + .chip_readl = internal_chip_readl, + .chip_readn = internal_chip_readn, + .chip_writeb = internal_chip_writeb, + .chip_writew = internal_chip_writew, + .chip_writel = internal_chip_writel, + .chip_writen = fallback_chip_writen, + .map_flash_region = physmap, + .unmap_flash_region = physunmap, +}; + +enum chipbustype internal_buses_supported = BUS_NONE; + static int internal_shutdown(void *data) { release_io_perms(); @@ -191,9 +206,10 @@ return 1; /* Default to Parallel/LPC/FWH flash devices. If a known host controller - * is found, the init routine sets the buses_supported bitfield. + * is found, the host controller init routine sets the + * internal_buses_supported bitfield. */ - buses_supported = BUS_NONSPI; + internal_buses_supported = BUS_NONSPI; /* Initialize PCI access for flash enables */ pacc = pci_alloc(); /* Get the pci_access structure */ @@ -287,6 +303,7 @@ * Besides that, we don't check the board enable return code either. */ #if defined(__i386__) || defined(__x86_64__) || defined (__mips) + register_par_programmer(&par_programmer_internal, internal_buses_supported); return 0; #else msg_perr("Your platform is not supported yet for the internal " Index: flashrom-register_all_programmers/ichspi.c =================================================================== --- flashrom-register_all_programmers/ichspi.c (Revision 1457) +++ flashrom-register_all_programmers/ichspi.c (Arbeitskopie) @@ -1523,7 +1523,7 @@ ich_spibar = physmap("VT8237S MMIO registers", mmio_base, 0x70); /* Not sure if it speaks all these bus protocols. */ - buses_supported = BUS_LPC | BUS_FWH; + internal_buses_supported = BUS_LPC | BUS_FWH; register_spi_programmer(&spi_programmer_via); msg_pdbg("0x00: 0x%04x (SPIS)\n", mmio_readw(ich_spibar + 0)); Index: flashrom-register_all_programmers/opaque.c =================================================================== --- flashrom-register_all_programmers/opaque.c (Revision 0) +++ flashrom-register_all_programmers/opaque.c (Revision 0) @@ -0,0 +1,93 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2011 Carl-Daniel Hailfinger + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * Contains the opaque programmer framework. + * An opaque programmer is a programmer which does not provide direct access + * to the flash chip and which abstracts all flash chip properties into a + * programmer specific interface. + */ + +#include +#include +#include "flash.h" +#include "flashchips.h" +#include "chipdrivers.h" +#include "programmer.h" + +const struct opaque_programmer opaque_programmer_none = { + .max_data_read = MAX_DATA_UNSPECIFIED, + .max_data_write = MAX_DATA_UNSPECIFIED, + .probe = NULL, + .read = NULL, + .write = NULL, +}; + +const struct opaque_programmer *opaque_programmer = &opaque_programmer_none; + +int probe_opaque(struct flashchip *flash) +{ + if (!opaque_programmer->probe) { + msg_perr("%s called, but this is not an opaque programmer. " + "Please report a bug at flashrom at flashrom.org\n", + __func__); + return 0; + } + + return opaque_programmer->probe(flash); +} + +int read_opaque(struct flashchip *flash, uint8_t *buf, int start, int len) +{ + if (!opaque_programmer->read) { + msg_perr("%s called, but this is not an opaque programmer. " + "Please report a bug at flashrom at flashrom.org\n", + __func__); + return 1; + } + return opaque_programmer->read(flash, buf, start, len); +} + +int write_opaque(struct flashchip *flash, uint8_t *buf, int start, int len) +{ + if (!opaque_programmer->write) { + msg_perr("%s called, but this is not an opaque programmer. " + "Please report a bug at flashrom at flashrom.org\n", + __func__); + return 1; + } + return opaque_programmer->write(flash, buf, start, len); +} + +int erase_opaque(struct flashchip *flash, unsigned int blockaddr, unsigned int blocklen) +{ + if (!opaque_programmer->erase) { + msg_perr("%s called, but this is not an opaque programmer. " + "Please report a bug at flashrom at flashrom.org\n", + __func__); + return 1; + } + return opaque_programmer->erase(flash, blockaddr, blocklen); +} + +void register_opaque_programmer(const struct opaque_programmer *pgm) +{ + opaque_programmer = pgm; + buses_supported |= BUS_PROG; +} Index: flashrom-register_all_programmers/nicnatsemi.c =================================================================== --- flashrom-register_all_programmers/nicnatsemi.c (Revision 1457) +++ flashrom-register_all_programmers/nicnatsemi.c (Arbeitskopie) @@ -35,6 +35,19 @@ {}, }; +static const struct par_programmer par_programmer_nicnatsemi = { + .chip_readb = nicnatsemi_chip_readb, + .chip_readw = fallback_chip_readw, + .chip_readl = fallback_chip_readl, + .chip_readn = fallback_chip_readn, + .chip_writeb = nicnatsemi_chip_writeb, + .chip_writew = fallback_chip_writew, + .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, + .map_flash_region = fallback_map, + .unmap_flash_region = fallback_unmap, +}; + static int nicnatsemi_shutdown(void *data) { pci_cleanup(pacc); @@ -48,7 +61,7 @@ io_base_addr = pcidev_init(PCI_BASE_ADDRESS_0, nics_natsemi); - buses_supported = BUS_PARALLEL; + register_par_programmer(&par_programmer_nicnatsemi, BUS_PARALLEL); /* The datasheet shows address lines MA0-MA16 in one place and MA0-MA15 * in another. My NIC has MA16 connected to A16 on the boot ROM socket Index: flashrom-register_all_programmers/it85spi.c =================================================================== --- flashrom-register_all_programmers/it85spi.c (Revision 1457) +++ flashrom-register_all_programmers/it85spi.c (Arbeitskopie) @@ -257,8 +257,10 @@ INDIRECT_A3(shm_io_base, (base >> 24)); #endif #ifdef LPC_MEMORY - base = (chipaddr)programmer_map_flash_region("it85 communication", - 0xFFFFF000, 0x1000); + /* FIXME: We should block accessing that region for anything else. + * Major TODO here, and it will be a lot of work. + */ + base = (chipaddr)physmap("it85 communication", 0xFFFFF000, 0x1000); msg_pdbg("%s():%d base=0x%08x\n", __func__, __LINE__, (unsigned int)base); ce_high = (unsigned char *)(base + 0xE00); /* 0xFFFFFE00 */ @@ -285,18 +287,26 @@ { int ret; - if (!(buses_supported & BUS_FWH)) { + if (!(internal_buses_supported & BUS_FWH)) { msg_pdbg("%s():%d buses not support FWH\n", __func__, __LINE__); return 1; } ret = it85xx_spi_common_init(s); msg_pdbg("FWH: %s():%d ret=%d\n", __func__, __LINE__, ret); if (!ret) { - msg_pdbg("%s():%d buses_supported=0x%x\n", __func__, __LINE__, - buses_supported); - if (buses_supported & BUS_FWH) - msg_pdbg("Overriding chipset SPI with IT85 FWH|SPI.\n"); - /* Really leave FWH enabled? */ + msg_pdbg("%s: internal_buses_supported=0x%x\n", __func__, + internal_buses_supported); + /* Check for FWH because IT85 listens to FWH cycles. + * FIXME: The big question is whether FWH cycles are necessary + * for communication even if LPC_IO is defined. + */ + if (internal_buses_supported & BUS_FWH) + msg_pdbg("Registering IT85 SPI.\n"); + /* FIXME: Really leave FWH enabled? We can't use this region + * anymore since accessing it would mess up IT85 communication. + * If we decide to disable FWH for this region, we should print + * a debug message about it. + */ /* Set this as SPI controller. */ register_spi_programmer(&spi_programmer_it85xx); } Index: flashrom-register_all_programmers/atahpt.c =================================================================== --- flashrom-register_all_programmers/atahpt.c (Revision 1457) +++ flashrom-register_all_programmers/atahpt.c (Arbeitskopie) @@ -40,6 +40,19 @@ {}, }; +static const struct par_programmer par_programmer_atahpt = { + .chip_readb = atahpt_chip_readb, + .chip_readw = fallback_chip_readw, + .chip_readl = fallback_chip_readl, + .chip_readn = fallback_chip_readn, + .chip_writeb = atahpt_chip_writeb, + .chip_writew = fallback_chip_writew, + .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, + .map_flash_region = fallback_map, + .unmap_flash_region = fallback_unmap, +}; + static int atahpt_shutdown(void *data) { /* Flash access is disabled automatically by PCI restore. */ @@ -61,7 +74,7 @@ reg32 |= (1 << 24); rpci_write_long(pcidev_dev, REG_FLASH_ACCESS, reg32); - buses_supported = BUS_PARALLEL; + register_par_programmer(&par_programmer_atahpt, BUS_PARALLEL); if (register_shutdown(atahpt_shutdown, NULL)) return 1; Index: flashrom-register_all_programmers/flashchips.c =================================================================== --- flashrom-register_all_programmers/flashchips.c (Revision 1457) +++ flashrom-register_all_programmers/flashchips.c (Arbeitskopie) @@ -8872,8 +8872,30 @@ .read = read_memmapped, .voltage = {3000, 3600}, /* Also has 12V fast program */ }, - +#if defined(CONFIG_INTERNAL) && (defined(__i386__) || defined(__x86_64__)) { + .vendor = "Programmer", + .name = "Opaque flash chip", + .bustype = BUS_PROG, + .manufacture_id = PROGMANUF_ID, + .model_id = PROGDEV_ID, + .total_size = 0, + .page_size = 256, + /* probe is assumed to work, rest will be filled in by probe */ + .tested = TEST_OK_PROBE, + .probe = probe_opaque, + /* eraseblock sizes will be set by the probing function */ + .block_erasers = + { + { + .block_erase = erase_opaque, + } + }, + .write = write_opaque, + .read = read_opaque, + }, +#endif // defined(CONFIG_INTERNAL) && (defined(__i386__) || defined(__x86_64__)) + { .vendor = "AMIC", .name = "unknown AMIC SPI chip", .bustype = BUS_SPI, @@ -9005,6 +9027,7 @@ .probe = probe_spi_rdid, .write = NULL, }, + { .vendor = "Generic", .name = "unknown SPI chip (REMS)", Index: flashrom-register_all_programmers/flashchips.h =================================================================== --- flashrom-register_all_programmers/flashchips.h (Revision 1457) +++ flashrom-register_all_programmers/flashchips.h (Arbeitskopie) @@ -646,4 +646,7 @@ #define WINBOND_W49V002A 0xB0 #define WINBOND_W49V002FA 0x32 +#define PROGMANUF_ID 0xFFFE /* dummy ID for opaque chips behind a programmer */ +#define PROGDEV_ID 0x01 /* dummy ID for opaque chips behind a programmer */ + #endif /* !FLASHCHIPS_H */ Index: flashrom-register_all_programmers/nic3com.c =================================================================== --- flashrom-register_all_programmers/nic3com.c (Revision 1457) +++ flashrom-register_all_programmers/nic3com.c (Arbeitskopie) @@ -55,6 +55,19 @@ {}, }; +static const struct par_programmer par_programmer_nic3com = { + .chip_readb = nic3com_chip_readb, + .chip_readw = fallback_chip_readw, + .chip_readl = fallback_chip_readl, + .chip_readn = fallback_chip_readn, + .chip_writeb = nic3com_chip_writeb, + .chip_writew = fallback_chip_writew, + .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, + .map_flash_region = fallback_map, + .unmap_flash_region = fallback_unmap, +}; + static int nic3com_shutdown(void *data) { /* 3COM 3C90xB cards need a special fixup. */ @@ -96,8 +109,8 @@ */ OUTW(SELECT_REG_WINDOW + 0, io_base_addr + INT_STATUS); - buses_supported = BUS_PARALLEL; max_rom_decode.parallel = 128 * 1024; + register_par_programmer(&par_programmer_nic3com, BUS_PARALLEL); if (register_shutdown(nic3com_shutdown, NULL)) return 1; Index: flashrom-register_all_programmers/satasii.c =================================================================== --- flashrom-register_all_programmers/satasii.c (Revision 1457) +++ flashrom-register_all_programmers/satasii.c (Arbeitskopie) @@ -42,6 +42,19 @@ {}, }; +static const struct par_programmer par_programmer_satasii = { + .chip_readb = satasii_chip_readb, + .chip_readw = fallback_chip_readw, + .chip_readl = fallback_chip_readl, + .chip_readn = fallback_chip_readn, + .chip_writeb = satasii_chip_writeb, + .chip_writew = fallback_chip_writew, + .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, + .map_flash_region = fallback_map, + .unmap_flash_region = fallback_unmap, +}; + static int satasii_shutdown(void *data) { physunmap(sii_bar, SATASII_MEMMAP_SIZE); @@ -76,7 +89,7 @@ if ((id != 0x0680) && (!(pci_mmio_readl(sii_bar) & (1 << 26)))) msg_pinfo("Warning: Flash seems unconnected.\n"); - buses_supported = BUS_PARALLEL; + register_par_programmer(&par_programmer_satasii, BUS_PARALLEL); if (register_shutdown(satasii_shutdown, NULL)) return 1; Index: flashrom-register_all_programmers/chipset_enable.c =================================================================== --- flashrom-register_all_programmers/chipset_enable.c (Revision 1457) +++ flashrom-register_all_programmers/chipset_enable.c (Arbeitskopie) @@ -213,7 +213,7 @@ uint16_t old, new; uint16_t xbcs = 0x4e; /* X-Bus Chip Select register. */ - buses_supported = BUS_PARALLEL; + internal_buses_supported = BUS_PARALLEL; old = pci_read_word(dev, xbcs); @@ -303,7 +303,7 @@ * FWH_DEC_EN1, but they are called FB_SEL1, FB_SEL2, FB_DEC_EN1 and * FB_DEC_EN2. */ - buses_supported = BUS_FWH; + internal_buses_supported = BUS_FWH; return enable_flash_ich(dev, name, 0x4e); } @@ -412,9 +412,9 @@ msg_pdbg("\nMaximum FWH chip size: 0x%x bytes", max_rom_decode.fwh); /* If we're called by enable_flash_ich_dc_spi, it will override - * buses_supported anyway. + * internal_buses_supported anyway. */ - buses_supported = BUS_FWH; + internal_buses_supported = BUS_FWH; return enable_flash_ich(dev, name, 0xdc); } @@ -434,7 +434,7 @@ if (new != old) rpci_write_byte(dev, 0xd9, new); - buses_supported = BUS_FWH; + internal_buses_supported = BUS_FWH; return 0; } @@ -468,12 +468,11 @@ bnt = mmio_readl(rcrb + 0x3410); if (bnt & 0x02) { /* If strapped to LPC, no SPI initialization is required */ - buses_supported = BUS_FWH; + internal_buses_supported = BUS_FWH; return 0; } /* This adds BUS_SPI */ - buses_supported = BUS_SPI; if (ich_init_spi(dev, tmp, rcrb, 7) != 0) { if (!ret) ret = ERROR_NONFATAL; @@ -556,7 +555,7 @@ * time. At least not with our current code. So we prevent searching * on ICH7 when the southbridge is strapped to LPC */ - buses_supported = BUS_FWH; + internal_buses_supported = BUS_FWH; if (ich_generation == 7) { if (bbs == 0x03) { /* If strapped to LPC, no further SPI initialization is @@ -564,7 +563,7 @@ return ret; } else { /* Disable LPC/FWH if strapped to PCI or SPI */ - buses_supported = 0; + internal_buses_supported = BUS_NONE; } } @@ -667,7 +666,7 @@ #define CS5530_ENABLE_SA2320 (1 << 2) #define CS5530_ENABLE_SA20 (1 << 6) - buses_supported = BUS_PARALLEL; + internal_buses_supported = BUS_PARALLEL; /* Decode 0x000E0000-0x000FFFFF (128 kB), not just 64 kB, and * decode 0xFF000000-0xFFFFFFFF (16 MB), not just 256 kB. * FIXME: Should we really touch the low mapping below 1 MB? Flashrom @@ -820,7 +819,7 @@ (prot & 0xfffff800) + (((prot & 0x7fc) << 8) | 0x3ff)); } - buses_supported = BUS_LPC | BUS_FWH; + internal_buses_supported = BUS_LPC | BUS_FWH; ret = sb600_probe_spi(dev); @@ -914,7 +913,7 @@ { uint8_t tmp; - buses_supported = BUS_PARALLEL; + internal_buses_supported = BUS_PARALLEL; tmp = INB(0xc06); tmp |= 0x1; @@ -1014,7 +1013,7 @@ switch ((val >> 5) & 0x3) { case 0x0: ret = enable_flash_mcp55(dev, name); - buses_supported = BUS_LPC; + internal_buses_supported = BUS_LPC; msg_pdbg("Flash bus type is LPC\n"); break; case 0x2: @@ -1022,7 +1021,7 @@ /* SPI is added in mcp6x_spi_init if it works. * Do we really want to disable LPC in this case? */ - buses_supported = BUS_NONE; + internal_buses_supported = BUS_NONE; msg_pdbg("Flash bus type is SPI\n"); msg_pinfo("SPI on this chipset is WIP. Please report any " "success or failure by mailing us the verbose " @@ -1030,7 +1029,7 @@ break; default: /* Should not happen. */ - buses_supported = BUS_NONE; + internal_buses_supported = BUS_NONE; msg_pdbg("Flash bus type is unknown (none)\n"); msg_pinfo("Something went wrong with bus type detection.\n"); goto out_msg; @@ -1323,7 +1322,6 @@ struct pci_dev *dev = NULL; int ret = -2; /* Nothing! */ int i; - char *s; /* Now let's try to find the chipset we have... */ for (i = 0; chipset_enables[i].vendor_name != NULL; i++) { @@ -1375,9 +1373,5 @@ } } - s = flashbuses_to_text(buses_supported); - msg_pinfo("This chipset supports the following protocols: %s.\n", s); - free(s); - return ret; } Index: flashrom-register_all_programmers/nicintel.c =================================================================== --- flashrom-register_all_programmers/nicintel.c (Revision 1457) +++ flashrom-register_all_programmers/nicintel.c (Arbeitskopie) @@ -43,6 +43,19 @@ #define CSR_FCR 0x0c +static const struct par_programmer par_programmer_nicintel = { + .chip_readb = nicintel_chip_readb, + .chip_readw = fallback_chip_readw, + .chip_readl = fallback_chip_readl, + .chip_readn = fallback_chip_readn, + .chip_writeb = nicintel_chip_writeb, + .chip_writew = fallback_chip_writew, + .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, + .map_flash_region = fallback_map, + .unmap_flash_region = fallback_unmap, +}; + static int nicintel_shutdown(void *data) { physunmap(nicintel_control_bar, NICINTEL_CONTROL_MEMMAP_SIZE); @@ -93,9 +106,8 @@ */ pci_rmmio_writew(0x0001, nicintel_control_bar + CSR_FCR); - buses_supported = BUS_PARALLEL; - max_rom_decode.parallel = NICINTEL_MEMMAP_SIZE; + register_par_programmer(&par_programmer_nicintel, BUS_PARALLEL); return 0; Index: flashrom-register_all_programmers/flashrom.c =================================================================== --- flashrom-register_all_programmers/flashrom.c (Revision 1457) +++ flashrom-register_all_programmers/flashrom.c (Arbeitskopie) @@ -66,16 +66,6 @@ { .name = "internal", .init = internal_init, - .map_flash_region = physmap, - .unmap_flash_region = physunmap, - .chip_readb = internal_chip_readb, - .chip_readw = internal_chip_readw, - .chip_readl = internal_chip_readl, - .chip_readn = internal_chip_readn, - .chip_writeb = internal_chip_writeb, - .chip_writew = internal_chip_writew, - .chip_writel = internal_chip_writel, - .chip_writen = fallback_chip_writen, .delay = internal_delay, }, #endif @@ -84,16 +74,6 @@ { .name = "dummy", .init = dummy_init, - .map_flash_region = dummy_map, - .unmap_flash_region = dummy_unmap, - .chip_readb = dummy_chip_readb, - .chip_readw = dummy_chip_readw, - .chip_readl = dummy_chip_readl, - .chip_readn = dummy_chip_readn, - .chip_writeb = dummy_chip_writeb, - .chip_writew = dummy_chip_writew, - .chip_writel = dummy_chip_writel, - .chip_writen = dummy_chip_writen, .delay = internal_delay, }, #endif @@ -102,16 +82,6 @@ { .name = "nic3com", .init = nic3com_init, - .map_flash_region = fallback_map, - .unmap_flash_region = fallback_unmap, - .chip_readb = nic3com_chip_readb, - .chip_readw = fallback_chip_readw, - .chip_readl = fallback_chip_readl, - .chip_readn = fallback_chip_readn, - .chip_writeb = nic3com_chip_writeb, - .chip_writew = fallback_chip_writew, - .chip_writel = fallback_chip_writel, - .chip_writen = fallback_chip_writen, .delay = internal_delay, }, #endif @@ -122,16 +92,6 @@ .name = "nicrealtek", //.name = "nicsmc1211", .init = nicrealtek_init, - .map_flash_region = fallback_map, - .unmap_flash_region = fallback_unmap, - .chip_readb = nicrealtek_chip_readb, - .chip_readw = fallback_chip_readw, - .chip_readl = fallback_chip_readl, - .chip_readn = fallback_chip_readn, - .chip_writeb = nicrealtek_chip_writeb, - .chip_writew = fallback_chip_writew, - .chip_writel = fallback_chip_writel, - .chip_writen = fallback_chip_writen, .delay = internal_delay, }, #endif @@ -140,16 +100,6 @@ { .name = "nicnatsemi", .init = nicnatsemi_init, - .map_flash_region = fallback_map, - .unmap_flash_region = fallback_unmap, - .chip_readb = nicnatsemi_chip_readb, - .chip_readw = fallback_chip_readw, - .chip_readl = fallback_chip_readl, - .chip_readn = fallback_chip_readn, - .chip_writeb = nicnatsemi_chip_writeb, - .chip_writew = fallback_chip_writew, - .chip_writel = fallback_chip_writel, - .chip_writen = fallback_chip_writen, .delay = internal_delay, }, #endif @@ -158,16 +108,6 @@ { .name = "gfxnvidia", .init = gfxnvidia_init, - .map_flash_region = fallback_map, - .unmap_flash_region = fallback_unmap, - .chip_readb = gfxnvidia_chip_readb, - .chip_readw = fallback_chip_readw, - .chip_readl = fallback_chip_readl, - .chip_readn = fallback_chip_readn, - .chip_writeb = gfxnvidia_chip_writeb, - .chip_writew = fallback_chip_writew, - .chip_writel = fallback_chip_writel, - .chip_writen = fallback_chip_writen, .delay = internal_delay, }, #endif @@ -176,16 +116,6 @@ { .name = "drkaiser", .init = drkaiser_init, - .map_flash_region = fallback_map, - .unmap_flash_region = fallback_unmap, - .chip_readb = drkaiser_chip_readb, - .chip_readw = fallback_chip_readw, - .chip_readl = fallback_chip_readl, - .chip_readn = fallback_chip_readn, - .chip_writeb = drkaiser_chip_writeb, - .chip_writew = fallback_chip_writew, - .chip_writel = fallback_chip_writel, - .chip_writen = fallback_chip_writen, .delay = internal_delay, }, #endif @@ -194,16 +124,6 @@ { .name = "satasii", .init = satasii_init, - .map_flash_region = fallback_map, - .unmap_flash_region = fallback_unmap, - .chip_readb = satasii_chip_readb, - .chip_readw = fallback_chip_readw, - .chip_readl = fallback_chip_readl, - .chip_readn = fallback_chip_readn, - .chip_writeb = satasii_chip_writeb, - .chip_writew = fallback_chip_writew, - .chip_writel = fallback_chip_writel, - .chip_writen = fallback_chip_writen, .delay = internal_delay, }, #endif @@ -212,16 +132,6 @@ { .name = "atahpt", .init = atahpt_init, - .map_flash_region = fallback_map, - .unmap_flash_region = fallback_unmap, - .chip_readb = atahpt_chip_readb, - .chip_readw = fallback_chip_readw, - .chip_readl = fallback_chip_readl, - .chip_readn = fallback_chip_readn, - .chip_writeb = atahpt_chip_writeb, - .chip_writew = fallback_chip_writew, - .chip_writel = fallback_chip_writel, - .chip_writen = fallback_chip_writen, .delay = internal_delay, }, #endif @@ -230,16 +140,6 @@ { .name = "ft2232_spi", .init = ft2232_spi_init, - .map_flash_region = fallback_map, - .unmap_flash_region = fallback_unmap, - .chip_readb = noop_chip_readb, - .chip_readw = fallback_chip_readw, - .chip_readl = fallback_chip_readl, - .chip_readn = fallback_chip_readn, - .chip_writeb = noop_chip_writeb, - .chip_writew = fallback_chip_writew, - .chip_writel = fallback_chip_writel, - .chip_writen = fallback_chip_writen, .delay = internal_delay, }, #endif @@ -248,16 +148,6 @@ { .name = "serprog", .init = serprog_init, - .map_flash_region = fallback_map, - .unmap_flash_region = fallback_unmap, - .chip_readb = serprog_chip_readb, - .chip_readw = fallback_chip_readw, - .chip_readl = fallback_chip_readl, - .chip_readn = serprog_chip_readn, - .chip_writeb = serprog_chip_writeb, - .chip_writew = fallback_chip_writew, - .chip_writel = fallback_chip_writel, - .chip_writen = fallback_chip_writen, .delay = serprog_delay, }, #endif @@ -266,16 +156,6 @@ { .name = "buspirate_spi", .init = buspirate_spi_init, - .map_flash_region = fallback_map, - .unmap_flash_region = fallback_unmap, - .chip_readb = noop_chip_readb, - .chip_readw = fallback_chip_readw, - .chip_readl = fallback_chip_readl, - .chip_readn = fallback_chip_readn, - .chip_writeb = noop_chip_writeb, - .chip_writew = fallback_chip_writew, - .chip_writel = fallback_chip_writel, - .chip_writen = fallback_chip_writen, .delay = internal_delay, }, #endif @@ -284,16 +164,6 @@ { .name = "dediprog", .init = dediprog_init, - .map_flash_region = fallback_map, - .unmap_flash_region = fallback_unmap, - .chip_readb = noop_chip_readb, - .chip_readw = fallback_chip_readw, - .chip_readl = fallback_chip_readl, - .chip_readn = fallback_chip_readn, - .chip_writeb = noop_chip_writeb, - .chip_writew = fallback_chip_writew, - .chip_writel = fallback_chip_writel, - .chip_writen = fallback_chip_writen, .delay = internal_delay, }, #endif @@ -302,16 +172,6 @@ { .name = "rayer_spi", .init = rayer_spi_init, - .map_flash_region = fallback_map, - .unmap_flash_region = fallback_unmap, - .chip_readb = noop_chip_readb, - .chip_readw = fallback_chip_readw, - .chip_readl = fallback_chip_readl, - .chip_readn = fallback_chip_readn, - .chip_writeb = noop_chip_writeb, - .chip_writew = fallback_chip_writew, - .chip_writel = fallback_chip_writel, - .chip_writen = fallback_chip_writen, .delay = internal_delay, }, #endif @@ -320,16 +180,6 @@ { .name = "nicintel", .init = nicintel_init, - .map_flash_region = fallback_map, - .unmap_flash_region = fallback_unmap, - .chip_readb = nicintel_chip_readb, - .chip_readw = fallback_chip_readw, - .chip_readl = fallback_chip_readl, - .chip_readn = fallback_chip_readn, - .chip_writeb = nicintel_chip_writeb, - .chip_writew = fallback_chip_writew, - .chip_writel = fallback_chip_writel, - .chip_writen = fallback_chip_writen, .delay = internal_delay, }, #endif @@ -338,16 +188,6 @@ { .name = "nicintel_spi", .init = nicintel_spi_init, - .map_flash_region = fallback_map, - .unmap_flash_region = fallback_unmap, - .chip_readb = noop_chip_readb, - .chip_readw = fallback_chip_readw, - .chip_readl = fallback_chip_readl, - .chip_readn = fallback_chip_readn, - .chip_writeb = noop_chip_writeb, - .chip_writew = fallback_chip_writew, - .chip_writel = fallback_chip_writel, - .chip_writen = fallback_chip_writen, .delay = internal_delay, }, #endif @@ -356,16 +196,6 @@ { .name = "ogp_spi", .init = ogp_spi_init, - .map_flash_region = fallback_map, - .unmap_flash_region = fallback_unmap, - .chip_readb = noop_chip_readb, - .chip_readw = fallback_chip_readw, - .chip_readl = fallback_chip_readl, - .chip_readn = fallback_chip_readn, - .chip_writeb = noop_chip_writeb, - .chip_writew = fallback_chip_writew, - .chip_writel = fallback_chip_writel, - .chip_writen = fallback_chip_writen, .delay = internal_delay, }, #endif @@ -374,16 +204,6 @@ { .name = "satamv", .init = satamv_init, - .map_flash_region = fallback_map, - .unmap_flash_region = fallback_unmap, - .chip_readb = satamv_chip_readb, - .chip_readw = fallback_chip_readw, - .chip_readl = fallback_chip_readl, - .chip_readn = fallback_chip_readn, - .chip_writeb = satamv_chip_writeb, - .chip_writew = fallback_chip_writew, - .chip_writel = fallback_chip_writel, - .chip_writen = fallback_chip_writen, .delay = internal_delay, }, #endif @@ -392,16 +212,6 @@ { .name = "linux_spi", .init = linux_spi_init, - .map_flash_region = fallback_map, - .unmap_flash_region = fallback_unmap, - .chip_readb = noop_chip_readb, - .chip_readw = fallback_chip_readw, - .chip_readl = fallback_chip_readl, - .chip_readn = fallback_chip_readn, - .chip_writeb = noop_chip_writeb, - .chip_writew = fallback_chip_writew, - .chip_writel = fallback_chip_writel, - .chip_writen = fallback_chip_writen, .delay = internal_delay, }, #endif @@ -502,53 +312,52 @@ void *programmer_map_flash_region(const char *descr, unsigned long phys_addr, size_t len) { - return programmer_table[programmer].map_flash_region(descr, - phys_addr, len); + return par_programmer->map_flash_region(descr, phys_addr, len); } void programmer_unmap_flash_region(void *virt_addr, size_t len) { - programmer_table[programmer].unmap_flash_region(virt_addr, len); + par_programmer->unmap_flash_region(virt_addr, len); } void chip_writeb(uint8_t val, chipaddr addr) { - programmer_table[programmer].chip_writeb(val, addr); + par_programmer->chip_writeb(val, addr); } void chip_writew(uint16_t val, chipaddr addr) { - programmer_table[programmer].chip_writew(val, addr); + par_programmer->chip_writew(val, addr); } void chip_writel(uint32_t val, chipaddr addr) { - programmer_table[programmer].chip_writel(val, addr); + par_programmer->chip_writel(val, addr); } void chip_writen(uint8_t *buf, chipaddr addr, size_t len) { - programmer_table[programmer].chip_writen(buf, addr, len); + par_programmer->chip_writen(buf, addr, len); } uint8_t chip_readb(const chipaddr addr) { - return programmer_table[programmer].chip_readb(addr); + return par_programmer->chip_readb(addr); } uint16_t chip_readw(const chipaddr addr) { - return programmer_table[programmer].chip_readw(addr); + return par_programmer->chip_readw(addr); } uint32_t chip_readl(const chipaddr addr) { - return programmer_table[programmer].chip_readl(addr); + return par_programmer->chip_readl(addr); } void chip_readn(uint8_t *buf, chipaddr addr, size_t len) { - programmer_table[programmer].chip_readn(buf, addr, len); + par_programmer->chip_readn(buf, addr, len); } void programmer_delay(int usecs) @@ -1156,7 +965,7 @@ return -1; #if CONFIG_INTERNAL == 1 - if (programmer_table[programmer].map_flash_region == physmap) + if (par_programmer->map_flash_region == physmap) snprintf(location, sizeof(location), "at physical address 0x%lx", base); else #endif Index: flashrom-register_all_programmers/programmer.c =================================================================== --- flashrom-register_all_programmers/programmer.c (Revision 1457) +++ flashrom-register_all_programmers/programmer.c (Arbeitskopie) @@ -19,7 +19,23 @@ */ #include "flash.h" +#include "programmer.h" +static const struct par_programmer par_programmer_none = { + .chip_readb = noop_chip_readb, + .chip_readw = fallback_chip_readw, + .chip_readl = fallback_chip_readl, + .chip_readn = fallback_chip_readn, + .chip_writeb = noop_chip_writeb, + .chip_writew = fallback_chip_writew, + .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, + .map_flash_region = fallback_map, + .unmap_flash_region = fallback_unmap, +}; + +const struct par_programmer *par_programmer = &par_programmer_none; + /* No-op shutdown() for programmers which don't need special handling */ int noop_shutdown(void) { @@ -96,3 +112,9 @@ buf[i] = chip_readb(addr + i); return; } + +void register_par_programmer(const struct par_programmer *pgm, const enum chipbustype buses) +{ + par_programmer = pgm; + buses_supported |= buses; +} Index: flashrom-register_all_programmers/programmer.h =================================================================== --- flashrom-register_all_programmers/programmer.h (Revision 1457) +++ flashrom-register_all_programmers/programmer.h (Arbeitskopie) @@ -91,18 +91,6 @@ int (*init) (void); - void * (*map_flash_region) (const char *descr, unsigned long phys_addr, - size_t len); - void (*unmap_flash_region) (void *virt_addr, size_t len); - - void (*chip_writeb) (uint8_t val, chipaddr addr); - void (*chip_writew) (uint16_t val, chipaddr addr); - void (*chip_writel) (uint32_t val, chipaddr addr); - void (*chip_writen) (uint8_t *buf, chipaddr addr, size_t len); - uint8_t (*chip_readb) (const chipaddr addr); - uint16_t (*chip_readw) (const chipaddr addr); - uint32_t (*chip_readl) (const chipaddr addr); - void (*chip_readn) (uint8_t *buf, const chipaddr addr, size_t len); void (*delay) (int usecs); }; @@ -304,6 +292,7 @@ extern int force_boardmismatch; void probe_superio(void); int register_superio(struct superio s); +extern enum chipbustype internal_buses_supported; int internal_init(void); void internal_chip_writeb(uint8_t val, chipaddr addr); void internal_chip_writew(uint16_t val, chipaddr addr); @@ -358,7 +347,23 @@ uint16_t fallback_chip_readw(const chipaddr addr); uint32_t fallback_chip_readl(const chipaddr addr); void fallback_chip_readn(uint8_t *buf, const chipaddr addr, size_t len); +struct par_programmer { + void (*chip_writeb) (uint8_t val, chipaddr addr); + void (*chip_writew) (uint16_t val, chipaddr addr); + void (*chip_writel) (uint32_t val, chipaddr addr); + void (*chip_writen) (uint8_t *buf, chipaddr addr, size_t len); + uint8_t (*chip_readb) (const chipaddr addr); + uint16_t (*chip_readw) (const chipaddr addr); + uint32_t (*chip_readl) (const chipaddr addr); + void (*chip_readn) (uint8_t *buf, const chipaddr addr, size_t len); + void *(*map_flash_region) (const char *descr, unsigned long phys_addr, + size_t len); + void (*unmap_flash_region) (void *virt_addr, size_t len); +}; +extern const struct par_programmer *par_programmer; +void register_par_programmer(const struct par_programmer *pgm, const enum chipbustype buses); + /* dummyflasher.c */ #if CONFIG_DUMMY == 1 int dummy_init(void); @@ -601,6 +606,19 @@ int wbsio_check_for_spi(void); #endif +/* opaque.c */ +struct opaque_programmer { + int max_data_read; + int max_data_write; + /* Specific functions for this programmer */ + int (*probe) (struct flashchip *flash); + int (*read) (struct flashchip *flash, uint8_t *buf, int start, int len); + int (*write) (struct flashchip *flash, uint8_t *buf, int start, int len); + int (*erase) (struct flashchip *flash, unsigned int blockaddr, unsigned int blocklen); +}; +extern const struct opaque_programmer *opaque_programmer; +void register_opaque_programmer(const struct opaque_programmer *pgm); + /* serprog.c */ #if CONFIG_SERPROG == 1 int serprog_init(void); Index: flashrom-register_all_programmers/chipdrivers.h =================================================================== --- flashrom-register_all_programmers/chipdrivers.h (Revision 1457) +++ flashrom-register_all_programmers/chipdrivers.h (Arbeitskopie) @@ -58,6 +58,12 @@ int spi_write_chunked(struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize); int spi_aai_write(struct flashchip *flash, uint8_t *buf, int start, int len); +/* opaque.c */ +int probe_opaque(struct flashchip *flash); +int read_opaque(struct flashchip *flash, uint8_t *buf, int start, int len); +int write_opaque(struct flashchip *flash, uint8_t *buf, int start, int len); +int erase_opaque(struct flashchip *flash, unsigned int blockaddr, unsigned int blocklen); + /* a25.c */ int spi_prettyprint_status_register_amic_a25l05p(struct flashchip *flash); int spi_prettyprint_status_register_amic_a25l40p(struct flashchip *flash); Index: flashrom-register_all_programmers/print.c =================================================================== --- flashrom-register_all_programmers/print.c (Revision 1457) +++ flashrom-register_all_programmers/print.c (Arbeitskopie) @@ -49,6 +49,8 @@ ret = strcat_realloc(ret, "FWH, "); if (bustype & BUS_SPI) ret = strcat_realloc(ret, "SPI, "); + if (bustype & BUS_PROG) + ret = strcat_realloc(ret, "Programmer-specific, "); if (bustype == BUS_NONE) ret = strcat_realloc(ret, "None, "); } Index: flashrom-register_all_programmers/board_enable.c =================================================================== --- flashrom-register_all_programmers/board_enable.c (Revision 1457) +++ flashrom-register_all_programmers/board_enable.c (Arbeitskopie) @@ -425,7 +425,7 @@ /* Check if at least one flash segment is enabled. */ if (tmp & 0xf0) { /* The IT8705F will respond to LPC cycles and translate them. */ - buses_supported = BUS_PARALLEL; + internal_buses_supported = BUS_PARALLEL; /* Flash ROM I/F Writes Enable */ tmp |= 0x04; msg_pdbg("Enabling IT8705F flash ROM interface write.\n"); -- http://www.hailfinger.org/ From c-d.hailfinger.devel.2006 at gmx.net Wed Nov 2 04:53:22 2011 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Wed, 02 Nov 2011 04:53:22 +0100 Subject: [flashrom] [RFC] Add struct flashchip * everywhere Message-ID: <4EB0BEB2.1040701@gmx.net> We need a way to identify which registered programmer should be used for a given access. Especially for cases where multiple programmers for the same bus type are registered (e.g. IT87+MCP79 SPI or Dual BIOS solutions), probing has to happen on each programmer. Somehow we have to tell the dispatcher (spi_send_command etc.) this information, and the only way to get the info to the dispatcher is either an ugly global variable which makes dealing with multiple flash chips and multiple bus probing really messy, or we store the info inside struct flashchip. Given that struct flashchip is passed around almost everywhere already, it is the natural location for such information and only very few function prototypes have to be changed to handle this. I have a prototype patch in the queue, but it's only half ready. If there is any interest, I can send the patch as is to give you an option to shoot it down while it is still unfinished. Regards, Carl-Daniel -- http://www.hailfinger.org/ From yarpr at pochta.ru Wed Nov 2 11:11:53 2011 From: yarpr at pochta.ru (yarpr at pochta.ru) Date: Wed, 02 Nov 2011 14:11:53 +0400 Subject: [flashrom] (no subject) Message-ID: ­­­­­ _ Only here you can find h­­­­a.pp­­­in­­­es­­­­­s in pe­­r­­­­­so­­­­nal r_el­­­­­­at­­­­­­io­ns­­­­­­­hi­­ps ­­­ -------------- next part -------------- An HTML attachment was scrubbed... URL: From stefan.tauner at student.tuwien.ac.at Wed Nov 2 13:41:27 2011 From: stefan.tauner at student.tuwien.ac.at (Stefan Tauner) Date: Wed, 2 Nov 2011 13:41:27 +0100 Subject: [flashrom] [RFC] Add struct flashchip * everywhere In-Reply-To: <4EB0BEB2.1040701@gmx.net> References: <4EB0BEB2.1040701@gmx.net> Message-ID: <201111021241.pA2CfGHH021689@mail2.student.tuwien.ac.at> On Wed, 02 Nov 2011 04:53:22 +0100 Carl-Daniel Hailfinger wrote: > We need a way to identify which registered programmer should be used for > a given access. Especially for cases where multiple programmers for the > same bus type are registered (e.g. IT87+MCP79 SPI or Dual BIOS > solutions), probing has to happen on each programmer. Somehow we have to > tell the dispatcher (spi_send_command etc.) this information, and the > only way to get the info to the dispatcher is either an ugly global > variable which makes dealing with multiple flash chips and multiple bus > probing really messy, or we store the info inside struct flashchip. > Given that struct flashchip is passed around almost everywhere already, > it is the natural location for such information and only very few > function prototypes have to be changed to handle this. > > I have a prototype patch in the queue, but it's only half ready. If > there is any interest, I can send the patch as is to give you an option > to shoot it down while it is still unfinished. changing prototypes should be no concern in such decisions imho. it is a one-time change that may break some patches in the queue (which is no problem, because there should be only a short queue, right? ;) but this should not play a major role in the design. the reason i bring this argument up explicitly is that i think the name "flashchip" may get a bit abused and changing it might be better. that's not necessarily the case, i just wanted to criticize something, because else it sounds good at this level of detail ;) another layer of redirection is - as always - also a possibility: introducing a new struct with pointers to the actual chip and the programmer to be used (and other information related to the actual situation/probing... e.g. access right ranges). but that's probably not needed (yet) and the splitting could be done later anyway if need be. OTOH if it is clear that there will be more information stuffed into struct flashchip, that is not really static and does not need to/should not reside in flashchips.c/struct flashchip, we may better discuss a separation now(?). -- Kind regards/Mit freundlichen Gr??en, Stefan Tauner From stefan.tauner at student.tuwien.ac.at Wed Nov 2 13:52:28 2011 From: stefan.tauner at student.tuwien.ac.at (Stefan Tauner) Date: Wed, 2 Nov 2011 13:52:28 +0100 Subject: [flashrom] Flashrom report In-Reply-To: References: <201110270843.p9R8hnJ5019855@mail2.student.tuwien.ac.at> Message-ID: <201111021252.pA2CqHFo002346@mail2.student.tuwien.ac.at> On Thu, 27 Oct 2011 11:27:57 +0200 Piotr Czepek wrote: > Found chipset "VIA VT8601/VT8601A" with PCI ID 1106:0601. > This chipset is marked as untested. If you are using an up-to-date version > of flashrom please email a report to flashrom at flashrom.org including a > verbose (-V) log. Thank you! > Enabling flash write... OK - searching further chips. > Found chipset "VIA VT8601T" with PCI ID 1106:8601. > This chipset is marked as untested. If you are using an up-to-date version > of flashrom please email a report to flashrom at flashrom.org including a > verbose (-V) log. Thank you! > Enabling flash write... OK - searching further chips. > Found chipset "VIA VT8231" with PCI ID 1106:8231. > This chipset is marked as untested. If you are using an up-to-date version > of flashrom please email a report to flashrom at flashrom.org including a > verbose (-V) log. Thank you! can someone please shed some light onto this VIA stuff? i see how this is done in source, but not why. just because we need to write one register in the northbridge(s) to disable "byte merging"? should i just mark all of them as tested? or should i leave the northbridges marked as untested because we did not enter the "if (byte merge enabled)" branch? -- Kind regards/Mit freundlichen Gr??en, Stefan Tauner From vidwer at gmail.com Wed Nov 2 14:31:35 2011 From: vidwer at gmail.com (Idwer Vollering) Date: Wed, 2 Nov 2011 14:31:35 +0100 Subject: [flashrom] Programming an A25L40 EEPROM In-Reply-To: References: Message-ID: 2011/10/27 Arup Basak : > I have the 512KB bios file, and was trying to program it with flashrom and > buspirate. > Looks like one version of flashrom says "missing libftdi.dll" while another > version says programmer buspirate_spi not supported. Can you find out which version/build showed those messages? > Can you give me link of any latest version. I have tried to copy the > libftdi.dll into the flashrom directory, also tried 'regsrv32 libftdi.dll' > in a command-box (where regsrv32 looks to be absent in Windows 7) This 7z file has (should have) the required dependencies: http://ra.openbios.org/~idwer/flashrom/flashrom_v0.9.4-r1457_mingw_win32_libftdi_libusb.7z If that does not work, install libusb-win32: http://www.libusb.org/wiki/libusb-win32 > > One more thing, when I hooked up the SPI chip to buspirate, if I use > terminal mode of buspirate and set correct mode, then if I try to read some > block using CS enables, I get 0x00 and if I keep CS disabled I get 0xFF. > I've tried to write anything with both CS enabled and disabled. But values > are read as above. > Maybe I've settled up wrong mode while trying to access EEPROM from > buspirate terminal mode. . I've worked with mode 5 spi, 125khz, Clock > polarity:Idle low , Output clock edge:Active to idle, Input sample > phase:middle, Output mode: Normal (H=3.3V, L=GND), W(power supplies on). > I didn't need to do so because for flashing my BIOS chip, I am trying to use > flashrom. > This is the fresh chip I bought for recovery. > http://in.rsdelivers.com/product/amic-technology/a25l040m-f/spi-flash-4mb-sop8-3v-4mx1/0573498.asp > Note: The BIOS chips is of my tablet, and not PC, so no problem if it takes > few days to resolve issues and program it. It isn't much serious case when > someone corrupts motherboard's BIOS. I know flashrom's support is free and > takes few hours to get reply. It's not an issue in my case. > > _______________________________________________ > flashrom mailing list > flashrom at flashrom.org > http://www.flashrom.org/mailman/listinfo/flashrom > From stefan.tauner at student.tuwien.ac.at Wed Nov 2 15:15:44 2011 From: stefan.tauner at student.tuwien.ac.at (Stefan Tauner) Date: Wed, 2 Nov 2011 15:15:44 +0100 Subject: [flashrom] [PATCH] Add board enable for Sun Ultra 40 M2 Message-ID: <1320243344-5416-1-git-send-email-stefan.tauner@student.tuwien.ac.at> Success report: http://paste.flashrom.org/view.php?id=889 (mostly) written by Joshua Roy (please add your signed-off tag) and Acked-by: Stefan Tauner --- board_enable.c | 33 +++++++++++++++++++++++++++++++++ print.c | 1 + 2 files changed, 34 insertions(+), 0 deletions(-) diff --git a/board_enable.c b/board_enable.c index 1874459..fe2f021 100644 --- a/board_enable.c +++ b/board_enable.c @@ -1051,6 +1051,38 @@ static int nvidia_mcp_gpio3b_raise(void) /* * Suited for: + * - Sun Ultra 40 M2: Dual Socket F (1207) + MCP55 + */ +static int board_sun_ultra_40_m2(void) +{ + int ret; + uint8_t reg; + uint16_t base; + struct pci_dev *dev; + + ret = nvidia_mcp_gpio4_lower(); + if (ret) + return ret; + + dev = pci_dev_find(0x10de, 0x0364); /* NVIDIA MCP55 LPC bridge */ + if (!dev) { + msg_perr("\nERROR: NVIDIA MCP55 LPC bridge not found.\n"); + return -1; + } + + base = pci_read_word(dev, 0xb4); /* some IO BAR? */ + if (!base) + return -1; + + reg = INB(base + 0x4b); + reg |= 0x10; + OUTB(reg, base + 0x4b); + + return 0; +} + +/* + * Suited for: * - Artec Group DBE61 and DBE62 */ static int board_artecgroup_dbe6x(void) @@ -2109,6 +2141,7 @@ const struct board_match board_matches[] = { {0x1106, 0x3104, 0x1297, 0xa238, 0x1106, 0x3059, 0x1297, 0xc063, NULL, NULL, NULL, P3, "Shuttle", "AK38N", 256, OK, NULL}, {0x10DE, 0x0050, 0x1297, 0x5036, 0x1412, 0x1724, 0x1297, 0x5036, NULL, NULL, NULL, P3, "Shuttle", "FN25", 0, OK, board_shuttle_fn25}, {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x3058, 0x15DD, 0x7609, NULL, NULL, NULL, P3, "Soyo", "SY-7VCA", 0, OK, via_apollo_gpo0_lower}, + {0x10de, 0x0364, 0x108e, 0x6676, 0x10de, 0x0369, 0x108e, 0x6676, "^Sun Ultra 40 M2", NULL, NULL, P3, "Sun", "Ultra 40 M2", 0, OK, board_sun_ultra_40_m2}, {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x0596, 0x1106, 0, NULL, NULL, NULL, P3, "Tekram", "P6Pro-A5", 256, OK, NULL}, {0x1106, 0x3123, 0x1106, 0x3123, 0x1106, 0x3059, 0x1106, 0x4161, NULL, NULL, NULL, P3, "Termtek", "TK-3370 (Rev:2.5B)", 0, OK, w836xx_memw_enable_4e}, {0x8086, 0x1076, 0x8086, 0x1176, 0x1106, 0x3059, 0x10f1, 0x2498, NULL, NULL, NULL, P3, "Tyan", "S2498 (Tomcat K7M)", 0, OK, w836xx_memw_enable_2e}, diff --git a/print.c b/print.c index 05eee9f..91288ee 100644 --- a/print.c +++ b/print.c @@ -846,6 +846,7 @@ const struct board_info boards_known[] = { B("Sun", "Fire x4200", 0, "http://www.sun.com/servers/entry/x4200/", "No public report found. May work now."), B("Sun", "Fire x4540", 0, "http://www.sun.com/servers/x64/x4540/", "No public report found. May work now."), B("Sun", "Fire x4600", 0, "http://www.sun.com/servers/x64/x4600/", "No public report found. May work now."), + B("Sun", "Ultra 40 M2", 1, NULL, NULL), B("Supermicro", "H8QC8", 1, "http://www.supermicro.com/Aplus/motherboard/Opteron/nforce/H8QC8.cfm", NULL), B("Supermicro", "X5DP8-G2", 1, "http://www.supermicro.com/products/motherboard/Xeon/E7501/X5DP8-G2.cfm", NULL), B("Supermicro", "X7DBT-INF", 1, "http://www.supermicro.com/products/motherboard/Xeon1333/5000P/X7DBT-INF.cfm", NULL), -- 1.7.1 From roysjosh at gmail.com Wed Nov 2 15:25:20 2011 From: roysjosh at gmail.com (Joshua Roys) Date: Wed, 02 Nov 2011 10:25:20 -0400 Subject: [flashrom] [PATCH] Add board enable for Sun Ultra 40 M2 In-Reply-To: <1320243344-5416-1-git-send-email-stefan.tauner@student.tuwien.ac.at> References: <1320243344-5416-1-git-send-email-stefan.tauner@student.tuwien.ac.at> Message-ID: <4EB152D0.10705@gmail.com> On 11/02/2011 10:15 AM, Stefan Tauner wrote: > Success report: > http://paste.flashrom.org/view.php?id=889 > Signed-off-by: Joshua Roys Stefan, feel free to sign-off also, if you want. > Acked-by: Stefan Tauner > --- > board_enable.c | 33 +++++++++++++++++++++++++++++++++ > print.c | 1 + > 2 files changed, 34 insertions(+), 0 deletions(-) > > diff --git a/board_enable.c b/board_enable.c > index 1874459..fe2f021 100644 > --- a/board_enable.c > +++ b/board_enable.c > @@ -1051,6 +1051,38 @@ static int nvidia_mcp_gpio3b_raise(void) > > /* > * Suited for: > + * - Sun Ultra 40 M2: Dual Socket F (1207) + MCP55 > + */ > +static int board_sun_ultra_40_m2(void) > +{ > + int ret; > + uint8_t reg; > + uint16_t base; > + struct pci_dev *dev; > + > + ret = nvidia_mcp_gpio4_lower(); > + if (ret) > + return ret; > + > + dev = pci_dev_find(0x10de, 0x0364); /* NVIDIA MCP55 LPC bridge */ > + if (!dev) { > + msg_perr("\nERROR: NVIDIA MCP55 LPC bridge not found.\n"); > + return -1; > + } > + > + base = pci_read_word(dev, 0xb4); /* some IO BAR? */ > + if (!base) > + return -1; > + > + reg = INB(base + 0x4b); > + reg |= 0x10; > + OUTB(reg, base + 0x4b); > + > + return 0; > +} > + > +/* > + * Suited for: > * - Artec Group DBE61 and DBE62 > */ > static int board_artecgroup_dbe6x(void) > @@ -2109,6 +2141,7 @@ const struct board_match board_matches[] = { > {0x1106, 0x3104, 0x1297, 0xa238, 0x1106, 0x3059, 0x1297, 0xc063, NULL, NULL, NULL, P3, "Shuttle", "AK38N", 256, OK, NULL}, > {0x10DE, 0x0050, 0x1297, 0x5036, 0x1412, 0x1724, 0x1297, 0x5036, NULL, NULL, NULL, P3, "Shuttle", "FN25", 0, OK, board_shuttle_fn25}, > {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x3058, 0x15DD, 0x7609, NULL, NULL, NULL, P3, "Soyo", "SY-7VCA", 0, OK, via_apollo_gpo0_lower}, > + {0x10de, 0x0364, 0x108e, 0x6676, 0x10de, 0x0369, 0x108e, 0x6676, "^Sun Ultra 40 M2", NULL, NULL, P3, "Sun", "Ultra 40 M2", 0, OK, board_sun_ultra_40_m2}, > {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x0596, 0x1106, 0, NULL, NULL, NULL, P3, "Tekram", "P6Pro-A5", 256, OK, NULL}, > {0x1106, 0x3123, 0x1106, 0x3123, 0x1106, 0x3059, 0x1106, 0x4161, NULL, NULL, NULL, P3, "Termtek", "TK-3370 (Rev:2.5B)", 0, OK, w836xx_memw_enable_4e}, > {0x8086, 0x1076, 0x8086, 0x1176, 0x1106, 0x3059, 0x10f1, 0x2498, NULL, NULL, NULL, P3, "Tyan", "S2498 (Tomcat K7M)", 0, OK, w836xx_memw_enable_2e}, > diff --git a/print.c b/print.c > index 05eee9f..91288ee 100644 > --- a/print.c > +++ b/print.c > @@ -846,6 +846,7 @@ const struct board_info boards_known[] = { > B("Sun", "Fire x4200", 0, "http://www.sun.com/servers/entry/x4200/", "No public report found. May work now."), > B("Sun", "Fire x4540", 0, "http://www.sun.com/servers/x64/x4540/", "No public report found. May work now."), > B("Sun", "Fire x4600", 0, "http://www.sun.com/servers/x64/x4600/", "No public report found. May work now."), > + B("Sun", "Ultra 40 M2", 1, NULL, NULL), > B("Supermicro", "H8QC8", 1, "http://www.supermicro.com/Aplus/motherboard/Opteron/nforce/H8QC8.cfm", NULL), > B("Supermicro", "X5DP8-G2", 1, "http://www.supermicro.com/products/motherboard/Xeon/E7501/X5DP8-G2.cfm", NULL), > B("Supermicro", "X7DBT-INF", 1, "http://www.supermicro.com/products/motherboard/Xeon1333/5000P/X7DBT-INF.cfm", NULL), From svn at flashrom.org Wed Nov 2 15:31:30 2011 From: svn at flashrom.org (repository service) Date: Wed, 02 Nov 2011 15:31:30 +0100 Subject: [flashrom] [commit] r1458 - trunk Message-ID: Author: stefanct Date: Wed Nov 2 15:31:18 2011 New Revision: 1458 URL: http://flashrom.org/trac/flashrom/changeset/1458 Log: Add board enable for Sun Ultra 40 M2 Failure report with logs: http://www.flashrom.org/pipermail/flashrom/2011-October/008158.html Success report: http://paste.flashrom.org/view.php?id=889 Signed-off-by: Joshua Roys Acked-by: Stefan Tauner Modified: trunk/board_enable.c trunk/print.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Sun Oct 23 00:01:09 2011 (r1457) +++ trunk/board_enable.c Wed Nov 2 15:31:18 2011 (r1458) @@ -1051,6 +1051,38 @@ /* * Suited for: + * - Sun Ultra 40 M2: Dual Socket F (1207) + MCP55 + */ +static int board_sun_ultra_40_m2(void) +{ + int ret; + uint8_t reg; + uint16_t base; + struct pci_dev *dev; + + ret = nvidia_mcp_gpio4_lower(); + if (ret) + return ret; + + dev = pci_dev_find(0x10de, 0x0364); /* NVIDIA MCP55 LPC bridge */ + if (!dev) { + msg_perr("\nERROR: NVIDIA MCP55 LPC bridge not found.\n"); + return -1; + } + + base = pci_read_word(dev, 0xb4); /* some IO BAR? */ + if (!base) + return -1; + + reg = INB(base + 0x4b); + reg |= 0x10; + OUTB(reg, base + 0x4b); + + return 0; +} + +/* + * Suited for: * - Artec Group DBE61 and DBE62 */ static int board_artecgroup_dbe6x(void) @@ -2109,6 +2141,7 @@ {0x1106, 0x3104, 0x1297, 0xa238, 0x1106, 0x3059, 0x1297, 0xc063, NULL, NULL, NULL, P3, "Shuttle", "AK38N", 256, OK, NULL}, {0x10DE, 0x0050, 0x1297, 0x5036, 0x1412, 0x1724, 0x1297, 0x5036, NULL, NULL, NULL, P3, "Shuttle", "FN25", 0, OK, board_shuttle_fn25}, {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x3058, 0x15DD, 0x7609, NULL, NULL, NULL, P3, "Soyo", "SY-7VCA", 0, OK, via_apollo_gpo0_lower}, + {0x10de, 0x0364, 0x108e, 0x6676, 0x10de, 0x0369, 0x108e, 0x6676, "^Sun Ultra 40 M2", NULL, NULL, P3, "Sun", "Ultra 40 M2", 0, OK, board_sun_ultra_40_m2}, {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x0596, 0x1106, 0, NULL, NULL, NULL, P3, "Tekram", "P6Pro-A5", 256, OK, NULL}, {0x1106, 0x3123, 0x1106, 0x3123, 0x1106, 0x3059, 0x1106, 0x4161, NULL, NULL, NULL, P3, "Termtek", "TK-3370 (Rev:2.5B)", 0, OK, w836xx_memw_enable_4e}, {0x8086, 0x1076, 0x8086, 0x1176, 0x1106, 0x3059, 0x10f1, 0x2498, NULL, NULL, NULL, P3, "Tyan", "S2498 (Tomcat K7M)", 0, OK, w836xx_memw_enable_2e}, Modified: trunk/print.c ============================================================================== --- trunk/print.c Sun Oct 23 00:01:09 2011 (r1457) +++ trunk/print.c Wed Nov 2 15:31:18 2011 (r1458) @@ -846,6 +846,7 @@ B("Sun", "Fire x4200", 0, "http://www.sun.com/servers/entry/x4200/", "No public report found. May work now."), B("Sun", "Fire x4540", 0, "http://www.sun.com/servers/x64/x4540/", "No public report found. May work now."), B("Sun", "Fire x4600", 0, "http://www.sun.com/servers/x64/x4600/", "No public report found. May work now."), + B("Sun", "Ultra 40 M2", 1, "http://download.oracle.com/docs/cd/E19127-01/ultra40.ws/820-0123-13/intro.html", NULL), B("Supermicro", "H8QC8", 1, "http://www.supermicro.com/Aplus/motherboard/Opteron/nforce/H8QC8.cfm", NULL), B("Supermicro", "X5DP8-G2", 1, "http://www.supermicro.com/products/motherboard/Xeon/E7501/X5DP8-G2.cfm", NULL), B("Supermicro", "X7DBT-INF", 1, "http://www.supermicro.com/products/motherboard/Xeon1333/5000P/X7DBT-INF.cfm", NULL), From stefan.tauner at student.tuwien.ac.at Wed Nov 2 15:33:52 2011 From: stefan.tauner at student.tuwien.ac.at (Stefan Tauner) Date: Wed, 2 Nov 2011 15:33:52 +0100 Subject: [flashrom] Flashrom fails to write - Sun Ultra 40 M2 In-Reply-To: References: Message-ID: <201111021433.pA2EXdGl026006@mail2.student.tuwien.ac.at> On Tue, 25 Oct 2011 11:29:45 -0700 Nick wrote: > DMI string system-manufacturer: "Sun Microsystems" > DMI string system-product-name: "Sun Ultra 40 M2 Workstation" > DMI string system-version: "11" > DMI string baseboard-manufacturer: "Sun Microsystems" > DMI string baseboard-product-name: "Sun Ultra 40 M2 Workstation" > DMI string baseboard-version: "50" > > nForce Pro 3600 / MCP55, SMSC SuperIO > > Verbose output when flashing coreboot - > http://paste.flashrom.org/view.php?id=880 > Verbose output when flashing original Sun BIOS image - > http://paste.flashrom.org/view.php?id=881 > > lspci -nnvvvxxx output - http://paste.flashrom.org/view.php?id=883 > superiotool -deV output - http://paste.flashrom.org/view.php?id=884 > > Original Sun Ultra 40 M2 BIOS image - > http://paste.flashrom.org/view.php?id=882 hey there, as you know we have a patch to get this working. i have committed it to our repository moments ago so that board will be supported from now (r1458) on. gl with coreboot ;) -- Kind regards/Mit freundlichen Gr??en, Stefan Tauner From stefan.tauner at student.tuwien.ac.at Wed Nov 2 15:35:05 2011 From: stefan.tauner at student.tuwien.ac.at (Stefan Tauner) Date: Wed, 2 Nov 2011 15:35:05 +0100 Subject: [flashrom] [PATCH] Add board enable for Sun Ultra 40 M2 In-Reply-To: <4EB152D0.10705@gmail.com> References: <1320243344-5416-1-git-send-email-stefan.tauner@student.tuwien.ac.at> <4EB152D0.10705@gmail.com> Message-ID: <201111021434.pA2EYrOX027606@mail2.student.tuwien.ac.at> On Wed, 02 Nov 2011 10:25:20 -0400 Joshua Roys wrote: > Signed-off-by: Joshua Roys thanks! committed (with an URL thanks to idwer) in r1458 -- Kind regards/Mit freundlichen Gr??en, Stefan Tauner From nochristrequired at gmail.com Wed Nov 2 16:56:38 2011 From: nochristrequired at gmail.com (Nick) Date: Wed, 2 Nov 2011 08:56:38 -0700 Subject: [flashrom] Flashrom fails to write - Sun Ultra 40 M2 In-Reply-To: <201111021433.pA2EXdGl026006@mail2.student.tuwien.ac.at> References: <201111021433.pA2EXdGl026006@mail2.student.tuwien.ac.at> Message-ID: Thanks Stefan! I saw that on IRC earlier. Since the code has been refactored, I will pull from svn, compile, and retest when I get home. Also, I am still interested in donating. Both you and Roy really helped me out with this and I'm very appreciative. I've also been hanging around #flashrom in case there's any way I can contribute to the project. Thanks again, Nick On Wed, Nov 2, 2011 at 7:33 AM, Stefan Tauner < stefan.tauner at student.tuwien.ac.at> wrote: > On Tue, 25 Oct 2011 11:29:45 -0700 > Nick wrote: > > > DMI string system-manufacturer: "Sun Microsystems" > > DMI string system-product-name: "Sun Ultra 40 M2 Workstation" > > DMI string system-version: "11" > > DMI string baseboard-manufacturer: "Sun Microsystems" > > DMI string baseboard-product-name: "Sun Ultra 40 M2 Workstation" > > DMI string baseboard-version: "50" > > > > nForce Pro 3600 / MCP55, SMSC SuperIO > > > > Verbose output when flashing coreboot - > > http://paste.flashrom.org/view.php?id=880 > > Verbose output when flashing original Sun BIOS image - > > http://paste.flashrom.org/view.php?id=881 > > > > lspci -nnvvvxxx output - http://paste.flashrom.org/view.php?id=883 > > superiotool -deV output - http://paste.flashrom.org/view.php?id=884 > > > > Original Sun Ultra 40 M2 BIOS image - > > http://paste.flashrom.org/view.php?id=882 > > hey there, > > as you know we have a patch to get this working. i have committed it to > our repository moments ago so that board will be supported from now > (r1458) on. gl with coreboot ;) > > -- > Kind regards/Mit freundlichen Gr??en, Stefan Tauner > -------------- next part -------------- An HTML attachment was scrubbed... URL: From flashrom at mkarcher.dialup.fu-berlin.de Wed Nov 2 18:29:57 2011 From: flashrom at mkarcher.dialup.fu-berlin.de (Michael Karcher) Date: Wed, 02 Nov 2011 18:29:57 +0100 Subject: [flashrom] [PATCH 1/5] Add opaque programmer registration infrastructure. In-Reply-To: <1319150349-24326-2-git-send-email-stefan.tauner@student.tuwien.ac.at> References: <1319150349-24326-1-git-send-email-stefan.tauner@student.tuwien.ac.at> <1319150349-24326-2-git-send-email-stefan.tauner@student.tuwien.ac.at> Message-ID: <1320254997.12407.12.camel@localhost> Am Freitag, den 21.10.2011, 00:39 +0200 schrieb Stefan Tauner: > diff --git a/flash.h b/flash.h > index 535c1b8..8ad2845 100644 > --- a/flash.h > +++ b/flash.h > @@ -62,8 +62,9 @@ enum chipbustype { > BUS_LPC = 1 << 1, > BUS_FWH = 1 << 2, > BUS_SPI = 1 << 3, > + BUS_PROG = 1 << 4, > BUS_NONSPI = BUS_PARALLEL | BUS_LPC | BUS_FWH, > - BUS_UNKNOWN = BUS_PARALLEL | BUS_LPC | BUS_FWH | BUS_SPI, > + BUS_UNKNOWN = BUS_PARALLEL | BUS_LPC | BUS_FWH | BUS_SPI | BUS_PROG, We don't need BUS_UNKNOWN. It is referenced only in flashbuses_to_text. Having a programmer being both opaque and non-opaque seems to be as useless as defining that a chip "might also be accessed through an opaque interface". In the case of opaque interfaces, we don't care about the chip type - so I don't see any use case for BUS_UNKNOWN, even more after adding BUS_PROG. > }; > +#if defined(CONFIG_INTERNAL) && (defined(__i386__) || defined(__x86_64__)) > + { > + .vendor = "Programmer", > + .name = "Opaque flash chip", > + .bustype = BUS_PROG, > + .manufacture_id = PROGMANUF_ID, > + .model_id = PROGDEV_ID, > + .total_size = 0, > + .page_size = 256, > + /* probe is assumed to work, rest will be filled in by probe */ > + .tested = TEST_OK_PROBE, > + .probe = probe_opaque, > + /* eraseblock sizes will be set by the probing function */ > + .block_erasers = > + { > + { > + .block_erase = erase_opaque, > + } > + }, > + .write = write_opaque, > + .read = read_opaque, > + }, > +#endif // defined(CONFIG_INTERNAL) && (defined(__i386__) || defined(__x86_64__)) Why do we need any prerequisite for the opaque programmer? It should work outside of x86(-64), too, depending on which opaque backend is used. I guess this #if is there because at the moment, the only opaque programmer is the ICH9 stuff, but wouldn't a define NEED_OPAQUE that is set in the include file as soon as any programmer based on the opaque programmer is selected be more sensible? > @@ -9005,6 +9027,7 @@ const struct flashchip flashchips[] = { > .probe = probe_spi_rdid, > .write = NULL, > }, > + > { > .vendor = "Generic", > .name = "unknown SPI chip (REMS)", Unrelated change - you might have it in accidentally. > +/* > + * Contains the opaque programmer framework. > + * An opaque programmer is a programmer which does not provide direct access > + * to the flash chip and which abstracts all flash chip properties into a > + * programmer specific interface. > + */ > + > +#include > +#include > +#include "flash.h" > +#include "flashchips.h" > +#include "chipdrivers.h" > +#include "programmer.h" > + > +const struct opaque_programmer opaque_programmer_none = { > + .max_data_read = MAX_DATA_UNSPECIFIED, > + .max_data_write = MAX_DATA_UNSPECIFIED, > + .probe = NULL, > + .read = NULL, You are missing ".erase = NULL" here. > + .write = NULL, > +}; > + > +const struct opaque_programmer *opaque_programmer = &opaque_programmer_none; > + > +int probe_opaque(struct flashchip *flash) > +{ > + if (!opaque_programmer->probe) { > + msg_perr("%s called, but this is not an opaque programmer. " > + "Please report a bug at flashrom at flashrom.org\n", > + __func__); I don't really like the error message, I would prefer "%s called without register_opaque" or something like that. > +void register_opaque_programmer(const struct opaque_programmer *pgm) > +{ > + opaque_programmer = pgm; > + buses_supported |= BUS_PROG; > +} You might want to check that the function pointers in pgm are not NULL, to make the suggested error message "without register_opaque" more apt. Otherwise, the patch looks good to me. This is Acked-By: Michael Karcher If you feel confident you didn't mess up anything, feel free to re-use the ack after minor edits. Regards, Michael Karcher From stefan.tauner at student.tuwien.ac.at Wed Nov 2 22:39:45 2011 From: stefan.tauner at student.tuwien.ac.at (Stefan Tauner) Date: Wed, 2 Nov 2011 22:39:45 +0100 Subject: [flashrom] Successful test on Asus P5K-VM In-Reply-To: References: Message-ID: <201111022139.pA2LdQTd020003@mail2.student.tuwien.ac.at> On Mon, 31 Oct 2011 20:11:54 +0100 Grischa Ebinger wrote: > Hello, > > I was able to successfully reflash the BIOS of a P5K-VM motherboard > with flashrom-0.9.4. It recognized 2 different flash chips (AT25DF081A > and AT26DF081A) at the same address. I selected the first of the two > chipsets. > > I wasn't sure if flashrom did support my hardware. According to your > wiki it wasn't tested before. Luckily, it did its job without a > hiccup. Thank you a lot for providing such a useful tool, I hope I can > help you by sending you this new data. Hello Grischa, Thanks for your report! I have marked the mainboard as supported and will commit that later together with other small changes. > [?] > Probing for Atmel AT25DF081A, 1024 kB: probe_spi_rdid_generic: id1 > 0x1f, id2 0x4501 > Chip status register is 00 > Found Atmel flash chip "AT25DF081A" (1024 kB, SPI) at physical address > 0xfff00000. > Ignoring security lockdown (if present) > Ignoring status register byte 2 > Chip status register is 00 > Chip status register: Sector Protection Register Lock (SRPL) is not set > Chip status register: Bit 6 is not set > Chip status register: Erase/Program Error (EPE) is not set > Chip status register: WP# pin (WPP) is asserted > Chip status register: Software Protection Status (SWP): no sectors are protected > Chip status register: Write Enable Latch (WEL) is not set > Chip status register: Write In Progress (WIP/BUSY) is not set > Probing for Atmel AT25DF161, 2048 kB: probe_spi_rdid_generic: id1 > 0x1f, id2 0x4501 > Probing for Atmel AT25DF321, 4096 kB: probe_spi_rdid_generic: id1 > 0x1f, id2 0x4501 > Probing for Atmel AT25DF321A, 4096 kB: probe_spi_rdid_generic: id1 > 0x1f, id2 0x4501 > Probing for Atmel AT25DF641, 8192 kB: probe_spi_rdid_generic: id1 > 0x1f, id2 0x4501 > Probing for Atmel AT25DQ161, 2048 kB: probe_spi_rdid_generic: id1 > 0x1f, id2 0x4501 > Probing for Atmel AT25F512B, 64 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 > Probing for Atmel AT25FS010, 128 kB: probe_spi_rdid_generic: id1 0x1f, > id2 0x4501 > Probing for Atmel AT25FS040, 512 kB: probe_spi_rdid_generic: id1 0x1f, > id2 0x4501 > Probing for Atmel AT26DF041, 512 kB: probe_spi_rdid_generic: id1 0x1f, > id2 0x4501 > Probing for Atmel AT26DF081A, 1024 kB: probe_spi_rdid_generic: id1 > 0x1f, id2 0x4501 > Chip status register is 00 > Found Atmel flash chip "AT26DF081A" (1024 kB, SPI) at physical address > 0xfff00000. > Chip status register is 00 > Chip status register: Sector Protection Register Lock (SRPL) is not set > Chip status register: Sequential Program Mode Status (SPM) is not set > Chip status register: Erase/Program Error (EPE) is not set > Chip status register: WP# pin (WPP) is asserted > Chip status register: Software Protection Status (SWP): no sectors are protected > Chip status register: Write Enable Latch (WEL) is not set > Chip status register: Write In Progress (WIP/BUSY) is not set > [?] > Multiple flash chips were detected: "AT25DF081A", "AT26DF081A" the chips are not found "at the same address", but report the same ID when queried. atmel did no give them distinct IDs so we can not distinguish them on our own, hence your help was required*, sorry. * i have not looked at the respective datesheets. it is possible that the other definition would work equally. > [?] > > $ lspci -nnvvxxx > [?] not needed in this case. -- Kind regards/Mit freundlichen Gr??en, Stefan Tauner From c-d.hailfinger.devel.2006 at gmx.net Wed Nov 2 23:20:17 2011 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Wed, 02 Nov 2011 23:20:17 +0100 Subject: [flashrom] [PATCH 1/5] Add opaque programmer registration infrastructure. In-Reply-To: <1320254997.12407.12.camel@localhost> References: <1319150349-24326-1-git-send-email-stefan.tauner@student.tuwien.ac.at> <1319150349-24326-2-git-send-email-stefan.tauner@student.tuwien.ac.at> <1320254997.12407.12.camel@localhost> Message-ID: <4EB1C221.10900@gmx.net> Am 02.11.2011 18:29 schrieb Michael Karcher: > Am Freitag, den 21.10.2011, 00:39 +0200 schrieb Stefan Tauner: >> diff --git a/flash.h b/flash.h >> index 535c1b8..8ad2845 100644 >> --- a/flash.h >> +++ b/flash.h >> @@ -62,8 +62,9 @@ enum chipbustype { >> BUS_LPC = 1 << 1, >> BUS_FWH = 1 << 2, >> BUS_SPI = 1 << 3, >> + BUS_PROG = 1 << 4, >> BUS_NONSPI = BUS_PARALLEL | BUS_LPC | BUS_FWH, >> - BUS_UNKNOWN = BUS_PARALLEL | BUS_LPC | BUS_FWH | BUS_SPI, >> + BUS_UNKNOWN = BUS_PARALLEL | BUS_LPC | BUS_FWH | BUS_SPI | BUS_PROG, > We don't need BUS_UNKNOWN. It is referenced only in flashbuses_to_text. > Having a programmer being both opaque and non-opaque seems to be as > useless as defining that a chip "might also be accessed through an > opaque interface". In the case of opaque interfaces, we don't care about > the chip type - so I don't see any use case for BUS_UNKNOWN, even more > after adding BUS_PROG. Killed. >> }; >> +#if defined(CONFIG_INTERNAL) && (defined(__i386__) || defined(__x86_64__)) >> + { >> + .vendor = "Programmer", >> + .name = "Opaque flash chip", >> + .bustype = BUS_PROG, >> + .manufacture_id = PROGMANUF_ID, >> + .model_id = PROGDEV_ID, >> + .total_size = 0, >> + .page_size = 256, >> + /* probe is assumed to work, rest will be filled in by probe */ >> + .tested = TEST_OK_PROBE, >> + .probe = probe_opaque, >> + /* eraseblock sizes will be set by the probing function */ >> + .block_erasers = >> + { >> + { >> + .block_erase = erase_opaque, >> + } >> + }, >> + .write = write_opaque, >> + .read = read_opaque, >> + }, >> +#endif // defined(CONFIG_INTERNAL) && (defined(__i386__) || defined(__x86_64__)) > Why do we need any prerequisite for the opaque programmer? It should > work outside of x86(-64), too, depending on which opaque backend is > used. I guess this #if is there because at the moment, the only opaque > programmer is the ICH9 stuff, but wouldn't a define NEED_OPAQUE that is > set in the include file as soon as any programmer based on the opaque > programmer is selected be more sensible? We don't use #ifdef for all other chips, so the sane solution is to avoid the #ifdef completely. >> @@ -9005,6 +9027,7 @@ const struct flashchip flashchips[] = { >> .probe = probe_spi_rdid, >> .write = NULL, >> }, >> + >> { >> .vendor = "Generic", >> .name = "unknown SPI chip (REMS)", > Unrelated change - you might have it in accidentally. Right. Stefan, do you plan to move this to your tested_stuff branch? >> +/* >> + * Contains the opaque programmer framework. >> + * An opaque programmer is a programmer which does not provide direct access >> + * to the flash chip and which abstracts all flash chip properties into a >> + * programmer specific interface. >> + */ >> + >> +#include >> +#include >> +#include "flash.h" >> +#include "flashchips.h" >> +#include "chipdrivers.h" >> +#include "programmer.h" >> + >> +const struct opaque_programmer opaque_programmer_none = { >> + .max_data_read = MAX_DATA_UNSPECIFIED, >> + .max_data_write = MAX_DATA_UNSPECIFIED, >> + .probe = NULL, >> + .read = NULL, > You are missing ".erase = NULL" here. Fixed. >> + .write = NULL, >> +}; >> + >> +const struct opaque_programmer *opaque_programmer = &opaque_programmer_none; >> + >> +int probe_opaque(struct flashchip *flash) >> +{ >> + if (!opaque_programmer->probe) { >> + msg_perr("%s called, but this is not an opaque programmer. " >> + "Please report a bug at flashrom at flashrom.org\n", >> + __func__); > I don't really like the error message, I would prefer "%s called without > register_opaque" or something like that. What about "%s called before register_opaque_programmer" ? >> +void register_opaque_programmer(const struct opaque_programmer *pgm) >> +{ >> + opaque_programmer = pgm; >> + buses_supported |= BUS_PROG; >> +} > You might want to check that the function pointers in pgm are not NULL, > to make the suggested error message "without register_opaque" more apt. Fixed. > Otherwise, the patch looks good to me. This is > Acked-By: Michael Karcher Thanks for the review! > If you feel confident you didn't mess up anything, feel free to re-use > the ack after minor edits. While I tested compilation, I'd still appreciate a second look at the result. An opaque programmer does not allow direct flash access and only offers abstract probe/read/erase/write methods. Due to that, opaque programmers need their own infrastructure and registration framework. Signed-off-by: Carl-Daniel Hailfinger Index: flashrom-register_opaque_programmer/flash.h =================================================================== --- flashrom-register_opaque_programmer/flash.h (Revision 1458) +++ flashrom-register_opaque_programmer/flash.h (Arbeitskopie) @@ -62,8 +62,8 @@ BUS_LPC = 1 << 1, BUS_FWH = 1 << 2, BUS_SPI = 1 << 3, + BUS_PROG = 1 << 4, BUS_NONSPI = BUS_PARALLEL | BUS_LPC | BUS_FWH, - BUS_UNKNOWN = BUS_PARALLEL | BUS_LPC | BUS_FWH | BUS_SPI, }; /* Index: flashrom-register_opaque_programmer/Makefile =================================================================== --- flashrom-register_opaque_programmer/Makefile (Revision 1458) +++ flashrom-register_opaque_programmer/Makefile (Arbeitskopie) @@ -242,7 +242,7 @@ CHIP_OBJS = jedec.o stm50flw0x0x.o w39.o w29ee011.o \ sst28sf040.o m29f400bt.o 82802ab.o pm49fl00x.o \ sst49lfxxxc.o sst_fwhub.o flashchips.o spi.o spi25.o sharplhf00l04.o \ - a25.o at25.o + a25.o at25.o opaque.o LIB_OBJS = layout.o Index: flashrom-register_opaque_programmer/opaque.c =================================================================== --- flashrom-register_opaque_programmer/opaque.c (Revision 0) +++ flashrom-register_opaque_programmer/opaque.c (Revision 0) @@ -0,0 +1,100 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2011 Carl-Daniel Hailfinger + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * Contains the opaque programmer framework. + * An opaque programmer is a programmer which does not provide direct access + * to the flash chip and which abstracts all flash chip properties into a + * programmer specific interface. + */ + +#include +#include +#include "flash.h" +#include "flashchips.h" +#include "chipdrivers.h" +#include "programmer.h" + +const struct opaque_programmer opaque_programmer_none = { + .max_data_read = MAX_DATA_UNSPECIFIED, + .max_data_write = MAX_DATA_UNSPECIFIED, + .probe = NULL, + .read = NULL, + .write = NULL, + .erase = NULL, +}; + +const struct opaque_programmer *opaque_programmer = &opaque_programmer_none; + +int probe_opaque(struct flashchip *flash) +{ + if (!opaque_programmer->probe) { + msg_perr("%s called before register_opaque_programmer. " + "Please report a bug at flashrom at flashrom.org\n", + __func__); + return 0; + } + + return opaque_programmer->probe(flash); +} + +int read_opaque(struct flashchip *flash, uint8_t *buf, int start, int len) +{ + if (!opaque_programmer->read) { + msg_perr("%s called before register_opaque_programmer. " + "Please report a bug at flashrom at flashrom.org\n", + __func__); + return 1; + } + return opaque_programmer->read(flash, buf, start, len); +} + +int write_opaque(struct flashchip *flash, uint8_t *buf, int start, int len) +{ + if (!opaque_programmer->write) { + msg_perr("%s called before register_opaque_programmer. " + "Please report a bug at flashrom at flashrom.org\n", + __func__); + return 1; + } + return opaque_programmer->write(flash, buf, start, len); +} + +int erase_opaque(struct flashchip *flash, unsigned int blockaddr, unsigned int blocklen) +{ + if (!opaque_programmer->erase) { + msg_perr("%s called before register_opaque_programmer. " + "Please report a bug at flashrom at flashrom.org\n", + __func__); + return 1; + } + return opaque_programmer->erase(flash, blockaddr, blocklen); +} + +void register_opaque_programmer(const struct opaque_programmer *pgm) +{ + if (!pgm->probe || !pgm->read || !pgm->write || !pgm->erase) { + msg_perr("%s called with one of probe/read/write/erase being " + "NULL. Please report a bug at flashrom at flashrom.org\n", + __func__); + return; + } + opaque_programmer = pgm; + buses_supported |= BUS_PROG; +} Index: flashrom-register_opaque_programmer/flashchips.c =================================================================== --- flashrom-register_opaque_programmer/flashchips.c (Revision 1458) +++ flashrom-register_opaque_programmer/flashchips.c (Arbeitskopie) @@ -8874,6 +8874,28 @@ }, { + .vendor = "Programmer", + .name = "Opaque flash chip", + .bustype = BUS_PROG, + .manufacture_id = PROGMANUF_ID, + .model_id = PROGDEV_ID, + .total_size = 0, + .page_size = 256, + /* probe is assumed to work, rest will be filled in by probe */ + .tested = TEST_OK_PROBE, + .probe = probe_opaque, + /* eraseblock sizes will be set by the probing function */ + .block_erasers = + { + { + .block_erase = erase_opaque, + } + }, + .write = write_opaque, + .read = read_opaque, + }, + + { .vendor = "AMIC", .name = "unknown AMIC SPI chip", .bustype = BUS_SPI, @@ -9005,6 +9027,7 @@ .probe = probe_spi_rdid, .write = NULL, }, + { .vendor = "Generic", .name = "unknown SPI chip (REMS)", Index: flashrom-register_opaque_programmer/flashchips.h =================================================================== --- flashrom-register_opaque_programmer/flashchips.h (Revision 1458) +++ flashrom-register_opaque_programmer/flashchips.h (Arbeitskopie) @@ -646,4 +646,7 @@ #define WINBOND_W49V002A 0xB0 #define WINBOND_W49V002FA 0x32 +#define PROGMANUF_ID 0xFFFE /* dummy ID for opaque chips behind a programmer */ +#define PROGDEV_ID 0x01 /* dummy ID for opaque chips behind a programmer */ + #endif /* !FLASHCHIPS_H */ Index: flashrom-register_opaque_programmer/programmer.h =================================================================== --- flashrom-register_opaque_programmer/programmer.h (Revision 1458) +++ flashrom-register_opaque_programmer/programmer.h (Arbeitskopie) @@ -601,6 +601,19 @@ int wbsio_check_for_spi(void); #endif +/* opaque.c */ +struct opaque_programmer { + int max_data_read; + int max_data_write; + /* Specific functions for this programmer */ + int (*probe) (struct flashchip *flash); + int (*read) (struct flashchip *flash, uint8_t *buf, int start, int len); + int (*write) (struct flashchip *flash, uint8_t *buf, int start, int len); + int (*erase) (struct flashchip *flash, unsigned int blockaddr, unsigned int blocklen); +}; +extern const struct opaque_programmer *opaque_programmer; +void register_opaque_programmer(const struct opaque_programmer *pgm); + /* serprog.c */ #if CONFIG_SERPROG == 1 int serprog_init(void); Index: flashrom-register_opaque_programmer/chipdrivers.h =================================================================== --- flashrom-register_opaque_programmer/chipdrivers.h (Revision 1458) +++ flashrom-register_opaque_programmer/chipdrivers.h (Arbeitskopie) @@ -58,6 +58,12 @@ int spi_write_chunked(struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize); int spi_aai_write(struct flashchip *flash, uint8_t *buf, int start, int len); +/* opaque.c */ +int probe_opaque(struct flashchip *flash); +int read_opaque(struct flashchip *flash, uint8_t *buf, int start, int len); +int write_opaque(struct flashchip *flash, uint8_t *buf, int start, int len); +int erase_opaque(struct flashchip *flash, unsigned int blockaddr, unsigned int blocklen); + /* a25.c */ int spi_prettyprint_status_register_amic_a25l05p(struct flashchip *flash); int spi_prettyprint_status_register_amic_a25l40p(struct flashchip *flash); Index: flashrom-register_opaque_programmer/print.c =================================================================== --- flashrom-register_opaque_programmer/print.c (Revision 1458) +++ flashrom-register_opaque_programmer/print.c (Arbeitskopie) @@ -32,13 +32,11 @@ char *flashbuses_to_text(enum chipbustype bustype) { char *ret = calloc(1, 1); - if (bustype == BUS_UNKNOWN) { - ret = strcat_realloc(ret, "Unknown, "); /* * FIXME: Once all chipsets and flash chips have been updated, NONSPI * will cease to exist and should be eliminated here as well. */ - } else if (bustype == BUS_NONSPI) { + if (bustype == BUS_NONSPI) { ret = strcat_realloc(ret, "Non-SPI, "); } else { if (bustype & BUS_PARALLEL) @@ -49,6 +47,8 @@ ret = strcat_realloc(ret, "FWH, "); if (bustype & BUS_SPI) ret = strcat_realloc(ret, "SPI, "); + if (bustype & BUS_PROG) + ret = strcat_realloc(ret, "Programmer-specific, "); if (bustype == BUS_NONE) ret = strcat_realloc(ret, "None, "); } -- http://www.hailfinger.org/ From stefan.tauner at student.tuwien.ac.at Thu Nov 3 01:58:21 2011 From: stefan.tauner at student.tuwien.ac.at (Stefan Tauner) Date: Thu, 3 Nov 2011 01:58:21 +0100 Subject: [flashrom] [PATCH] ichspi: use a variable to distinguish ich generations instead of spi_programmer->type In-Reply-To: <4EB0A071.8020506@gmx.net> References: <4EB0A071.8020506@gmx.net> Message-ID: <1320281901-15465-1-git-send-email-stefan.tauner@student.tuwien.ac.at> The type member is enough most of the time to derive the wanted information, but - not always (e.g. ich_set_bbar), - only available after registration, which we want to delay till the end of init, and - we really want to distinguish between chipset version-grained attributes which are not reflected by the registered programmer. Hence this patch introduces a new static variable which is set up early by the init functions and allows us to get rid of all "switch (spi_programmer->type)" in ichspi.c. We reuse the enum introduced for descriptor mode for the type of the new variable. Previously magic numbers were passed by chipset_enable wrappers. Now they use the enumeration items too. To get this working the enum definition had to be moved to programmer.h, which was fixed on the way by adding necessary includes. Another noteworthy detail: previously we have checked for a valid programmer/ich generation all over the place. I have removed those checks and added one single check in the init method. Calling any function of a programmer without executing the init method first, is undefined behavior. Signed-off-by: Stefan Tauner --- On Wed, 02 Nov 2011 02:44:17 +0100 Carl-Daniel Hailfinger wrote: > > i think it might be a good idea to get rid of the whole > > switch(spi_programmer->type) > > pattern and create a file-scope static ich_generation variable instead > > of using the type member and the ich_generation parameters everywhere. > > Absolutely agreed. > The only possible generic problem with that approach would be the > registration of multiple ICH-style SPI programmers, but unless we see > boards with two active ICH-style southbridges I think we can assume the > static variable handles it well. (Note that boards with multiple MCP55 > southbridges exist, but only one southbridge has an attached flash chip.) and even then they would have to be from different incompatible generations... i think we are quite safe ;) > There might be an issue for those who want to use flashrom as a > standalone tool (e.g. on top of libpayload) where heap allocations for > static variables are unwanted, but that's a huge can of worms and I'd > rather ignore that issue until either static variables work well in that > environment or until someone hacks a way around static variables being a > problem there. > > > the type member is enough most of the time to derive the wanted > > information, but > > - not always (e.g. ich_set_bbar) > > - only available after registration, which we want to delay till the end > > of init. > > - we really want to distinguish between chipset version-grained > > attributes which are not reflected by the registered programmer. > > Indeed. So if you could rework the patch to use your static variable > suggestion, it would reduce patch size and make the code more readable. you may want to evaluate that "patch size" argument again... *sigh* i have added the first applicable chipset to each default case for documentation purposes. chipset_enable.c | 24 +++++++------- ich_descriptors.h | 15 +-------- ichspi.c | 90 ++++++++++++++++++++++------------------------------- programmer.h | 14 ++++++++ 4 files changed, 64 insertions(+), 79 deletions(-) diff --git a/chipset_enable.c b/chipset_enable.c index d2d81e0..6bde2d0 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -504,7 +504,7 @@ static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name, static const char *const straps_names_unknown[] = { "unknown", "unknown", "unknown", "unknown" }; switch (ich_generation) { - case 7: + case CHIPSET_ICH7: /* EP80579 may need further changes, but this is the least * intrusive way to get correct BOOT Strap printing without * changing the rest of its code path). */ @@ -513,13 +513,13 @@ static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name, else straps_names = straps_names_ich7_nm10; break; - case 8: - case 9: - case 10: + case CHIPSET_ICH8: + case CHIPSET_ICH9: + case CHIPSET_ICH10: straps_names = straps_names_ich8910; break; - case 11: - case 12: + case CHIPSET_5_SERIES_IBEX_PEAK: + case CHIPSET_6_SERIES_COUGAR_POINT: straps_names = straps_names_pch56; break; default: @@ -579,34 +579,34 @@ static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name, static int enable_flash_ich7(struct pci_dev *dev, const char *name) { - return enable_flash_ich_dc_spi(dev, name, 7); + return enable_flash_ich_dc_spi(dev, name, CHIPSET_ICH7); } static int enable_flash_ich8(struct pci_dev *dev, const char *name) { - return enable_flash_ich_dc_spi(dev, name, 8); + return enable_flash_ich_dc_spi(dev, name, CHIPSET_ICH8); } static int enable_flash_ich9(struct pci_dev *dev, const char *name) { - return enable_flash_ich_dc_spi(dev, name, 9); + return enable_flash_ich_dc_spi(dev, name, CHIPSET_ICH9); } static int enable_flash_ich10(struct pci_dev *dev, const char *name) { - return enable_flash_ich_dc_spi(dev, name, 10); + return enable_flash_ich_dc_spi(dev, name, CHIPSET_ICH10); } /* Ibex Peak aka. 5 series & 3400 series */ static int enable_flash_pch5(struct pci_dev *dev, const char *name) { - return enable_flash_ich_dc_spi(dev, name, 11); + return enable_flash_ich_dc_spi(dev, name, CHIPSET_5_SERIES_IBEX_PEAK); } /* Cougar Point aka. 6 series & c200 series */ static int enable_flash_pch6(struct pci_dev *dev, const char *name) { - return enable_flash_ich_dc_spi(dev, name, 12); + return enable_flash_ich_dc_spi(dev, name, CHIPSET_6_SERIES_COUGAR_POINT); } static int via_no_byte_merge(struct pci_dev *dev, const char *name) diff --git a/ich_descriptors.h b/ich_descriptors.h index 4e2ad0a..714eda9 100644 --- a/ich_descriptors.h +++ b/ich_descriptors.h @@ -24,6 +24,7 @@ #define __ICH_DESCRIPTORS_H__ 1 #include +#include "programmer.h" /* for enum ich_chipset */ /* FIXME: Replace with generic return codes */ #define ICH_RET_OK 0 @@ -63,20 +64,6 @@ #define ICH_FREG_BASE(flreg) (((flreg) << 12) & 0x01fff000) #define ICH_FREG_LIMIT(flreg) (((flreg) >> 4) & 0x01fff000) -/* Used to select the right descriptor printing function. - * Currently only ICH8 and Ibex Peak are supported. - */ -enum ich_chipset { - CHIPSET_ICH_UNKNOWN, - CHIPSET_ICH7 = 7, - CHIPSET_ICH8, - CHIPSET_ICH9, - CHIPSET_ICH10, - CHIPSET_5_SERIES_IBEX_PEAK, - CHIPSET_6_SERIES_COUGAR_POINT, - CHIPSET_7_SERIES_PANTHER_POINT -}; - void prettyprint_ich_reg_vscc(uint32_t reg_val, int verbosity); struct ich_desc_content { diff --git a/ichspi.c b/ichspi.c index afa420b..137f438 100644 --- a/ichspi.c +++ b/ichspi.c @@ -172,6 +172,7 @@ /* ICH SPI configuration lock-down. May be set during chipset enabling. */ static int ichspi_lock = 0; +static enum ich_chipset ich_generation = CHIPSET_ICH_UNKNOWN; uint32_t ichspi_bbar = 0; static void *ich_spibar = NULL; @@ -454,23 +455,20 @@ static int generate_opcodes(OPCODES * op) return -1; } - switch (spi_programmer->type) { - case SPI_CONTROLLER_ICH7: - case SPI_CONTROLLER_VIA: + switch (ich_generation) { + case CHIPSET_ICH7: preop = REGREAD16(ICH7_REG_PREOP); optype = REGREAD16(ICH7_REG_OPTYPE); opmenu[0] = REGREAD32(ICH7_REG_OPMENU); opmenu[1] = REGREAD32(ICH7_REG_OPMENU + 4); break; - case SPI_CONTROLLER_ICH9: + case CHIPSET_ICH8: + default: /* Future version might behave the same */ preop = REGREAD16(ICH9_REG_PREOP); optype = REGREAD16(ICH9_REG_OPTYPE); opmenu[0] = REGREAD32(ICH9_REG_OPMENU); opmenu[1] = REGREAD32(ICH9_REG_OPMENU + 4); break; - default: - msg_perr("%s: unsupported chipset\n", __func__); - return -1; } op->preop[0] = (uint8_t) preop; @@ -529,9 +527,8 @@ static int program_opcodes(OPCODES *op, int enable_undo) } msg_pdbg("\n%s: preop=%04x optype=%04x opmenu=%08x%08x\n", __func__, preop, optype, opmenu[0], opmenu[1]); - switch (spi_programmer->type) { - case SPI_CONTROLLER_ICH7: - case SPI_CONTROLLER_VIA: + switch (ich_generation) { + case CHIPSET_ICH7: /* Register undo only for enable_undo=1, i.e. first call. */ if (enable_undo) { rmmio_valw(ich_spibar + ICH7_REG_PREOP); @@ -544,7 +541,8 @@ static int program_opcodes(OPCODES *op, int enable_undo) mmio_writel(opmenu[0], ich_spibar + ICH7_REG_OPMENU); mmio_writel(opmenu[1], ich_spibar + ICH7_REG_OPMENU + 4); break; - case SPI_CONTROLLER_ICH9: + case CHIPSET_ICH8: + default: /* Future version might behave the same */ /* Register undo only for enable_undo=1, i.e. first call. */ if (enable_undo) { rmmio_valw(ich_spibar + ICH9_REG_PREOP); @@ -557,9 +555,6 @@ static int program_opcodes(OPCODES *op, int enable_undo) mmio_writel(opmenu[0], ich_spibar + ICH9_REG_OPMENU); mmio_writel(opmenu[1], ich_spibar + ICH9_REG_OPMENU + 4); break; - default: - msg_perr("%s: unsupported chipset\n", __func__); - return -1; } return 0; @@ -569,16 +564,17 @@ static int program_opcodes(OPCODES *op, int enable_undo) * Try to set BBAR (BIOS Base Address Register), but read back the value in case * it didn't stick. */ -static void ich_set_bbar(int ich_generation, uint32_t min_addr) +static void ich_set_bbar(uint32_t min_addr) { int bbar_off; switch (ich_generation) { - case 7: + case CHIPSET_ICH7: bbar_off = 0x50; break; - case 8: + case CHIPSET_ICH8: msg_perr("BBAR offset is unknown on ICH8!\n"); return; + case CHIPSET_ICH9: default: /* Future version might behave the same */ bbar_off = ICH9_REG_BBAR; break; @@ -943,15 +939,12 @@ static int run_opcode(OPCODE op, uint32_t offset, return SPI_INVALID_LENGTH; } - switch (spi_programmer->type) { - case SPI_CONTROLLER_VIA: - case SPI_CONTROLLER_ICH7: + switch (ich_generation) { + case CHIPSET_ICH7: return ich7_run_opcode(op, offset, datalength, data, maxlength); - case SPI_CONTROLLER_ICH9: + case CHIPSET_ICH8: + default: /* Future version might behave the same */ return ich9_run_opcode(op, offset, datalength, data); - default: - /* If we ever get here, something really weird happened */ - return -1; } } @@ -1022,19 +1015,11 @@ static int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) { addr = (writearr[1] << 16) | (writearr[2] << 8) | (writearr[3] << 0); - switch (spi_programmer->type) { - case SPI_CONTROLLER_ICH7: - case SPI_CONTROLLER_VIA: - case SPI_CONTROLLER_ICH9: - if (addr < ichspi_bbar) { - msg_perr("%s: Address 0x%06x below allowed " - "range 0x%06x-0xffffff\n", __func__, - addr, ichspi_bbar); - return SPI_INVALID_ADDRESS; - } - break; - default: - break; + if (addr < ichspi_bbar) { + msg_perr("%s: Address 0x%06x below allowed " + "range 0x%06x-0xffffff\n", __func__, + addr, ichspi_bbar); + return SPI_INVALID_ADDRESS; } } @@ -1315,8 +1300,7 @@ static const struct spi_programmer spi_programmer_ich9 = { .write_256 = default_spi_write_256, }; -int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, - int ich_generation) +int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, int ich_gen) { int i; uint8_t old, new; @@ -1324,15 +1308,16 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, uint32_t tmp; int desc_valid = 0; + ich_generation = ich_gen; + switch (ich_generation) { - case 7: - spibar_offset = 0x3020; - break; - case 8: + case CHIPSET_ICH_UNKNOWN: + return -1; + case CHIPSET_ICH7: + case CHIPSET_ICH8: spibar_offset = 0x3020; break; - case 9: - case 10: + case CHIPSET_ICH9: default: /* Future version might behave the same */ spibar_offset = 0x3800; break; @@ -1345,7 +1330,7 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, ich_spibar = rcrb + spibar_offset; switch (ich_generation) { - case 7: + case CHIPSET_ICH7: msg_pdbg("0x00: 0x%04x (SPIS)\n", mmio_readw(ich_spibar + 0)); msg_pdbg("0x02: 0x%04x (SPIC)\n", @@ -1381,13 +1366,11 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); ichspi_lock = 1; } - ich_set_bbar(ich_generation, 0); + ich_set_bbar(0); register_spi_programmer(&spi_programmer_ich7); ich_init_opcodes(); break; - case 8: - case 9: - case 10: + case CHIPSET_ICH8: default: /* Future version might behave the same */ tmp2 = mmio_readw(ich_spibar + ICH9_REG_HSFS); msg_pdbg("0x04: 0x%04x (HSFS)\n", tmp2); @@ -1447,7 +1430,7 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, mmio_readl(ich_spibar + ICH9_REG_OPMENU)); msg_pdbg("0x9C: 0x%08x (OPMENU+4)\n", mmio_readl(ich_spibar + ICH9_REG_OPMENU + 4)); - if (ich_generation == 8) { + if (ich_generation == CHIPSET_ICH8) { tmp = mmio_readl(ich_spibar + ICH8_REG_VSCC); msg_pdbg("0xC1: 0x%08x (VSCC)\n", tmp); msg_pdbg("VSCC: "); @@ -1469,7 +1452,7 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, tmp = mmio_readl(ich_spibar + ICH9_REG_FPB); msg_pdbg("0xD0: 0x%08x (FPB)\n", tmp); - ich_set_bbar(ich_generation, 0); + ich_set_bbar(0); } msg_pdbg("\n"); @@ -1524,6 +1507,7 @@ int via_init_spi(struct pci_dev *dev) /* Not sure if it speaks all these bus protocols. */ buses_supported = BUS_LPC | BUS_FWH; + ich_generation = CHIPSET_ICH7; register_spi_programmer(&spi_programmer_via); msg_pdbg("0x00: 0x%04x (SPIS)\n", mmio_readw(ich_spibar + 0)); @@ -1556,7 +1540,7 @@ int via_init_spi(struct pci_dev *dev) ichspi_lock = 1; } - ich_set_bbar(7, 0); + ich_set_bbar(0); ich_init_opcodes(); return 0; diff --git a/programmer.h b/programmer.h index 8d72518..dc40ab8 100644 --- a/programmer.h +++ b/programmer.h @@ -24,6 +24,9 @@ #ifndef __PROGRAMMER_H__ #define __PROGRAMMER_H__ 1 +#include +#include "flash.h" /* for chipaddr, pci_dev */ + enum programmer { #if CONFIG_INTERNAL == 1 PROGRAMMER_INTERNAL, @@ -577,6 +580,17 @@ void register_spi_programmer(const struct spi_programmer *programmer); /* ichspi.c */ #if CONFIG_INTERNAL == 1 +enum ich_chipset { + CHIPSET_ICH_UNKNOWN, + CHIPSET_ICH7 = 7, + CHIPSET_ICH8, + CHIPSET_ICH9, + CHIPSET_ICH10, + CHIPSET_5_SERIES_IBEX_PEAK, + CHIPSET_6_SERIES_COUGAR_POINT, + CHIPSET_7_SERIES_PANTHER_POINT +}; + extern uint32_t ichspi_bbar; int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, int ich_generation); -- 1.7.1 From stefan.tauner at student.tuwien.ac.at Thu Nov 3 12:04:23 2011 From: stefan.tauner at student.tuwien.ac.at (Stefan Tauner) Date: Thu, 3 Nov 2011 12:04:23 +0100 Subject: [flashrom] [PATCH 5/7] warn if SMM BIOS Write Protection is detected in BIOS_CNTL In-Reply-To: <4DDC5848.4050000@coreboot.org> References: <1305671512-7267-1-git-send-email-stefan.tauner@student.tuwien.ac.at> <1306192994-4006-6-git-send-email-stefan.tauner@student.tuwien.ac.at> <4DDC5848.4050000@coreboot.org> Message-ID: <201111031104.pA3B42DE013508@mail2.student.tuwien.ac.at> On Tue, 24 May 2011 18:15:52 -0700 Stefan Reinauer wrote: > On 5/23/11 4:23 PM, Stefan Tauner wrote: > > Signed-off-by: Stefan Tauner > > --- > > chipset_enable.c | 12 +++++++++++- > > 1 files changed, 11 insertions(+), 1 deletions(-) > > > > diff --git a/chipset_enable.c b/chipset_enable.c > > index 83b49ad..339c6bb 100644 > > --- a/chipset_enable.c > > +++ b/chipset_enable.c > > @@ -264,8 +264,18 @@ static int enable_flash_ich(struct pci_dev *dev, const char *name, > > (old& (1<< 0)) ? "en" : "dis"); > > msg_pdbg("BIOS_CNTL is 0x%x\n", old); > > > > - new = old | 1; > > + /* > > + * Quote from the 6 Series datasheet: > > + * "5: SMM BIOS Write Protect Disable (SMM_BWP) > > + * 1 = BIOS region SMM protection is enabled. > > + * The BIOS Region is not writable unless all processors are in SMM." > > + * In earlier chipsets this bit is reserved. */ > > + if (old& (5<< 1)) { > > + msg_pinfo("WARNING: BIOS region SMM protection is enabled!\n"); > > + return -1; > You might still be successful doing the write, in case the SMM handler > does not enforce the protection, so maybe you should just print a > warning but not return here? in chromium-os you are trying to unset that bit[1], but according to the data sheet this is impossible - it is R/W LO (read/write lock once). and you degraded the warning to dbg level... certainly not suited for upstream, but maybe desirable for chromium(?). have you tested this on a board where SMM_BWP is really set to 1? we may wanna try to write it anyway, but it would be far more interesting if it really works on some chipsets :) 1: http://git.chromium.org/gitweb/?p=chromiumos/third_party/flashrom.git;a=commitdiff;h=a5f4e82c59d6bcaf06b94623e5516d1db8cb843a -- Kind regards/Mit freundlichen Gr??en, Stefan Tauner From stefan.reinauer at coreboot.org Thu Nov 3 19:08:37 2011 From: stefan.reinauer at coreboot.org (Stefan Reinauer) Date: Thu, 3 Nov 2011 19:08:37 +0100 Subject: [flashrom] [PATCH 5/7] warn if SMM BIOS Write Protection is detected in BIOS_CNTL In-Reply-To: <201111031104.pA3B42DE013508@mail2.student.tuwien.ac.at> References: <1305671512-7267-1-git-send-email-stefan.tauner@student.tuwien.ac.at> <1306192994-4006-6-git-send-email-stefan.tauner@student.tuwien.ac.at> <4DDC5848.4050000@coreboot.org> <201111031104.pA3B42DE013508@mail2.student.tuwien.ac.at> Message-ID: <20111103180747.GA1545@coreboot.org> * Stefan Tauner [111103 12:04]: > > > - new = old | 1; > > > + /* > > > + * Quote from the 6 Series datasheet: > > > + * "5: SMM BIOS Write Protect Disable (SMM_BWP) > > > + * 1 = BIOS region SMM protection is enabled. > > > + * The BIOS Region is not writable unless all processors are in SMM." > > > + * In earlier chipsets this bit is reserved. */ > > > + if (old& (5<< 1)) { > > > + msg_pinfo("WARNING: BIOS region SMM protection is enabled!\n"); > > > + return -1; > > You might still be successful doing the write, in case the SMM handler > > does not enforce the protection, so maybe you should just print a > > warning but not return here? > > in chromium-os you are trying to unset that bit[1], but according to the > data sheet this is impossible - it is R/W LO (read/write lock once). Maybe there is some confusion about R/W LO. The bit can be locked, but that does not mean it is locked automatically by writing / clearing it. Once it is locked, the lock can not be undone except by a chipset reset. > and you degraded the warning to dbg level... certainly not suited for > upstream, but maybe desirable for chromium(?). Yes, that was done on purpose, because the lock bit that prevents the bit from being cleared also produces a warning. > have you tested this on a board where SMM_BWP is really set to 1? we > may wanna try to write it anyway, but it would be far more interesting > if it really works on some chipsets :) Yes, this was implemented to fix a problem I was seeing, and it solved the problem. :-) Stefan From c-d.hailfinger.devel.2006 at gmx.net Thu Nov 3 23:07:05 2011 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Thu, 03 Nov 2011 23:07:05 +0100 Subject: [flashrom] [RFC] Add struct flashchip * everywhere In-Reply-To: <201111021241.pA2CfGHH021689@mail2.student.tuwien.ac.at> References: <4EB0BEB2.1040701@gmx.net> <201111021241.pA2CfGHH021689@mail2.student.tuwien.ac.at> Message-ID: <4EB31089.7000902@gmx.net> Am 02.11.2011 13:41 schrieb Stefan Tauner: > On Wed, 02 Nov 2011 04:53:22 +0100 > Carl-Daniel Hailfinger wrote: > >> We need a way to identify which registered programmer should be used for >> a given access. Especially for cases where multiple programmers for the >> same bus type are registered (e.g. IT87+MCP79 SPI or Dual BIOS >> solutions), probing has to happen on each programmer. Somehow we have to >> tell the dispatcher (spi_send_command etc.) this information, and the >> only way to get the info to the dispatcher is either an ugly global >> variable which makes dealing with multiple flash chips and multiple bus >> probing really messy, or we store the info inside struct flashchip. >> Given that struct flashchip is passed around almost everywhere already, >> it is the natural location for such information and only very few >> function prototypes have to be changed to handle this. >> >> I have a prototype patch in the queue, but it's only half ready. If >> there is any interest, I can send the patch as is to give you an option >> to shoot it down while it is still unfinished. > changing prototypes should be no concern in such decisions imho. it is > a one-time change that may break some patches in the queue (which is no > problem, because there should be only a short queue, right? ;) but this > should not play a major role in the design. Heh, OK. > the reason i bring this argument up explicitly is that i think > the name "flashchip" may get a bit abused and changing it might be > better. that's not necessarily the case, i just wanted to criticize > something, because else it sounds good at this level of detail ;) struct everything? And yes, that proposal is halfway serious. > another layer of redirection is - as always - also a > possibility: introducing a new struct with pointers to the actual chip > and the programmer to be used (and other information related to the > actual situation/probing... e.g. access right ranges). but that's > probably not needed (yet) and the splitting could be done later anyway > if need be. OTOH if it is clear that there will be more information > stuffed into struct flashchip, that is not really static and does not > need to/should not reside in flashchips.c/struct flashchip, we may > better discuss a separation now(?). We have a big problem: There is almost no information in struct flashchip which is constant in all cases. The name, size and erase structures could be filled in automatically for SFDP stuff. That alone kills the separation idea IMHO. Here comes my current patch for struct flashchip * everyhwere. Uwe: I know that 80 columns are a limit, and I violated it badly in many places. I just wanted to get something testable out, and I will change the formatting if the patch has a chance for merging. Signed-off-by: Carl-Daniel Hailfinger Index: flashrom-struct_flashchip_everywhere/flash.h =================================================================== --- flashrom-struct_flashchip_everywhere/flash.h (Revision 1458) +++ flashrom-struct_flashchip_everywhere/flash.h (Arbeitskopie) @@ -44,14 +44,6 @@ void *programmer_map_flash_region(const char *descr, unsigned long phys_addr, size_t len); void programmer_unmap_flash_region(void *virt_addr, size_t len); -void chip_writeb(uint8_t val, chipaddr addr); -void chip_writew(uint16_t val, chipaddr addr); -void chip_writel(uint32_t val, chipaddr addr); -void chip_writen(uint8_t *buf, chipaddr addr, size_t len); -uint8_t chip_readb(const chipaddr addr); -uint16_t chip_readw(const chipaddr addr); -uint32_t chip_readl(const chipaddr addr); -void chip_readn(uint8_t *buf, const chipaddr addr, size_t len); void programmer_delay(int usecs); #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) @@ -186,6 +178,15 @@ extern const struct flashchip flashchips[]; +void chip_writeb(const struct flashchip *flash, uint8_t val, chipaddr addr); +void chip_writew(const struct flashchip *flash, uint16_t val, chipaddr addr); +void chip_writel(const struct flashchip *flash, uint32_t val, chipaddr addr); +void chip_writen(const struct flashchip *flash, uint8_t *buf, chipaddr addr, size_t len); +uint8_t chip_readb(const struct flashchip *flash, const chipaddr addr); +uint16_t chip_readw(const struct flashchip *flash, const chipaddr addr); +uint32_t chip_readl(const struct flashchip *flash, const chipaddr addr); +void chip_readn(const struct flashchip *flash, uint8_t *buf, const chipaddr addr, size_t len); + /* print.c */ char *flashbuses_to_text(enum chipbustype bustype); void print_supported(void); @@ -266,9 +267,9 @@ const unsigned char *writearr; unsigned char *readarr; }; -int spi_send_command(unsigned int writecnt, unsigned int readcnt, +int spi_send_command(struct flashchip *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); -int spi_send_multicommand(struct spi_command *cmds); -uint32_t spi_get_valid_read_addr(void); +int spi_send_multicommand(struct flashchip *flash, struct spi_command *cmds); +uint32_t spi_get_valid_read_addr(struct flashchip *flash); #endif /* !__FLASH_H__ */ Index: flashrom-struct_flashchip_everywhere/it87spi.c =================================================================== --- flashrom-struct_flashchip_everywhere/it87spi.c (Revision 1458) +++ flashrom-struct_flashchip_everywhere/it87spi.c (Arbeitskopie) @@ -103,7 +103,7 @@ return; } -static int it8716f_spi_send_command(unsigned int writecnt, unsigned int readcnt, +static int it8716f_spi_send_command(struct flashchip *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); static int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len); @@ -247,7 +247,7 @@ * commands with the address in inverse wire order. That's why the register * ordering in case 4 and 5 may seem strange. */ -static int it8716f_spi_send_command(unsigned int writecnt, unsigned int readcnt, +static int it8716f_spi_send_command(struct flashchip *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { uint8_t busy, writeenc; @@ -318,19 +318,19 @@ int i, result; chipaddr bios = flash->virtual_memory; - result = spi_write_enable(); + result = spi_write_enable(flash); if (result) return result; /* FIXME: The command below seems to be redundant or wrong. */ OUTB(0x06, it8716f_flashport + 1); OUTB(((2 + (fast_spi ? 1 : 0)) << 4), it8716f_flashport); for (i = 0; i < flash->page_size; i++) - chip_writeb(buf[i], bios + start + i); + chip_writeb(flash, buf[i], bios + start + i); OUTB(0, it8716f_flashport); /* Wait until the Write-In-Progress bit is cleared. * This usually takes 1-10 ms, so wait in 1 ms steps. */ - while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) + while (spi_read_status_register(flash) & JEDEC_RDSR_BIT_WIP) programmer_delay(1000); return 0; } Index: flashrom-struct_flashchip_everywhere/jedec.c =================================================================== --- flashrom-struct_flashchip_everywhere/jedec.c (Revision 1458) +++ flashrom-struct_flashchip_everywhere/jedec.c (Arbeitskopie) @@ -37,17 +37,17 @@ return (val ^ (val >> 1)) & 0x1; } -static void toggle_ready_jedec_common(chipaddr dst, int delay) +static void toggle_ready_jedec_common(const struct flashchip *flash, chipaddr dst, int delay) { unsigned int i = 0; uint8_t tmp1, tmp2; - tmp1 = chip_readb(dst) & 0x40; + tmp1 = chip_readb(flash, dst) & 0x40; while (i++ < 0xFFFFFFF) { if (delay) programmer_delay(delay); - tmp2 = chip_readb(dst) & 0x40; + tmp2 = chip_readb(flash, dst) & 0x40; if (tmp1 == tmp2) { break; } @@ -57,9 +57,9 @@ msg_cdbg("%s: excessive loops, i=0x%x\n", __func__, i); } -void toggle_ready_jedec(chipaddr dst) +void toggle_ready_jedec(const struct flashchip *flash, chipaddr dst) { - toggle_ready_jedec_common(dst, 0); + toggle_ready_jedec_common(flash, dst, 0); } /* Some chips require a minimum delay between toggle bit reads. @@ -69,12 +69,12 @@ * Given that erase is slow on all chips, it is recommended to use * toggle_ready_jedec_slow in erase functions. */ -static void toggle_ready_jedec_slow(chipaddr dst) +static void toggle_ready_jedec_slow(const struct flashchip *flash, chipaddr dst) { - toggle_ready_jedec_common(dst, 8 * 1000); + toggle_ready_jedec_common(flash, dst, 8 * 1000); } -void data_polling_jedec(chipaddr dst, uint8_t data) +void data_polling_jedec(const struct flashchip *flash, chipaddr dst, uint8_t data) { unsigned int i = 0; uint8_t tmp; @@ -82,7 +82,7 @@ data &= 0x80; while (i++ < 0xFFFFFFF) { - tmp = chip_readb(dst) & 0x80; + tmp = chip_readb(flash, dst) & 0x80; if (tmp == data) { break; } @@ -113,9 +113,9 @@ static void start_program_jedec_common(struct flashchip *flash, unsigned int mask) { chipaddr bios = flash->virtual_memory; - chip_writeb(0xAA, bios + (0x5555 & mask)); - chip_writeb(0x55, bios + (0x2AAA & mask)); - chip_writeb(0xA0, bios + (0x5555 & mask)); + chip_writeb(flash, 0xAA, bios + (0x5555 & mask)); + chip_writeb(flash, 0x55, bios + (0x2AAA & mask)); + chip_writeb(flash, 0xA0, bios + (0x5555 & mask)); } static int probe_jedec_common(struct flashchip *flash, unsigned int mask) @@ -150,57 +150,57 @@ /* Reset chip to a clean slate */ if ((flash->feature_bits & FEATURE_RESET_MASK) == FEATURE_LONG_RESET) { - chip_writeb(0xAA, bios + (0x5555 & mask)); + chip_writeb(flash, 0xAA, bios + (0x5555 & mask)); if (probe_timing_exit) programmer_delay(10); - chip_writeb(0x55, bios + (0x2AAA & mask)); + chip_writeb(flash, 0x55, bios + (0x2AAA & mask)); if (probe_timing_exit) programmer_delay(10); } - chip_writeb(0xF0, bios + (0x5555 & mask)); + chip_writeb(flash, 0xF0, bios + (0x5555 & mask)); if (probe_timing_exit) programmer_delay(probe_timing_exit); /* Issue JEDEC Product ID Entry command */ - chip_writeb(0xAA, bios + (0x5555 & mask)); + chip_writeb(flash, 0xAA, bios + (0x5555 & mask)); if (probe_timing_enter) programmer_delay(10); - chip_writeb(0x55, bios + (0x2AAA & mask)); + chip_writeb(flash, 0x55, bios + (0x2AAA & mask)); if (probe_timing_enter) programmer_delay(10); - chip_writeb(0x90, bios + (0x5555 & mask)); + chip_writeb(flash, 0x90, bios + (0x5555 & mask)); if (probe_timing_enter) programmer_delay(probe_timing_enter); /* Read product ID */ - id1 = chip_readb(bios); - id2 = chip_readb(bios + 0x01); + id1 = chip_readb(flash, bios); + id2 = chip_readb(flash, bios + 0x01); largeid1 = id1; largeid2 = id2; /* Check if it is a continuation ID, this should be a while loop. */ if (id1 == 0x7F) { largeid1 <<= 8; - id1 = chip_readb(bios + 0x100); + id1 = chip_readb(flash, bios + 0x100); largeid1 |= id1; } if (id2 == 0x7F) { largeid2 <<= 8; - id2 = chip_readb(bios + 0x101); + id2 = chip_readb(flash, bios + 0x101); largeid2 |= id2; } /* Issue JEDEC Product ID Exit command */ if ((flash->feature_bits & FEATURE_RESET_MASK) == FEATURE_LONG_RESET) { - chip_writeb(0xAA, bios + (0x5555 & mask)); + chip_writeb(flash, 0xAA, bios + (0x5555 & mask)); if (probe_timing_exit) programmer_delay(10); - chip_writeb(0x55, bios + (0x2AAA & mask)); + chip_writeb(flash, 0x55, bios + (0x2AAA & mask)); if (probe_timing_exit) programmer_delay(10); } - chip_writeb(0xF0, bios + (0x5555 & mask)); + chip_writeb(flash, 0xF0, bios + (0x5555 & mask)); if (probe_timing_exit) programmer_delay(probe_timing_exit); @@ -209,17 +209,17 @@ msg_cdbg(", id1 parity violation"); /* Read the product ID location again. We should now see normal flash contents. */ - flashcontent1 = chip_readb(bios); - flashcontent2 = chip_readb(bios + 0x01); + flashcontent1 = chip_readb(flash, bios); + flashcontent2 = chip_readb(flash, bios + 0x01); /* Check if it is a continuation ID, this should be a while loop. */ if (flashcontent1 == 0x7F) { flashcontent1 <<= 8; - flashcontent1 |= chip_readb(bios + 0x100); + flashcontent1 |= chip_readb(flash, bios + 0x100); } if (flashcontent2 == 0x7F) { flashcontent2 <<= 8; - flashcontent2 |= chip_readb(bios + 0x101); + flashcontent2 |= chip_readb(flash, bios + 0x101); } if (largeid1 == flashcontent1) @@ -246,22 +246,22 @@ delay_us = 10; /* Issue the Sector Erase command */ - chip_writeb(0xAA, bios + (0x5555 & mask)); + chip_writeb(flash, 0xAA, bios + (0x5555 & mask)); programmer_delay(delay_us); - chip_writeb(0x55, bios + (0x2AAA & mask)); + chip_writeb(flash, 0x55, bios + (0x2AAA & mask)); programmer_delay(delay_us); - chip_writeb(0x80, bios + (0x5555 & mask)); + chip_writeb(flash, 0x80, bios + (0x5555 & mask)); programmer_delay(delay_us); - chip_writeb(0xAA, bios + (0x5555 & mask)); + chip_writeb(flash, 0xAA, bios + (0x5555 & mask)); programmer_delay(delay_us); - chip_writeb(0x55, bios + (0x2AAA & mask)); + chip_writeb(flash, 0x55, bios + (0x2AAA & mask)); programmer_delay(delay_us); - chip_writeb(0x30, bios + page); + chip_writeb(flash, 0x30, bios + page); programmer_delay(delay_us); /* wait for Toggle bit ready */ - toggle_ready_jedec_slow(bios); + toggle_ready_jedec_slow(flash, bios); /* FIXME: Check the status register for errors. */ return 0; @@ -276,22 +276,22 @@ delay_us = 10; /* Issue the Sector Erase command */ - chip_writeb(0xAA, bios + (0x5555 & mask)); + chip_writeb(flash, 0xAA, bios + (0x5555 & mask)); programmer_delay(delay_us); - chip_writeb(0x55, bios + (0x2AAA & mask)); + chip_writeb(flash, 0x55, bios + (0x2AAA & mask)); programmer_delay(delay_us); - chip_writeb(0x80, bios + (0x5555 & mask)); + chip_writeb(flash, 0x80, bios + (0x5555 & mask)); programmer_delay(delay_us); - chip_writeb(0xAA, bios + (0x5555 & mask)); + chip_writeb(flash, 0xAA, bios + (0x5555 & mask)); programmer_delay(delay_us); - chip_writeb(0x55, bios + (0x2AAA & mask)); + chip_writeb(flash, 0x55, bios + (0x2AAA & mask)); programmer_delay(delay_us); - chip_writeb(0x50, bios + block); + chip_writeb(flash, 0x50, bios + block); programmer_delay(delay_us); /* wait for Toggle bit ready */ - toggle_ready_jedec_slow(bios); + toggle_ready_jedec_slow(flash, bios); /* FIXME: Check the status register for errors. */ return 0; @@ -305,21 +305,21 @@ delay_us = 10; /* Issue the JEDEC Chip Erase command */ - chip_writeb(0xAA, bios + (0x5555 & mask)); + chip_writeb(flash, 0xAA, bios + (0x5555 & mask)); programmer_delay(delay_us); - chip_writeb(0x55, bios + (0x2AAA & mask)); + chip_writeb(flash, 0x55, bios + (0x2AAA & mask)); programmer_delay(delay_us); - chip_writeb(0x80, bios + (0x5555 & mask)); + chip_writeb(flash, 0x80, bios + (0x5555 & mask)); programmer_delay(delay_us); - chip_writeb(0xAA, bios + (0x5555 & mask)); + chip_writeb(flash, 0xAA, bios + (0x5555 & mask)); programmer_delay(delay_us); - chip_writeb(0x55, bios + (0x2AAA & mask)); + chip_writeb(flash, 0x55, bios + (0x2AAA & mask)); programmer_delay(delay_us); - chip_writeb(0x10, bios + (0x5555 & mask)); + chip_writeb(flash, 0x10, bios + (0x5555 & mask)); programmer_delay(delay_us); - toggle_ready_jedec_slow(bios); + toggle_ready_jedec_slow(flash, bios); /* FIXME: Check the status register for errors. */ return 0; @@ -341,10 +341,10 @@ start_program_jedec_common(flash, mask); /* transfer data from source to destination */ - chip_writeb(*src, dst); - toggle_ready_jedec(bios); + chip_writeb(flash, *src, dst); + toggle_ready_jedec(flash, bios); - if (chip_readb(dst) != *src && tried++ < MAX_REFLASH_TRIES) { + if (chip_readb(flash, dst) != *src && tried++ < MAX_REFLASH_TRIES) { goto retry; } @@ -395,12 +395,12 @@ for (i = 0; i < page_size; i++) { /* If the data is 0xFF, don't program it */ if (*src != 0xFF) - chip_writeb(*src, dst); + chip_writeb(flash, *src, dst); dst++; src++; } - toggle_ready_jedec(dst - 1); + toggle_ready_jedec(flash, dst - 1); dst = d; src = s; Index: flashrom-struct_flashchip_everywhere/bitbang_spi.c =================================================================== --- flashrom-struct_flashchip_everywhere/bitbang_spi.c (Revision 1458) +++ flashrom-struct_flashchip_everywhere/bitbang_spi.c (Arbeitskopie) @@ -63,7 +63,7 @@ bitbang_spi_master->release_bus(); } -static int bitbang_spi_send_command(unsigned int writecnt, unsigned int readcnt, +static int bitbang_spi_send_command(struct flashchip *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); static const struct spi_programmer spi_programmer_bitbang = { @@ -141,7 +141,7 @@ return ret; } -static int bitbang_spi_send_command(unsigned int writecnt, unsigned int readcnt, +static int bitbang_spi_send_command(struct flashchip *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { int i; Index: flashrom-struct_flashchip_everywhere/serprog.c =================================================================== --- flashrom-struct_flashchip_everywhere/serprog.c (Revision 1458) +++ flashrom-struct_flashchip_everywhere/serprog.c (Arbeitskopie) @@ -299,6 +299,12 @@ return 0; } +static int serprog_spi_send_command(struct flashchip *flash, + unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr, + unsigned char *readarr); +static int serprog_spi_read(struct flashchip *flash, uint8_t *buf, int start, + int len); static struct spi_programmer spi_programmer_serprog = { .type = SPI_CONTROLLER_SERPROG, .max_data_read = MAX_DATA_READ_UNLIMITED, @@ -766,7 +772,7 @@ sp_prev_was_write = 0; } -int serprog_spi_send_command(unsigned int writecnt, unsigned int readcnt, +static int serprog_spi_send_command(struct flashchip *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { @@ -796,7 +802,7 @@ * the advantage that it is much faster for most chips, but breaks those with * non-contiguous address space (like AT45DB161D). When spi_read_chunked is * fixed this method can be removed. */ -int serprog_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) +static int serprog_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) { int i; int cur_len; @@ -804,7 +810,7 @@ for (i = 0; i < len; i += cur_len) { int ret; cur_len = min(max_read, (len - i)); - ret = spi_nbyte_read(start + i, buf + i, cur_len); + ret = spi_nbyte_read(flash, start + i, buf + i, cur_len); if (ret) return ret; } Index: flashrom-struct_flashchip_everywhere/w39.c =================================================================== --- flashrom-struct_flashchip_everywhere/w39.c (Revision 1458) +++ flashrom-struct_flashchip_everywhere/w39.c (Arbeitskopie) @@ -26,7 +26,7 @@ chipaddr wrprotect = flash->virtual_registers + offset + 2; uint8_t locking; - locking = chip_readb(wrprotect); + locking = chip_readb(flash, wrprotect); msg_cdbg("Lock status of block at 0x%08x is ", offset); switch (locking & 0x7) { case 0: @@ -64,7 +64,7 @@ chipaddr wrprotect = flash->virtual_registers + offset + 2; uint8_t locking; - locking = chip_readb(wrprotect); + locking = chip_readb(flash, wrprotect); /* Read or write lock present? */ if (locking & ((1 << 2) | (1 << 0))) { /* Lockdown active? */ @@ -73,7 +73,7 @@ return -1; } else { msg_cdbg("Unlocking block at 0x%08x\n", offset); - chip_writeb(0, wrprotect); + chip_writeb(flash, 0, wrprotect); } } @@ -86,18 +86,18 @@ uint8_t val; /* Product Identification Entry */ - chip_writeb(0xAA, bios + 0x5555); - chip_writeb(0x55, bios + 0x2AAA); - chip_writeb(0x90, bios + 0x5555); + chip_writeb(flash, 0xAA, bios + 0x5555); + chip_writeb(flash, 0x55, bios + 0x2AAA); + chip_writeb(flash, 0x90, bios + 0x5555); programmer_delay(10); /* Read something, maybe hardware lock bits */ - val = chip_readb(bios + offset); + val = chip_readb(flash, bios + offset); /* Product Identification Exit */ - chip_writeb(0xAA, bios + 0x5555); - chip_writeb(0x55, bios + 0x2AAA); - chip_writeb(0xF0, bios + 0x5555); + chip_writeb(flash, 0xAA, bios + 0x5555); + chip_writeb(flash, 0x55, bios + 0x2AAA); + chip_writeb(flash, 0xF0, bios + 0x5555); programmer_delay(10); return val; Index: flashrom-struct_flashchip_everywhere/sst49lfxxxc.c =================================================================== --- flashrom-struct_flashchip_everywhere/sst49lfxxxc.c (Revision 1458) +++ flashrom-struct_flashchip_everywhere/sst49lfxxxc.c (Arbeitskopie) @@ -26,8 +26,8 @@ static int write_lockbits_block_49lfxxxc(struct flashchip *flash, unsigned long address, unsigned char bits) { unsigned long lock = flash->virtual_registers + address + 2; - msg_cdbg("lockbits at address=0x%08lx is 0x%01x\n", lock, chip_readb(lock)); - chip_writeb(bits, lock); + msg_cdbg("lockbits at address=0x%08lx is 0x%01x\n", lock, chip_readb(flash, lock)); + chip_writeb(flash, bits, lock); return 0; } @@ -64,8 +64,8 @@ uint8_t status; chipaddr bios = flash->virtual_memory; - chip_writeb(0x30, bios); - chip_writeb(0xD0, bios + address); + chip_writeb(flash, 0x30, bios); + chip_writeb(flash, 0xD0, bios + address); status = wait_82802ab(flash); print_status_82802ab(status); Index: flashrom-struct_flashchip_everywhere/sharplhf00l04.c =================================================================== --- flashrom-struct_flashchip_everywhere/sharplhf00l04.c (Revision 1458) +++ flashrom-struct_flashchip_everywhere/sharplhf00l04.c (Arbeitskopie) @@ -33,18 +33,18 @@ uint8_t status; // clear status register - chip_writeb(0x50, bios); + chip_writeb(flash, 0x50, bios); status = wait_82802ab(flash); print_status_82802ab(status); // clear write protect msg_cspew("write protect is at 0x%lx\n", (wrprotect)); - msg_cspew("write protect is 0x%x\n", chip_readb(wrprotect)); - chip_writeb(0, wrprotect); - msg_cspew("write protect is 0x%x\n", chip_readb(wrprotect)); + msg_cspew("write protect is 0x%x\n", chip_readb(flash, wrprotect)); + chip_writeb(flash, 0, wrprotect); + msg_cspew("write protect is 0x%x\n", chip_readb(flash, wrprotect)); // now start it - chip_writeb(0x20, bios); - chip_writeb(0xd0, bios); + chip_writeb(flash, 0x20, bios); + chip_writeb(flash, 0xd0, bios); programmer_delay(10); // now let's see what the register is status = wait_82802ab(flash); Index: flashrom-struct_flashchip_everywhere/a25.c =================================================================== --- flashrom-struct_flashchip_everywhere/a25.c (Revision 1458) +++ flashrom-struct_flashchip_everywhere/a25.c (Arbeitskopie) @@ -33,7 +33,7 @@ { uint8_t status; - status = spi_read_status_register(); + status = spi_read_status_register(flash); msg_cdbg("Chip status register is %02x\n", status); spi_prettyprint_status_register_amic_a25_srwd(status); @@ -49,7 +49,7 @@ { uint8_t status; - status = spi_read_status_register(); + status = spi_read_status_register(flash); msg_cdbg("Chip status register is %02x\n", status); spi_prettyprint_status_register_amic_a25_srwd(status); @@ -64,7 +64,7 @@ { uint8_t status; - status = spi_read_status_register(); + status = spi_read_status_register(flash); msg_cdbg("Chip status register is %02x\n", status); spi_prettyprint_status_register_amic_a25_srwd(status); @@ -82,7 +82,7 @@ { uint8_t status; - status = spi_read_status_register(); + status = spi_read_status_register(flash); msg_cdbg("Chip status register is %02x\n", status); spi_prettyprint_status_register_amic_a25_srwd(status); Index: flashrom-struct_flashchip_everywhere/dummyflasher.c =================================================================== --- flashrom-struct_flashchip_everywhere/dummyflasher.c (Revision 1458) +++ flashrom-struct_flashchip_everywhere/dummyflasher.c (Arbeitskopie) @@ -60,7 +60,7 @@ static int spi_write_256_chunksize = 256; -static int dummy_spi_send_command(unsigned int writecnt, unsigned int readcnt, +static int dummy_spi_send_command(struct flashchip *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); static int dummy_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); @@ -492,7 +492,7 @@ } #endif -static int dummy_spi_send_command(unsigned int writecnt, unsigned int readcnt, +static int dummy_spi_send_command(struct flashchip *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { int i; Index: flashrom-struct_flashchip_everywhere/sst_fwhub.c =================================================================== --- flashrom-struct_flashchip_everywhere/sst_fwhub.c (Revision 1458) +++ flashrom-struct_flashchip_everywhere/sst_fwhub.c (Arbeitskopie) @@ -29,7 +29,7 @@ chipaddr registers = flash->virtual_registers; uint8_t blockstatus; - blockstatus = chip_readb(registers + offset + 2); + blockstatus = chip_readb(flash, registers + offset + 2); msg_cdbg("Lock status for 0x%06x (size 0x%06x) is %02x, ", offset, flash->page_size, blockstatus); switch (blockstatus & 0x3) { @@ -59,7 +59,7 @@ if (blockstatus) { msg_cdbg("Trying to clear lock for 0x%06x... ", offset); - chip_writeb(0, registers + offset + 2); + chip_writeb(flash, 0, registers + offset + 2); blockstatus = check_sst_fwhub_block_lock(flash, offset); msg_cdbg("%s\n", (blockstatus) ? "failed" : "OK"); Index: flashrom-struct_flashchip_everywhere/at25.c =================================================================== --- flashrom-struct_flashchip_everywhere/at25.c (Revision 1458) +++ flashrom-struct_flashchip_everywhere/at25.c (Arbeitskopie) @@ -61,7 +61,7 @@ { uint8_t status; - status = spi_read_status_register(); + status = spi_read_status_register(flash); msg_cdbg("Chip status register is %02x\n", status); spi_prettyprint_status_register_atmel_at25_srpl(status); @@ -84,7 +84,7 @@ { uint8_t status; - status = spi_read_status_register(); + status = spi_read_status_register(flash); msg_cdbg("Chip status register is %02x\n", status); spi_prettyprint_status_register_atmel_at25_srpl(status); @@ -103,7 +103,7 @@ { uint8_t status; - status = spi_read_status_register(); + status = spi_read_status_register(flash); msg_cdbg("Chip status register is %02x\n", status); msg_cdbg("Chip status register: Status Register Write Protect (WPEN) " @@ -127,7 +127,7 @@ { uint8_t status; - status = spi_read_status_register(); + status = spi_read_status_register(flash); msg_cdbg("Chip status register is %02x\n", status); msg_cdbg("Chip status register: Status Register Write Protect (WPEN) " @@ -151,7 +151,7 @@ { uint8_t status; - status = spi_read_status_register(); + status = spi_read_status_register(flash); msg_cdbg("Chip status register is %02x\n", status); spi_prettyprint_status_register_atmel_at25_srpl(status); @@ -168,7 +168,7 @@ uint8_t status; int result; - status = spi_read_status_register(); + status = spi_read_status_register(flash); /* If block protection is disabled, stop here. */ if ((status & (3 << 2)) == 0) return 0; @@ -195,7 +195,7 @@ msg_cerr("spi_write_status_register failed\n"); return result; } - status = spi_read_status_register(); + status = spi_read_status_register(flash); if ((status & (3 << 2)) != 0) { msg_cerr("Block protection could not be disabled!\n"); return 1; @@ -223,7 +223,7 @@ uint8_t status; int result; - status = spi_read_status_register(); + status = spi_read_status_register(flash); /* If block protection is disabled, stop here. */ if ((status & 0x6c) == 0) return 0; @@ -244,7 +244,7 @@ msg_cerr("spi_write_status_register failed\n"); return result; } - status = spi_read_status_register(); + status = spi_read_status_register(flash); if ((status & 0x6c) != 0) { msg_cerr("Block protection could not be disabled!\n"); return 1; @@ -257,7 +257,7 @@ uint8_t status; int result; - status = spi_read_status_register(); + status = spi_read_status_register(flash); /* If block protection is disabled, stop here. */ if ((status & 0x7c) == 0) return 0; @@ -278,7 +278,7 @@ msg_cerr("spi_write_status_register failed\n"); return result; } - status = spi_read_status_register(); + status = spi_read_status_register(flash); if ((status & 0x7c) != 0) { msg_cerr("Block protection could not be disabled!\n"); return 1; Index: flashrom-struct_flashchip_everywhere/ichspi.c =================================================================== --- flashrom-struct_flashchip_everywhere/ichspi.c (Revision 1458) +++ flashrom-struct_flashchip_everywhere/ichspi.c (Arbeitskopie) @@ -955,7 +955,7 @@ } } -static int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, +static int ich_spi_send_command(struct flashchip *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { int result; @@ -1152,7 +1152,7 @@ } #endif -static int ich_spi_send_multicommand(struct spi_command *cmds) +static int ich_spi_send_multicommand(struct flashchip *flash, struct spi_command *cmds) { int ret = 0; int i; @@ -1202,7 +1202,7 @@ * preoppos matched, this is a normal opcode. */ } - ret = ich_spi_send_command(cmds->writecnt, cmds->readcnt, + ret = ich_spi_send_command(flash, cmds->writecnt, cmds->readcnt, cmds->writearr, cmds->readarr); /* Reset the type of all opcodes to non-atomic. */ for (i = 0; i < 8; i++) Index: flashrom-struct_flashchip_everywhere/82802ab.c =================================================================== --- flashrom-struct_flashchip_everywhere/82802ab.c (Revision 1458) +++ flashrom-struct_flashchip_everywhere/82802ab.c (Arbeitskopie) @@ -47,18 +47,18 @@ int shifted = (flash->feature_bits & FEATURE_ADDR_SHIFTED) != 0; /* Reset to get a clean state */ - chip_writeb(0xFF, bios); + chip_writeb(flash, 0xFF, bios); programmer_delay(10); /* Enter ID mode */ - chip_writeb(0x90, bios); + chip_writeb(flash, 0x90, bios); programmer_delay(10); - id1 = chip_readb(bios + (0x00 << shifted)); - id2 = chip_readb(bios + (0x01 << shifted)); + id1 = chip_readb(flash, bios + (0x00 << shifted)); + id2 = chip_readb(flash, bios + (0x01 << shifted)); /* Leave ID mode */ - chip_writeb(0xFF, bios); + chip_writeb(flash, 0xFF, bios); programmer_delay(10); @@ -71,8 +71,8 @@ * Read the product ID location again. We should now see normal * flash contents. */ - flashcontent1 = chip_readb(bios + (0x00 << shifted)); - flashcontent2 = chip_readb(bios + (0x01 << shifted)); + flashcontent1 = chip_readb(flash, bios + (0x00 << shifted)); + flashcontent2 = chip_readb(flash, bios + (0x01 << shifted)); if (id1 == flashcontent1) msg_cdbg(", id1 is normal flash content"); @@ -94,15 +94,15 @@ uint8_t status; chipaddr bios = flash->virtual_memory; - chip_writeb(0x70, bios); - if ((chip_readb(bios) & 0x80) == 0) { // it's busy - while ((chip_readb(bios) & 0x80) == 0) ; + chip_writeb(flash, 0x70, bios); + if ((chip_readb(flash, bios) & 0x80) == 0) { // it's busy + while ((chip_readb(flash, bios) & 0x80) == 0) ; } - status = chip_readb(bios); + status = chip_readb(flash, bios); /* Reset to get a clean state */ - chip_writeb(0xFF, bios); + chip_writeb(flash, 0xFF, bios); return status; } @@ -113,7 +113,7 @@ //chipaddr wrprotect = flash->virtual_registers + page + 2; for (i = 0; i < flash->total_size * 1024; i+= flash->page_size) - chip_writeb(0, flash->virtual_registers + i + 2); + chip_writeb(flash, 0, flash->virtual_registers + i + 2); return 0; } @@ -125,11 +125,11 @@ uint8_t status; // clear status register - chip_writeb(0x50, bios + page); + chip_writeb(flash, 0x50, bios + page); // now start it - chip_writeb(0x20, bios + page); - chip_writeb(0xd0, bios + page); + chip_writeb(flash, 0x20, bios + page); + chip_writeb(flash, 0xd0, bios + page); programmer_delay(10); // now let's see what the register is @@ -148,8 +148,8 @@ for (i = 0; i < len; i++) { /* transfer data from source to destination */ - chip_writeb(0x40, dst); - chip_writeb(*src++, dst++); + chip_writeb(flash, 0x40, dst); + chip_writeb(flash, *src++, dst++); wait_82802ab(flash); } @@ -164,13 +164,13 @@ int i; /* Clear status register */ - chip_writeb(0x50, bios); + chip_writeb(flash, 0x50, bios); /* Read identifier codes */ - chip_writeb(0x90, bios); + chip_writeb(flash, 0x90, bios); /* Read master lock-bit */ - mcfg = chip_readb(bios + 0x3); + mcfg = chip_readb(flash, bios + 0x3); msg_cdbg("master lock is "); if (mcfg) { msg_cdbg("locked!\n"); @@ -181,7 +181,7 @@ /* Read block lock-bits */ for (i = 0; i < flash->total_size * 1024; i+= (64 * 1024)) { - bcfg = chip_readb(bios + i + 2); // read block lock config + bcfg = chip_readb(flash, bios + i + 2); // read block lock config msg_cdbg("block lock at %06x is %slocked!\n", i, bcfg ? "" : "un"); if (bcfg) { need_unlock = 1; @@ -189,14 +189,14 @@ } /* Reset chip */ - chip_writeb(0xFF, bios); + chip_writeb(flash, 0xFF, bios); /* Unlock: clear block lock-bits, if needed */ if (can_unlock && need_unlock) { msg_cdbg("Unlock: "); - chip_writeb(0x60, bios); - chip_writeb(0xD0, bios); - chip_writeb(0xFF, bios); + chip_writeb(flash, 0x60, bios); + chip_writeb(flash, 0xD0, bios); + chip_writeb(flash, 0xFF, bios); msg_cdbg("Done!\n"); } @@ -220,10 +220,10 @@ wait_82802ab(flash); /* Read identifier codes */ - chip_writeb(0x90, bios); + chip_writeb(flash, 0x90, bios); /* Read master lock-bit */ - mcfg = chip_readb(bios + 0x3); + mcfg = chip_readb(flash, bios + 0x3); msg_cdbg("master lock is "); if (mcfg) { msg_cdbg("locked!\n"); @@ -235,7 +235,7 @@ /* Read block lock-bits, 8 * 8 KB + 15 * 64 KB */ for (i = 0; i < flash->total_size * 1024; i += (i >= (64 * 1024) ? 64 * 1024 : 8 * 1024)) { - bcfg = chip_readb(bios + i + 2); /* read block lock config */ + bcfg = chip_readb(flash, bios + i + 2); /* read block lock config */ msg_cdbg("block lock at %06x is %slocked!\n", i, bcfg ? "" : "un"); if (bcfg) @@ -243,14 +243,14 @@ } /* Reset chip */ - chip_writeb(0xFF, bios); + chip_writeb(flash, 0xFF, bios); /* Unlock: clear block lock-bits, if needed */ if (can_unlock && need_unlock) { msg_cdbg("Unlock: "); - chip_writeb(0x60, bios); - chip_writeb(0xD0, bios); - chip_writeb(0xFF, bios); + chip_writeb(flash, 0x60, bios); + chip_writeb(flash, 0xD0, bios); + chip_writeb(flash, 0xFF, bios); wait_82802ab(flash); msg_cdbg("Done!\n"); } Index: flashrom-struct_flashchip_everywhere/dediprog.c =================================================================== --- flashrom-struct_flashchip_everywhere/dediprog.c (Revision 1458) +++ flashrom-struct_flashchip_everywhere/dediprog.c (Arbeitskopie) @@ -317,7 +317,7 @@ return ret; } -static int dediprog_spi_send_command(unsigned int writecnt, unsigned int readcnt, +static int dediprog_spi_send_command(struct flashchip *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { int ret; Index: flashrom-struct_flashchip_everywhere/spi25.c =================================================================== --- flashrom-struct_flashchip_everywhere/spi25.c (Revision 1458) +++ flashrom-struct_flashchip_everywhere/spi25.c (Arbeitskopie) @@ -29,13 +29,13 @@ #include "programmer.h" #include "spi.h" -static int spi_rdid(unsigned char *readarr, int bytes) +static int spi_rdid(struct flashchip *flash, unsigned char *readarr, int bytes) { static const unsigned char cmd[JEDEC_RDID_OUTSIZE] = { JEDEC_RDID }; int ret; int i; - ret = spi_send_command(sizeof(cmd), bytes, cmd, readarr); + ret = spi_send_command(flash, sizeof(cmd), bytes, cmd, readarr); if (ret) return ret; msg_cspew("RDID returned"); @@ -45,20 +45,20 @@ return 0; } -static int spi_rems(unsigned char *readarr) +static int spi_rems(struct flashchip *flash, unsigned char *readarr) { unsigned char cmd[JEDEC_REMS_OUTSIZE] = { JEDEC_REMS, 0, 0, 0 }; uint32_t readaddr; int ret; - ret = spi_send_command(sizeof(cmd), JEDEC_REMS_INSIZE, cmd, readarr); + ret = spi_send_command(flash, sizeof(cmd), JEDEC_REMS_INSIZE, cmd, readarr); if (ret == SPI_INVALID_ADDRESS) { /* Find the lowest even address allowed for reads. */ - readaddr = (spi_get_valid_read_addr() + 1) & ~1; + readaddr = (spi_get_valid_read_addr(flash) + 1) & ~1; cmd[1] = (readaddr >> 16) & 0xff, cmd[2] = (readaddr >> 8) & 0xff, cmd[3] = (readaddr >> 0) & 0xff, - ret = spi_send_command(sizeof(cmd), JEDEC_REMS_INSIZE, cmd, readarr); + ret = spi_send_command(flash, sizeof(cmd), JEDEC_REMS_INSIZE, cmd, readarr); } if (ret) return ret; @@ -66,21 +66,21 @@ return 0; } -static int spi_res(unsigned char *readarr, int bytes) +static int spi_res(struct flashchip *flash, unsigned char *readarr, int bytes) { unsigned char cmd[JEDEC_RES_OUTSIZE] = { JEDEC_RES, 0, 0, 0 }; uint32_t readaddr; int ret; int i; - ret = spi_send_command(sizeof(cmd), bytes, cmd, readarr); + ret = spi_send_command(flash, sizeof(cmd), bytes, cmd, readarr); if (ret == SPI_INVALID_ADDRESS) { /* Find the lowest even address allowed for reads. */ - readaddr = (spi_get_valid_read_addr() + 1) & ~1; + readaddr = (spi_get_valid_read_addr(flash) + 1) & ~1; cmd[1] = (readaddr >> 16) & 0xff, cmd[2] = (readaddr >> 8) & 0xff, cmd[3] = (readaddr >> 0) & 0xff, - ret = spi_send_command(sizeof(cmd), bytes, cmd, readarr); + ret = spi_send_command(flash, sizeof(cmd), bytes, cmd, readarr); } if (ret) return ret; @@ -91,13 +91,13 @@ return 0; } -int spi_write_enable(void) +int spi_write_enable(struct flashchip *flash) { static const unsigned char cmd[JEDEC_WREN_OUTSIZE] = { JEDEC_WREN }; int result; /* Send WREN (Write Enable) */ - result = spi_send_command(sizeof(cmd), 0, cmd, NULL); + result = spi_send_command(flash, sizeof(cmd), 0, cmd, NULL); if (result) msg_cerr("%s failed\n", __func__); @@ -105,12 +105,12 @@ return result; } -int spi_write_disable(void) +int spi_write_disable(struct flashchip *flash) { static const unsigned char cmd[JEDEC_WRDI_OUTSIZE] = { JEDEC_WRDI }; /* Send WRDI (Write Disable) */ - return spi_send_command(sizeof(cmd), 0, cmd, NULL); + return spi_send_command(flash, sizeof(cmd), 0, cmd, NULL); } static int probe_spi_rdid_generic(struct flashchip *flash, int bytes) @@ -119,7 +119,7 @@ uint32_t id1; uint32_t id2; - if (spi_rdid(readarr, bytes)) { + if (spi_rdid(flash, readarr, bytes)) { return 0; } @@ -199,7 +199,7 @@ unsigned char readarr[JEDEC_REMS_INSIZE]; uint32_t id1, id2; - if (spi_rems(readarr)) { + if (spi_rems(flash, readarr)) { return 0; } @@ -242,7 +242,7 @@ /* Check if RDID is usable and does not return 0xff 0xff 0xff or * 0x00 0x00 0x00. In that case, RES is pointless. */ - if (!spi_rdid(readarr, 3) && memcmp(readarr, allff, 3) && + if (!spi_rdid(flash, readarr, 3) && memcmp(readarr, allff, 3) && memcmp(readarr, all00, 3)) { msg_cdbg("Ignoring RES in favour of RDID.\n"); return 0; @@ -250,13 +250,13 @@ /* Check if REMS is usable and does not return 0xff 0xff or * 0x00 0x00. In that case, RES is pointless. */ - if (!spi_rems(readarr) && memcmp(readarr, allff, JEDEC_REMS_INSIZE) && + if (!spi_rems(flash, readarr) && memcmp(readarr, allff, JEDEC_REMS_INSIZE) && memcmp(readarr, all00, JEDEC_REMS_INSIZE)) { msg_cdbg("Ignoring RES in favour of REMS.\n"); return 0; } - if (spi_res(readarr, 1)) { + if (spi_res(flash, readarr, 1)) { return 0; } @@ -279,7 +279,7 @@ unsigned char readarr[2]; uint32_t id1, id2; - if (spi_res(readarr, 2)) { + if (spi_res(flash, readarr, 2)) { return 0; } @@ -298,7 +298,7 @@ return 1; } -uint8_t spi_read_status_register(void) +uint8_t spi_read_status_register(struct flashchip *flash) { static const unsigned char cmd[JEDEC_RDSR_OUTSIZE] = { JEDEC_RDSR }; /* FIXME: No workarounds for driver/hardware bugs in generic code. */ @@ -306,7 +306,7 @@ int ret; /* Read Status Register */ - ret = spi_send_command(sizeof(cmd), sizeof(readarr), cmd, readarr); + ret = spi_send_command(flash, sizeof(cmd), sizeof(readarr), cmd, readarr); if (ret) msg_cerr("RDSR failed!\n"); @@ -414,7 +414,7 @@ { uint8_t status; - status = spi_read_status_register(); + status = spi_read_status_register(flash); msg_cdbg("Chip status register is %02x\n", status); switch (flash->manufacture_id) { case ST_ID: @@ -465,7 +465,7 @@ .readarr = NULL, }}; - result = spi_send_multicommand(cmds); + result = spi_send_multicommand(flash, cmds); if (result) { msg_cerr("%s failed during command execution\n", __func__); @@ -475,7 +475,7 @@ * This usually takes 1-85 s, so wait in 1 s steps. */ /* FIXME: We assume spi_read_status_register will never fail. */ - while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) + while (spi_read_status_register(flash) & JEDEC_RDSR_BIT_WIP) programmer_delay(1000 * 1000); /* FIXME: Check the status register for errors. */ return 0; @@ -502,7 +502,7 @@ .readarr = NULL, }}; - result = spi_send_multicommand(cmds); + result = spi_send_multicommand(flash, cmds); if (result) { msg_cerr("%s failed during command execution\n", __func__); return result; @@ -511,7 +511,7 @@ * This usually takes 1-85 s, so wait in 1 s steps. */ /* FIXME: We assume spi_read_status_register will never fail. */ - while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) + while (spi_read_status_register(flash) & JEDEC_RDSR_BIT_WIP) programmer_delay(1000 * 1000); /* FIXME: Check the status register for errors. */ return 0; @@ -543,7 +543,7 @@ .readarr = NULL, }}; - result = spi_send_multicommand(cmds); + result = spi_send_multicommand(flash, cmds); if (result) { msg_cerr("%s failed during command execution at address 0x%x\n", __func__, addr); @@ -552,7 +552,7 @@ /* Wait until the Write-In-Progress bit is cleared. * This usually takes 100-4000 ms, so wait in 100 ms steps. */ - while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) + while (spi_read_status_register(flash) & JEDEC_RDSR_BIT_WIP) programmer_delay(100 * 1000); /* FIXME: Check the status register for errors. */ return 0; @@ -589,7 +589,7 @@ .readarr = NULL, }}; - result = spi_send_multicommand(cmds); + result = spi_send_multicommand(flash, cmds); if (result) { msg_cerr("%s failed during command execution at address 0x%x\n", __func__, addr); @@ -598,7 +598,7 @@ /* Wait until the Write-In-Progress bit is cleared. * This usually takes 100-4000 ms, so wait in 100 ms steps. */ - while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) + while (spi_read_status_register(flash) & JEDEC_RDSR_BIT_WIP) programmer_delay(100 * 1000); /* FIXME: Check the status register for errors. */ return 0; @@ -633,7 +633,7 @@ .readarr = NULL, }}; - result = spi_send_multicommand(cmds); + result = spi_send_multicommand(flash, cmds); if (result) { msg_cerr("%s failed during command execution at address 0x%x\n", __func__, addr); @@ -642,7 +642,7 @@ /* Wait until the Write-In-Progress bit is cleared. * This usually takes 100-4000 ms, so wait in 100 ms steps. */ - while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) + while (spi_read_status_register(flash) & JEDEC_RDSR_BIT_WIP) programmer_delay(100 * 1000); /* FIXME: Check the status register for errors. */ return 0; @@ -675,7 +675,7 @@ .readarr = NULL, }}; - result = spi_send_multicommand(cmds); + result = spi_send_multicommand(flash, cmds); if (result) { msg_cerr("%s failed during command execution at address 0x%x\n", __func__, addr); @@ -684,7 +684,7 @@ /* Wait until the Write-In-Progress bit is cleared. * This usually takes 15-800 ms, so wait in 10 ms steps. */ - while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) + while (spi_read_status_register(flash) & JEDEC_RDSR_BIT_WIP) programmer_delay(10 * 1000); /* FIXME: Check the status register for errors. */ return 0; @@ -710,13 +710,13 @@ return spi_chip_erase_c7(flash); } -int spi_write_status_enable(void) +int spi_write_status_enable(struct flashchip *flash) { static const unsigned char cmd[JEDEC_EWSR_OUTSIZE] = { JEDEC_EWSR }; int result; /* Send EWSR (Enable Write Status Register). */ - result = spi_send_command(sizeof(cmd), JEDEC_EWSR_INSIZE, cmd, NULL); + result = spi_send_command(flash, sizeof(cmd), JEDEC_EWSR_INSIZE, cmd, NULL); if (result) msg_cerr("%s failed\n", __func__); @@ -751,7 +751,7 @@ .readarr = NULL, }}; - result = spi_send_multicommand(cmds); + result = spi_send_multicommand(flash, cmds); if (result) { msg_cerr("%s failed during command execution\n", __func__); @@ -766,7 +766,7 @@ * 100 ms, then wait in 10 ms steps until a total of 5 s have elapsed. */ programmer_delay(100 * 1000); - while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) { + while (spi_read_status_register(flash) & JEDEC_RDSR_BIT_WIP) { if (++i > 490) { msg_cerr("Error: WIP bit after WRSR never cleared\n"); return TIMEOUT_ERROR; @@ -799,7 +799,7 @@ .readarr = NULL, }}; - result = spi_send_multicommand(cmds); + result = spi_send_multicommand(flash, cmds); if (result) { msg_cerr("%s failed during command execution\n", __func__); @@ -814,7 +814,7 @@ * 100 ms, then wait in 10 ms steps until a total of 5 s have elapsed. */ programmer_delay(100 * 1000); - while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) { + while (spi_read_status_register(flash) & JEDEC_RDSR_BIT_WIP) { if (++i > 490) { msg_cerr("Error: WIP bit after WRSR never cleared\n"); return TIMEOUT_ERROR; @@ -840,7 +840,7 @@ return ret; } -int spi_byte_program(int addr, uint8_t databyte) +int spi_byte_program(struct flashchip *flash, int addr, uint8_t databyte) { int result; struct spi_command cmds[] = { @@ -867,7 +867,7 @@ .readarr = NULL, }}; - result = spi_send_multicommand(cmds); + result = spi_send_multicommand(flash, cmds); if (result) { msg_cerr("%s failed during command execution at address 0x%x\n", __func__, addr); @@ -875,7 +875,7 @@ return result; } -int spi_nbyte_program(int addr, uint8_t *bytes, int len) +int spi_nbyte_program(struct flashchip *flash, int addr, uint8_t *bytes, int len) { int result; /* FIXME: Switch to malloc based on len unless that kills speed. */ @@ -914,7 +914,7 @@ memcpy(&cmd[4], bytes, len); - result = spi_send_multicommand(cmds); + result = spi_send_multicommand(flash, cmds); if (result) { msg_cerr("%s failed during command execution at address 0x%x\n", __func__, addr); @@ -931,7 +931,7 @@ uint8_t status; int result; - status = spi_read_status_register(); + status = spi_read_status_register(flash); /* If block protection is disabled, stop here. */ if ((status & 0x3c) == 0) return 0; @@ -942,7 +942,7 @@ msg_cerr("spi_write_status_register failed\n"); return result; } - status = spi_read_status_register(); + status = spi_read_status_register(flash); if ((status & 0x3c) != 0) { msg_cerr("Block protection could not be disabled!\n"); return 1; @@ -950,7 +950,7 @@ return 0; } -int spi_nbyte_read(int address, uint8_t *bytes, int len) +int spi_nbyte_read(struct flashchip *flash, int address, uint8_t *bytes, int len) { const unsigned char cmd[JEDEC_READ_OUTSIZE] = { JEDEC_READ, @@ -960,7 +960,7 @@ }; /* Send Read */ - return spi_send_command(sizeof(cmd), len, cmd, bytes); + return spi_send_command(flash, sizeof(cmd), len, cmd, bytes); } /* @@ -992,7 +992,7 @@ lenhere = min(start + len, (i + 1) * page_size) - starthere; for (j = 0; j < lenhere; j += chunksize) { toread = min(chunksize, lenhere - j); - rc = spi_nbyte_read(starthere + j, buf + starthere - start + j, toread); + rc = spi_nbyte_read(flash, starthere + j, buf + starthere - start + j, toread); if (rc) break; } @@ -1037,10 +1037,10 @@ lenhere = min(start + len, (i + 1) * page_size) - starthere; for (j = 0; j < lenhere; j += chunksize) { towrite = min(chunksize, lenhere - j); - rc = spi_nbyte_program(starthere + j, buf + starthere - start + j, towrite); + rc = spi_nbyte_program(flash, starthere + j, buf + starthere - start + j, towrite); if (rc) break; - while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) + while (spi_read_status_register(flash) & JEDEC_RDSR_BIT_WIP) programmer_delay(10); } if (rc) @@ -1062,10 +1062,10 @@ int i, result = 0; for (i = start; i < start + len; i++) { - result = spi_byte_program(i, buf[i - start]); + result = spi_byte_program(flash, i, buf[i - start]); if (result) return 1; - while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) + while (spi_read_status_register(flash) & JEDEC_RDSR_BIT_WIP) programmer_delay(10); } @@ -1150,7 +1150,7 @@ } - result = spi_send_multicommand(cmds); + result = spi_send_multicommand(flash, cmds); if (result) { msg_cerr("%s failed during start command execution\n", __func__); @@ -1159,7 +1159,7 @@ */ return result; } - while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) + while (spi_read_status_register(flash) & JEDEC_RDSR_BIT_WIP) programmer_delay(10); /* We already wrote 2 bytes in the multicommand step. */ @@ -1169,15 +1169,15 @@ while (pos < start + len - 1) { cmd[1] = buf[pos++ - start]; cmd[2] = buf[pos++ - start]; - spi_send_command(JEDEC_AAI_WORD_PROGRAM_CONT_OUTSIZE, 0, cmd, NULL); - while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) + spi_send_command(flash, JEDEC_AAI_WORD_PROGRAM_CONT_OUTSIZE, 0, cmd, NULL); + while (spi_read_status_register(flash) & JEDEC_RDSR_BIT_WIP) programmer_delay(10); } /* Use WRDI to exit AAI mode. This needs to be done before issuing any * other non-AAI command. */ - spi_write_disable(); + spi_write_disable(flash); /* Write remaining byte (if any). */ if (pos < start + len) { Index: flashrom-struct_flashchip_everywhere/pm49fl00x.c =================================================================== --- flashrom-struct_flashchip_everywhere/pm49fl00x.c (Revision 1458) +++ flashrom-struct_flashchip_everywhere/pm49fl00x.c (Arbeitskopie) @@ -22,7 +22,7 @@ #include "flash.h" -static void write_lockbits_49fl00x(chipaddr bios, int size, +static void write_lockbits_49fl00x(const struct flashchip *flash, chipaddr bios, int size, unsigned char bits, int block_size) { int i, left = size; @@ -32,18 +32,18 @@ if (block_size == 16384 && i % 2) continue; - chip_writeb(bits, bios + (i * block_size) + 2); + chip_writeb(flash, bits, bios + (i * block_size) + 2); } } int unlock_49fl00x(struct flashchip *flash) { - write_lockbits_49fl00x(flash->virtual_registers, flash->total_size * 1024, 0, flash->page_size); + write_lockbits_49fl00x(flash, flash->virtual_registers, flash->total_size * 1024, 0, flash->page_size); return 0; } int lock_49fl00x(struct flashchip *flash) { - write_lockbits_49fl00x(flash->virtual_registers, flash->total_size * 1024, 1, flash->page_size); + write_lockbits_49fl00x(flash, flash->virtual_registers, flash->total_size * 1024, 1, flash->page_size); return 0; } Index: flashrom-struct_flashchip_everywhere/it85spi.c =================================================================== --- flashrom-struct_flashchip_everywhere/it85spi.c (Revision 1458) +++ flashrom-struct_flashchip_everywhere/it85spi.c (Arbeitskopie) @@ -268,7 +268,7 @@ return 0; } -static int it85xx_spi_send_command(unsigned int writecnt, unsigned int readcnt, +static int it85xx_spi_send_command(struct flashchip *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); static const struct spi_programmer spi_programmer_it85xx = { @@ -310,7 +310,7 @@ * 3. read date from LPC/FWH address 0xffff_fdxxh (drive CE# low and get * data from MISO) */ -static int it85xx_spi_send_command(unsigned int writecnt, unsigned int readcnt, +static int it85xx_spi_send_command(struct flashchip *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { int i; Index: flashrom-struct_flashchip_everywhere/buspirate_spi.c =================================================================== --- flashrom-struct_flashchip_everywhere/buspirate_spi.c (Revision 1458) +++ flashrom-struct_flashchip_everywhere/buspirate_spi.c (Arbeitskopie) @@ -86,7 +86,7 @@ return 0; } -static int buspirate_spi_send_command(unsigned int writecnt, unsigned int readcnt, +static int buspirate_spi_send_command(struct flashchip *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); static const struct spi_programmer spi_programmer_buspirate = { @@ -291,7 +291,7 @@ return 0; } -static int buspirate_spi_send_command(unsigned int writecnt, unsigned int readcnt, +static int buspirate_spi_send_command(struct flashchip *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { static unsigned char *buf = NULL; Index: flashrom-struct_flashchip_everywhere/linux_spi.c =================================================================== --- flashrom-struct_flashchip_everywhere/linux_spi.c (Revision 1458) +++ flashrom-struct_flashchip_everywhere/linux_spi.c (Arbeitskopie) @@ -34,7 +34,7 @@ static int fd = -1; static int linux_spi_shutdown(void *data); -static int linux_spi_send_command(unsigned int writecnt, unsigned int readcnt, +static int linux_spi_send_command(struct flashchip *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *txbuf, unsigned char *rxbuf); static int linux_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); @@ -107,7 +107,7 @@ return 0; } -static int linux_spi_send_command(unsigned int writecnt, unsigned int readcnt, +static int linux_spi_send_command(struct flashchip *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *txbuf, unsigned char *rxbuf) { struct spi_ioc_transfer msg[2] = { Index: flashrom-struct_flashchip_everywhere/w29ee011.c =================================================================== --- flashrom-struct_flashchip_everywhere/w29ee011.c (Revision 1458) +++ flashrom-struct_flashchip_everywhere/w29ee011.c (Arbeitskopie) @@ -38,29 +38,29 @@ } /* Issue JEDEC Product ID Entry command */ - chip_writeb(0xAA, bios + 0x5555); + chip_writeb(flash, 0xAA, bios + 0x5555); programmer_delay(10); - chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(flash, 0x55, bios + 0x2AAA); programmer_delay(10); - chip_writeb(0x80, bios + 0x5555); + chip_writeb(flash, 0x80, bios + 0x5555); programmer_delay(10); - chip_writeb(0xAA, bios + 0x5555); + chip_writeb(flash, 0xAA, bios + 0x5555); programmer_delay(10); - chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(flash, 0x55, bios + 0x2AAA); programmer_delay(10); - chip_writeb(0x60, bios + 0x5555); + chip_writeb(flash, 0x60, bios + 0x5555); programmer_delay(10); /* Read product ID */ - id1 = chip_readb(bios); - id2 = chip_readb(bios + 0x01); + id1 = chip_readb(flash, bios); + id2 = chip_readb(flash, bios + 0x01); /* Issue JEDEC Product ID Exit command */ - chip_writeb(0xAA, bios + 0x5555); + chip_writeb(flash, 0xAA, bios + 0x5555); programmer_delay(10); - chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(flash, 0x55, bios + 0x2AAA); programmer_delay(10); - chip_writeb(0xF0, bios + 0x5555); + chip_writeb(flash, 0xF0, bios + 0x5555); programmer_delay(10); msg_cdbg("%s: id1 0x%02x, id2 0x%02x\n", __func__, id1, id2); Index: flashrom-struct_flashchip_everywhere/spi.c =================================================================== --- flashrom-struct_flashchip_everywhere/spi.c (Revision 1458) +++ flashrom-struct_flashchip_everywhere/spi.c (Arbeitskopie) @@ -42,7 +42,7 @@ const struct spi_programmer *spi_programmer = &spi_programmer_none; -int spi_send_command(unsigned int writecnt, unsigned int readcnt, +int spi_send_command(struct flashchip *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { if (!spi_programmer->command) { @@ -52,11 +52,11 @@ return 1; } - return spi_programmer->command(writecnt, readcnt, + return spi_programmer->command(flash, writecnt, readcnt, writearr, readarr); } -int spi_send_multicommand(struct spi_command *cmds) +int spi_send_multicommand(struct flashchip *flash, struct spi_command *cmds) { if (!spi_programmer->multicommand) { msg_perr("%s called, but SPI is unsupported on this " @@ -65,10 +65,10 @@ return 1; } - return spi_programmer->multicommand(cmds); + return spi_programmer->multicommand(flash, cmds); } -int default_spi_send_command(unsigned int writecnt, unsigned int readcnt, +int default_spi_send_command(struct flashchip *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { struct spi_command cmd[] = { @@ -84,14 +84,14 @@ .readarr = NULL, }}; - return spi_send_multicommand(cmd); + return spi_send_multicommand(flash, cmd); } -int default_spi_send_multicommand(struct spi_command *cmds) +int default_spi_send_multicommand(struct flashchip *flash, struct spi_command *cmds) { int result = 0; for (; (cmds->writecnt || cmds->readcnt) && !result; cmds++) { - result = spi_send_command(cmds->writecnt, cmds->readcnt, + result = spi_send_command(flash, cmds->writecnt, cmds->readcnt, cmds->writearr, cmds->readarr); } return result; @@ -135,7 +135,7 @@ * address. Highest possible address with the current SPI implementation * means 0xffffff, the highest unsigned 24bit number. */ - addrbase = spi_get_valid_read_addr(); + addrbase = spi_get_valid_read_addr(flash); if (addrbase + flash->total_size * 1024 > (1 << 24)) { msg_perr("Flash chip size exceeds the allowed access window. "); msg_perr("Read will probably fail.\n"); @@ -177,7 +177,7 @@ * be the lowest allowed address for all commands which take an address. * This is a programmer limitation. */ -uint32_t spi_get_valid_read_addr(void) +uint32_t spi_get_valid_read_addr(struct flashchip *flash) { switch (spi_programmer->type) { #if CONFIG_INTERNAL == 1 Index: flashrom-struct_flashchip_everywhere/ft2232_spi.c =================================================================== --- flashrom-struct_flashchip_everywhere/ft2232_spi.c (Revision 1458) +++ flashrom-struct_flashchip_everywhere/ft2232_spi.c (Arbeitskopie) @@ -144,7 +144,7 @@ return 0; } -static int ft2232_spi_send_command(unsigned int writecnt, unsigned int readcnt, +static int ft2232_spi_send_command(struct flashchip *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); static const struct spi_programmer spi_programmer_ft2232 = { @@ -342,7 +342,7 @@ } /* Returns 0 upon success, a negative number upon errors. */ -static int ft2232_spi_send_command(unsigned int writecnt, unsigned int readcnt, +static int ft2232_spi_send_command(struct flashchip *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { struct ftdi_context *ftdic = &ftdic_context; Index: flashrom-struct_flashchip_everywhere/wbsio_spi.c =================================================================== --- flashrom-struct_flashchip_everywhere/wbsio_spi.c (Revision 1458) +++ flashrom-struct_flashchip_everywhere/wbsio_spi.c (Arbeitskopie) @@ -60,7 +60,7 @@ return flashport; } -static int wbsio_spi_send_command(unsigned int writecnt, unsigned int readcnt, +static int wbsio_spi_send_command(struct flashchip *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); static int wbsio_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); @@ -110,7 +110,7 @@ * Would one more byte of RAM in the chip (to get all 24 bits) really make * such a big difference? */ -static int wbsio_spi_send_command(unsigned int writecnt, unsigned int readcnt, +static int wbsio_spi_send_command(struct flashchip *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { int i; Index: flashrom-struct_flashchip_everywhere/sst28sf040.c =================================================================== --- flashrom-struct_flashchip_everywhere/sst28sf040.c (Revision 1458) +++ flashrom-struct_flashchip_everywhere/sst28sf040.c (Arbeitskopie) @@ -34,13 +34,13 @@ { chipaddr bios = flash->virtual_memory; - chip_readb(bios + 0x1823); - chip_readb(bios + 0x1820); - chip_readb(bios + 0x1822); - chip_readb(bios + 0x0418); - chip_readb(bios + 0x041B); - chip_readb(bios + 0x0419); - chip_readb(bios + 0x040A); + chip_readb(flash, bios + 0x1823); + chip_readb(flash, bios + 0x1820); + chip_readb(flash, bios + 0x1822); + chip_readb(flash, bios + 0x0418); + chip_readb(flash, bios + 0x041B); + chip_readb(flash, bios + 0x0419); + chip_readb(flash, bios + 0x040A); return 0; } @@ -49,13 +49,13 @@ { chipaddr bios = flash->virtual_memory; - chip_readb(bios + 0x1823); - chip_readb(bios + 0x1820); - chip_readb(bios + 0x1822); - chip_readb(bios + 0x0418); - chip_readb(bios + 0x041B); - chip_readb(bios + 0x0419); - chip_readb(bios + 0x041A); + chip_readb(flash, bios + 0x1823); + chip_readb(flash, bios + 0x1820); + chip_readb(flash, bios + 0x1822); + chip_readb(flash, bios + 0x0418); + chip_readb(flash, bios + 0x041B); + chip_readb(flash, bios + 0x0419); + chip_readb(flash, bios + 0x041A); return 0; } @@ -65,11 +65,11 @@ chipaddr bios = flash->virtual_memory; /* This command sequence is very similar to erase_block_82802ab. */ - chip_writeb(AUTO_PG_ERASE1, bios); - chip_writeb(AUTO_PG_ERASE2, bios + address); + chip_writeb(flash, AUTO_PG_ERASE1, bios); + chip_writeb(flash, AUTO_PG_ERASE2, bios + address); /* wait for Toggle bit ready */ - toggle_ready_jedec(bios); + toggle_ready_jedec(flash, bios); /* FIXME: Check the status register for errors. */ return 0; @@ -90,11 +90,11 @@ continue; } /*issue AUTO PROGRAM command */ - chip_writeb(AUTO_PGRM, dst); - chip_writeb(*src++, dst++); + chip_writeb(flash, AUTO_PGRM, dst); + chip_writeb(flash, *src++, dst++); /* wait for Toggle bit ready */ - toggle_ready_jedec(bios); + toggle_ready_jedec(flash, bios); } return 0; @@ -104,11 +104,11 @@ { chipaddr bios = flash->virtual_memory; - chip_writeb(CHIP_ERASE, bios); - chip_writeb(CHIP_ERASE, bios); + chip_writeb(flash, CHIP_ERASE, bios); + chip_writeb(flash, CHIP_ERASE, bios); programmer_delay(10); - toggle_ready_jedec(bios); + toggle_ready_jedec(flash, bios); /* FIXME: Check the status register for errors. */ return 0; Index: flashrom-struct_flashchip_everywhere/stm50flw0x0x.c =================================================================== --- flashrom-struct_flashchip_everywhere/stm50flw0x0x.c (Revision 1458) +++ flashrom-struct_flashchip_everywhere/stm50flw0x0x.c (Arbeitskopie) @@ -60,8 +60,8 @@ // unlock each 4k-sector for (j = 0; j < 0x10000; j += 0x1000) { msg_cdbg("unlocking at 0x%x\n", offset + j); - chip_writeb(unlock_sector, wrprotect + offset + j); - if (chip_readb(wrprotect + offset + j) != unlock_sector) { + chip_writeb(flash, unlock_sector, wrprotect + offset + j); + if (chip_readb(flash, wrprotect + offset + j) != unlock_sector) { msg_cerr("Cannot unlock sector @ 0x%x\n", offset + j); return -1; @@ -69,8 +69,8 @@ } } else { msg_cdbg("unlocking at 0x%x\n", offset); - chip_writeb(unlock_sector, wrprotect + offset); - if (chip_readb(wrprotect + offset) != unlock_sector) { + chip_writeb(flash, unlock_sector, wrprotect + offset); + if (chip_readb(flash, wrprotect + offset) != unlock_sector) { msg_cerr("Cannot unlock sector @ 0x%x\n", offset); return -1; } @@ -99,10 +99,10 @@ chipaddr bios = flash->virtual_memory + sector; // clear status register - chip_writeb(0x50, bios); + chip_writeb(flash, 0x50, bios); // now start it - chip_writeb(0x32, bios); - chip_writeb(0xd0, bios); + chip_writeb(flash, 0x32, bios); + chip_writeb(flash, 0xd0, bios); programmer_delay(10); wait_82802ab(flash); Index: flashrom-struct_flashchip_everywhere/sb600spi.c =================================================================== --- flashrom-struct_flashchip_everywhere/sb600spi.c (Revision 1458) +++ flashrom-struct_flashchip_everywhere/sb600spi.c (Arbeitskopie) @@ -88,7 +88,7 @@ ; } -static int sb600_spi_send_command(unsigned int writecnt, unsigned int readcnt, +static int sb600_spi_send_command(struct flashchip *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { int count; Index: flashrom-struct_flashchip_everywhere/programmer.c =================================================================== --- flashrom-struct_flashchip_everywhere/programmer.c (Revision 1458) +++ flashrom-struct_flashchip_everywhere/programmer.c (Arbeitskopie) @@ -39,60 +39,60 @@ } /* No-op chip_writeb() for drivers not supporting addr/data pair accesses */ -uint8_t noop_chip_readb(const chipaddr addr) +uint8_t noop_chip_readb(struct flashchip *flash, const chipaddr addr) { return 0xff; } /* No-op chip_writeb() for drivers not supporting addr/data pair accesses */ -void noop_chip_writeb(uint8_t val, chipaddr addr) +void noop_chip_writeb(struct flashchip *flash, uint8_t val, chipaddr addr) { } /* Little-endian fallback for drivers not supporting 16 bit accesses */ -void fallback_chip_writew(uint16_t val, chipaddr addr) +void fallback_chip_writew(const struct flashchip *flash, uint16_t val, chipaddr addr) { - chip_writeb(val & 0xff, addr); - chip_writeb((val >> 8) & 0xff, addr + 1); + chip_writeb(flash, val & 0xff, addr); + chip_writeb(flash, (val >> 8) & 0xff, addr + 1); } /* Little-endian fallback for drivers not supporting 16 bit accesses */ -uint16_t fallback_chip_readw(const chipaddr addr) +uint16_t fallback_chip_readw(struct flashchip *flash, const chipaddr addr) { uint16_t val; - val = chip_readb(addr); - val |= chip_readb(addr + 1) << 8; + val = chip_readb(flash, addr); + val |= chip_readb(flash, addr + 1) << 8; return val; } /* Little-endian fallback for drivers not supporting 32 bit accesses */ -void fallback_chip_writel(uint32_t val, chipaddr addr) +void fallback_chip_writel(const struct flashchip *flash, uint32_t val, chipaddr addr) { - chip_writew(val & 0xffff, addr); - chip_writew((val >> 16) & 0xffff, addr + 2); + chip_writew(flash, val & 0xffff, addr); + chip_writew(flash, (val >> 16) & 0xffff, addr + 2); } /* Little-endian fallback for drivers not supporting 32 bit accesses */ -uint32_t fallback_chip_readl(const chipaddr addr) +uint32_t fallback_chip_readl(struct flashchip *flash, const chipaddr addr) { uint32_t val; - val = chip_readw(addr); - val |= chip_readw(addr + 2) << 16; + val = chip_readw(flash, addr); + val |= chip_readw(flash, addr + 2) << 16; return val; } -void fallback_chip_writen(uint8_t *buf, chipaddr addr, size_t len) +void fallback_chip_writen(const struct flashchip *flash, uint8_t *buf, chipaddr addr, size_t len) { size_t i; for (i = 0; i < len; i++) - chip_writeb(buf[i], addr + i); + chip_writeb(flash, buf[i], addr + i); return; } -void fallback_chip_readn(uint8_t *buf, chipaddr addr, size_t len) +void fallback_chip_readn(struct flashchip *flash, uint8_t *buf, chipaddr addr, size_t len) { size_t i; for (i = 0; i < len; i++) - buf[i] = chip_readb(addr + i); + buf[i] = chip_readb(flash, addr + i); return; } Index: flashrom-struct_flashchip_everywhere/flashrom.c =================================================================== --- flashrom-struct_flashchip_everywhere/flashrom.c (Revision 1458) +++ flashrom-struct_flashchip_everywhere/flashrom.c (Arbeitskopie) @@ -511,43 +511,47 @@ programmer_table[programmer].unmap_flash_region(virt_addr, len); } -void chip_writeb(uint8_t val, chipaddr addr) +void chip_writeb(const struct flashchip *flash, uint8_t val, chipaddr addr) { programmer_table[programmer].chip_writeb(val, addr); } -void chip_writew(uint16_t val, chipaddr addr) +void chip_writew(const struct flashchip *flash, uint16_t val, chipaddr addr) { programmer_table[programmer].chip_writew(val, addr); } -void chip_writel(uint32_t val, chipaddr addr) +void chip_writel(const struct flashchip *flash, uint32_t val, chipaddr addr) { programmer_table[programmer].chip_writel(val, addr); } -void chip_writen(uint8_t *buf, chipaddr addr, size_t len) +void chip_writen(const struct flashchip *flash, uint8_t *buf, chipaddr addr, size_t len) { programmer_table[programmer].chip_writen(buf, addr, len); } -uint8_t chip_readb(const chipaddr addr) +uint8_t chip_readb(const struct flashchip *flash, const chipaddr addr) { + // FIXME: Pass on flash to the programmer return programmer_table[programmer].chip_readb(addr); } -uint16_t chip_readw(const chipaddr addr) +uint16_t chip_readw(const struct flashchip *flash, const chipaddr addr) { + // FIXME: Pass on flash to the programmer return programmer_table[programmer].chip_readw(addr); } -uint32_t chip_readl(const chipaddr addr) +uint32_t chip_readl(const struct flashchip *flash, const chipaddr addr) { + // FIXME: Pass on flash to the programmer return programmer_table[programmer].chip_readl(addr); } -void chip_readn(uint8_t *buf, chipaddr addr, size_t len) +void chip_readn(const struct flashchip *flash, uint8_t *buf, chipaddr addr, size_t len) { + // FIXME: Pass on flash to the programmer programmer_table[programmer].chip_readn(buf, addr, len); } @@ -566,7 +570,7 @@ int read_memmapped(struct flashchip *flash, uint8_t *buf, int start, int len) { - chip_readn(buf, flash->virtual_memory + start, len); + chip_readn(flash, buf, flash->virtual_memory + start, len); return 0; } Index: flashrom-struct_flashchip_everywhere/programmer.h =================================================================== --- flashrom-struct_flashchip_everywhere/programmer.h (Revision 1458) +++ flashrom-struct_flashchip_everywhere/programmer.h (Arbeitskopie) @@ -558,9 +558,9 @@ enum spi_controller type; int max_data_read; int max_data_write; - int (*command)(unsigned int writecnt, unsigned int readcnt, + int (*command)(struct flashchip *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); - int (*multicommand)(struct spi_command *cmds); + int (*multicommand)(struct flashchip *flash, struct spi_command *cmds); /* Optimized functions for this programmer */ int (*read)(struct flashchip *flash, uint8_t *buf, int start, int len); @@ -568,9 +568,9 @@ }; extern const struct spi_programmer *spi_programmer; -int default_spi_send_command(unsigned int writecnt, unsigned int readcnt, +int default_spi_send_command(struct flashchip *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); -int default_spi_send_multicommand(struct spi_command *cmds); +int default_spi_send_multicommand(struct flashchip *flash, struct spi_command *cmds); int default_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); int default_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); void register_spi_programmer(const struct spi_programmer *programmer); @@ -608,10 +608,6 @@ uint8_t serprog_chip_readb(const chipaddr addr); void serprog_chip_readn(uint8_t *buf, const chipaddr addr, size_t len); void serprog_delay(int usecs); -int serprog_spi_send_command(unsigned int writecnt, unsigned int readcnt, - const unsigned char *writearr, - unsigned char *readarr); -int serprog_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); #endif /* serial.c */ Index: flashrom-struct_flashchip_everywhere/chipdrivers.h =================================================================== --- flashrom-struct_flashchip_everywhere/chipdrivers.h (Revision 1458) +++ flashrom-struct_flashchip_everywhere/chipdrivers.h (Arbeitskopie) @@ -33,8 +33,8 @@ int probe_spi_rems(struct flashchip *flash); int probe_spi_res1(struct flashchip *flash); int probe_spi_res2(struct flashchip *flash); -int spi_write_enable(void); -int spi_write_disable(void); +int spi_write_enable(struct flashchip *flash); +int spi_write_disable(struct flashchip *flash); int spi_block_erase_20(struct flashchip *flash, unsigned int addr, unsigned int blocklen); int spi_block_erase_52(struct flashchip *flash, unsigned int addr, unsigned int blocklen); int spi_block_erase_d7(struct flashchip *flash, unsigned int addr, unsigned int blocklen); @@ -44,16 +44,16 @@ int spi_chip_write_1(struct flashchip *flash, uint8_t *buf, int start, int len); int spi_chip_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); int spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len); -uint8_t spi_read_status_register(void); +uint8_t spi_read_status_register(struct flashchip *flash); int spi_write_status_register(struct flashchip *flash, int status); void spi_prettyprint_status_register_bit(uint8_t status, int bit); void spi_prettyprint_status_register_bp3210(uint8_t status, int bp); void spi_prettyprint_status_register_welwip(uint8_t status); int spi_prettyprint_status_register(struct flashchip *flash); int spi_disable_blockprotect(struct flashchip *flash); -int spi_byte_program(int addr, uint8_t databyte); -int spi_nbyte_program(int addr, uint8_t *bytes, int len); -int spi_nbyte_read(int addr, uint8_t *bytes, int len); +int spi_byte_program(struct flashchip *flash, int addr, uint8_t databyte); +int spi_nbyte_program(struct flashchip *flash, int addr, uint8_t *bytes, int len); +int spi_nbyte_read(struct flashchip *flash, int addr, uint8_t *bytes, int len); int spi_read_chunked(struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize); int spi_write_chunked(struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize); int spi_aai_write(struct flashchip *flash, uint8_t *buf, int start, int len); @@ -89,9 +89,9 @@ /* jedec.c */ uint8_t oddparity(uint8_t val); -void toggle_ready_jedec(chipaddr dst); -void data_polling_jedec(chipaddr dst, uint8_t data); -int write_byte_program_jedec(chipaddr bios, uint8_t *src, +void toggle_ready_jedec(struct flashchip *flash, chipaddr dst); +void data_polling_jedec(struct flashchip *flash, chipaddr dst, uint8_t data); +int write_byte_program_jedec(struct flashchip *flash, chipaddr bios, uint8_t *src, chipaddr dst); int probe_jedec(struct flashchip *flash); int write_jedec(struct flashchip *flash, uint8_t *buf, int start, int len); @@ -105,7 +105,7 @@ int block_erase_m29f400bt(struct flashchip *flash, unsigned int start, unsigned int len); int block_erase_chip_m29f400bt(struct flashchip *flash, unsigned int start, unsigned int len); int write_m29f400bt(struct flashchip *flash, uint8_t *buf, int start, int len); -void protect_m29f400bt(chipaddr bios); +void protect_m29f400bt(struct flashchip *flash, chipaddr bios); /* pm49fl00x.c */ int unlock_49fl00x(struct flashchip *flash); Index: flashrom-struct_flashchip_everywhere/m29f400bt.c =================================================================== --- flashrom-struct_flashchip_everywhere/m29f400bt.c (Revision 1458) +++ flashrom-struct_flashchip_everywhere/m29f400bt.c (Arbeitskopie) @@ -35,17 +35,17 @@ chipaddr dst = flash->virtual_memory + start; for (i = 0; i < len; i++) { - chip_writeb(0xAA, bios + 0xAAA); - chip_writeb(0x55, bios + 0x555); - chip_writeb(0xA0, bios + 0xAAA); + chip_writeb(flash, 0xAA, bios + 0xAAA); + chip_writeb(flash, 0x55, bios + 0x555); + chip_writeb(flash, 0xA0, bios + 0xAAA); /* transfer data from source to destination */ - chip_writeb(*src, dst); - toggle_ready_jedec(dst); + chip_writeb(flash, *src, dst); + toggle_ready_jedec(flash, dst); #if 0 /* We only want to print something in the error case. */ msg_cerr("Value in the flash at address 0x%lx = %#x, want %#x\n", - (dst - bios), chip_readb(dst), *src); + (dst - bios), chip_readb(flash, dst), *src); #endif dst++; src++; @@ -60,21 +60,21 @@ chipaddr bios = flash->virtual_memory; uint8_t id1, id2; - chip_writeb(0xAA, bios + 0xAAA); - chip_writeb(0x55, bios + 0x555); - chip_writeb(0x90, bios + 0xAAA); + chip_writeb(flash, 0xAA, bios + 0xAAA); + chip_writeb(flash, 0x55, bios + 0x555); + chip_writeb(flash, 0x90, bios + 0xAAA); programmer_delay(10); - id1 = chip_readb(bios); + id1 = chip_readb(flash, bios); /* The data sheet says id2 is at (bios + 0x01) and id2 listed in * flash.h does not match. It should be possible to use JEDEC probe. */ - id2 = chip_readb(bios + 0x02); + id2 = chip_readb(flash, bios + 0x02); - chip_writeb(0xAA, bios + 0xAAA); - chip_writeb(0x55, bios + 0x555); - chip_writeb(0xF0, bios + 0xAAA); + chip_writeb(flash, 0xAA, bios + 0xAAA); + chip_writeb(flash, 0x55, bios + 0x555); + chip_writeb(flash, 0xF0, bios + 0xAAA); programmer_delay(10); @@ -90,16 +90,16 @@ { chipaddr bios = flash->virtual_memory; - chip_writeb(0xAA, bios + 0xAAA); - chip_writeb(0x55, bios + 0x555); - chip_writeb(0x80, bios + 0xAAA); + chip_writeb(flash, 0xAA, bios + 0xAAA); + chip_writeb(flash, 0x55, bios + 0x555); + chip_writeb(flash, 0x80, bios + 0xAAA); - chip_writeb(0xAA, bios + 0xAAA); - chip_writeb(0x55, bios + 0x555); - chip_writeb(0x10, bios + 0xAAA); + chip_writeb(flash, 0xAA, bios + 0xAAA); + chip_writeb(flash, 0x55, bios + 0x555); + chip_writeb(flash, 0x10, bios + 0xAAA); programmer_delay(10); - toggle_ready_jedec(bios); + toggle_ready_jedec(flash, bios); /* FIXME: Check the status register for errors. */ return 0; @@ -110,16 +110,16 @@ chipaddr bios = flash->virtual_memory; chipaddr dst = bios + start; - chip_writeb(0xAA, bios + 0xAAA); - chip_writeb(0x55, bios + 0x555); - chip_writeb(0x80, bios + 0xAAA); + chip_writeb(flash, 0xAA, bios + 0xAAA); + chip_writeb(flash, 0x55, bios + 0x555); + chip_writeb(flash, 0x80, bios + 0xAAA); - chip_writeb(0xAA, bios + 0xAAA); - chip_writeb(0x55, bios + 0x555); - chip_writeb(0x30, dst); + chip_writeb(flash, 0xAA, bios + 0xAAA); + chip_writeb(flash, 0x55, bios + 0x555); + chip_writeb(flash, 0x30, dst); programmer_delay(10); - toggle_ready_jedec(bios); + toggle_ready_jedec(flash, bios); /* FIXME: Check the status register for errors. */ return 0; -- http://www.hailfinger.org/ From c-d.hailfinger.devel.2006 at gmx.net Thu Nov 3 23:22:02 2011 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Thu, 03 Nov 2011 23:22:02 +0100 Subject: [flashrom] SST49LF080A - ERASE FAILED at 0x000a3d28! In-Reply-To: <4EADD17D.8010906@assembler.cz> References: <4EADD17D.8010906@assembler.cz> Message-ID: <4EB3140A.2020904@gmx.net> Hi Rudolf, Am 30.10.2011 23:36 schrieb Rudolf Marek: > It worked with this chip some time ago (a year). Erasing with -E also > fails but the next one will succeed. If I write back content again and > do it all again I can reproduce this. It seems like a timing issue. > > Log attached. > > Changing probe_timing to 10000 is not helping. Tried with latest > flashrom, older ended with SIGSEGV. I expect flashrom from one year ago to show similar issues (but the error checking was worse back then, so it might not show up in all cases). > Any clue? Yes, crappy flash chip. I'll explain below the log. > Thanks > Rudolf > > flashrom v0.9.4-r1457 on Linux 3.0.3 (x86_64), built with libpci 3.1.7, GCC 4.4.5 20100728 (prerelease), little endian > flashrom is free software, get the source code at http://www.flashrom.org > > Calibrating delay loop... OS timer resolution is 1 usecs, 899M loops per second, 10 myus = 10 us, 100 myus = 100 us, 1000 myus = 1001 us, 10000 myus = 10004 us, 4 myus = 4 us, OK. > Initializing internal programmer > Found candidate at: 00000500-00000510 > Found coreboot table at 0x00000500. > Found candidate at: 00000000-00000228 > Found coreboot table at 0x00000000. > coreboot table found at 0x1fffd000. > coreboot header(24) checksum: aa66 table(552) checksum: c1b5 entries: 14 > Vendor ID: ASUS, part ID: A8V-E SE > DMI string system-manufacturer: "ASUS" > DMI string system-product-name: "A8V-E SE" > DMI string system-version: "Not Specified" > DMI string baseboard-manufacturer: "" > DMI string baseboard-product-name: "" > DMI string baseboard-version: "" > DMI string chassis-type: "Desktop" > Found chipset "VIA VT8237" with PCI ID 1106:3227. Enabling flash write... OK. > This chipset supports the following protocols: Non-SPI. > [...] > Found SST flash chip "SST49LF080A" (1024 kB, LPC). > coreboot last image size (not ROM size) is 524288 bytes. > Manufacturer: ASUS > Mainboard ID: A8V-E SE > This firmware image matches this mainboard. > Reading old flash chip contents... done. > Erasing and writing flash chip... Trying erase function 0... 0x000000-0x000fff:S, 0x001000-0x001fff:S, 0x002000-0x002fff:S, 0x003000-0x003fff:S, 0x004000-0x004fff:S, 0x005000-0x005fff:S, 0x006000-0x006fff:S, 0x007000-0x007fff:S, 0x008000-0x008fff:S, 0x009000-0x009fff:S, 0x00a000-0x00afff:S, 0x00b000-0x00bfff:S, 0x00c000-0x00cfff:S, 0x00d000-0x00dfff:S, 0x00e000-0x00efff:S, 0x00f000-0x00ffff:S, 0x010000-0x010fff:S, 0x011000-0x011fff:S, 0x012000-0x012fff:S, 0x013000-0x013fff:S, 0x014000-0x014fff:S, 0x015000-0x015fff:S, 0x016000-0x016fff:S, 0x017000-0x017fff:S, 0x018000-0x018fff:S, 0x019000-0x019fff:S, 0x01a000-0x01afff:S, 0x01b000-0x01bfff:S, 0x01c000-0x01cfff:S, 0x01d000-0x01dfff:S, 0x01e000-0x01efff:S, 0x01f000-0x01ffff:S, 0x020000-0x020fff:S, 0x021000-0x021fff:S, 0x022000-0x022fff:S, 0x023000-0x023fff:S, 0x024000-0x024fff:S, 0x025000-0x025fff:S, 0x026000-0x026fff:S, 0x027000-0x027fff:S, 0x028000-0x028fff:S, 0x029000-0x029fff:S, 0x02a000-0x02afff:S, 0x02b000-0x02bfff:S, 0x02c000-0x02cfff:S, 0x02d000-0x02dfff:S, 0x02e000-0x02efff:S, 0x02f000-0x02ffff:S, 0x030000-0x030fff:S, 0x031000-0x031fff:S, 0x032000-0x032fff:S, 0x033000-0x033fff:S, 0x034000-0x034fff:S, 0x035000-0x035fff:S, 0x036000-0x036fff:S, 0x037000-0x037fff:S, 0x038000-0x038fff:S, 0x039000-0x039fff:S, 0x03a000-0x03afff:S, 0x03b000-0x03bfff:S, 0x03c000-0x03cfff:S, 0x03d000-0x03dfff:S, 0x03e000-0x03efff:S, 0x03f000-0x03ffff:S, 0x040000-0x040fff:S, 0x041000-0x041fff:S, 0x042000-0x042fff:S, 0x043000-0x043fff:S, 0x044000-0x044fff:S, 0x045000-0x045fff:S, 0x046000-0x046fff:S, 0x047000-0x047fff:S, 0x048000-0x048fff:S, 0x049000-0x049fff:S, 0x04a000-0x04afff:S, 0x04b000-0x04bfff:S, 0x04c000-0x04cfff:S, 0x04d000-0x04dfff:S, 0x04e000-0x04efff:S, 0x04f000-0x04ffff:S, 0x050000-0x050fff:S, 0x051000-0x051fff:S, 0x052000-0x052fff:S, 0x053000-0x053fff:S, 0x054000-0x054fff:S, 0x055000-0x055fff:S, 0x056000-0x056fff:S, 0x057000-0x057fff:S, 0x058000-0x058fff:S, 0x059000-0x059fff:S, 0x05a000-0x05afff:S, 0x05b000-0x05bfff:S, 0x05c000-0x05cfff:S, 0x05d000-0x05dfff:S, 0x05e000-0x05efff:S, 0x05f000-0x05ffff:S, 0x060000-0x060fff:S, 0x061000-0x061fff:S, 0x062000-0x062fff:E, 0x063000-0x063fff:S, 0x064000-0x064fff:S, 0x065000-0x065fff:S, 0x066000-0x066fff:S, 0x067000-0x067fff:S, 0x068000-0x068fff:S, 0x069000-0x069fff:S, 0x06a000-0x06afff:S, 0x06b000-0x06bfff:E, 0x06c000-0x06cfff:S, 0x06d000-0x06dfff:S, 0x06e000-0x06efff:S, 0x06f000-0x06ffff:S, 0x070000-0x070fff:E, 0x071000-0x071fff:E, 0x072000-0x072fff:E, 0x073000-0x073fff:E, 0x074000-0x074fff:E, 0x075000-0x075fff:E, 0x076000-0x076fff:E, 0x077000-0x077fff:EERASE FAILED at 0x00077612! Expected=0xff, Read=0xdf, failed byte count from 0x00077000-0x00077fff: 0x1 > ERASE FAILED! > Reading current flash chip contents... done. Looking for another erase function. > Trying erase function 1... 0x000000-0x00ffff:S, 0x010000-0x01ffff:EW, 0x020000-0x02ffff:EW, 0x030000-0x03ffff:S, 0x040000-0x04ffff:S, 0x050000-0x05ffff:E, 0x060000-0x06ffff:S, 0x070000-0x07ffff:EW, 0x080000-0x08ffff:EW, 0x090000-0x09ffff:EW, 0x0a0000-0x0affff:EW, 0x0b0000-0x0bffff:EERASE FAILED at 0x000b2f2c! Expected=0xff, Read=0x7f, failed byte count from 0x000b0000-0x000bffff: 0x1 > ERASE FAILED! > Looking for another erase function. > No usable erase functions left. > FAILED! > Uh oh. Erase/write failed. Checking if anything changed. > Your flash chip is in an unknown state. You have two defective locations according to this log: 0x77612 and 0xb2f2c. This is a one-bit error in both cases, and automatically rerunning erase would fix it. We'd have to detect that one stuck bit in an erase operation is not a complete failure which forces the use of the next erase function, but rather something which can be fixed by rerunning the same erase command. This is fixable, but it's a bit lower on my priority list and won't happen before hwseq is merged. Regards, Carl-Daniel -- http://www.hailfinger.org/ From r.marek at assembler.cz Thu Nov 3 23:51:22 2011 From: r.marek at assembler.cz (Rudolf Marek) Date: Thu, 03 Nov 2011 23:51:22 +0100 Subject: [flashrom] Flashing FM28V100 through satasii In-Reply-To: References: Message-ID: <4EB31AEA.7040402@assembler.cz> The message is some test from the chip which is telling if some chip is connected or not. Try to override that or check the datasheet to see what it really does. Thanks Rudolf From kshepherd at scarletline.com Thu Nov 3 23:28:02 2011 From: kshepherd at scarletline.com (Kevin Shepherd) Date: Thu, 03 Nov 2011 22:28:02 +0000 Subject: [flashrom] Addition to working hardware Asus Z8PE-D12 Message-ID: <4EB31572.70607@scarletline.com> I would like to report complete success in upgrading my motherboard BIOS, and to thank the developers for their hard work. My motherboard is not yet listed in your working hardware lists. Motherboard: Asus Z8PE-D12 OS: Ubuntu 11.04 amd64 Please find attached my verbose log of the erase/write (flashrom-asus-z8pe-d12.log), as well as the three requested logs from your board testing page. Here is the command run: flashrom -V -w Z8PE-D12X-ASUS-1103.ROM - Kevin Shepherd -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: flashrom-asus-z8pe-d12.log Type: text/x-log Size: 31897 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: flashrom-V.log Type: text/x-log Size: 20533 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: lspci-nnvvxxx.log Type: text/x-log Size: 135575 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: superiotoo-deV.log Type: text/x-log Size: 5142 bytes Desc: not available URL: From stefan.tauner at student.tuwien.ac.at Fri Nov 4 00:26:25 2011 From: stefan.tauner at student.tuwien.ac.at (Stefan Tauner) Date: Fri, 4 Nov 2011 00:26:25 +0100 Subject: [flashrom] [PATCH 1/5] Add opaque programmer registration infrastructure. In-Reply-To: <4EB1C221.10900@gmx.net> References: <1319150349-24326-1-git-send-email-stefan.tauner@student.tuwien.ac.at> <1319150349-24326-2-git-send-email-stefan.tauner@student.tuwien.ac.at> <1320254997.12407.12.camel@localhost> <4EB1C221.10900@gmx.net> Message-ID: <201111032326.pA3NQ8Aa010587@mail2.student.tuwien.ac.at> On Wed, 02 Nov 2011 23:20:17 +0100 Carl-Daniel Hailfinger wrote: > >> @@ -9005,6 +9027,7 @@ const struct flashchip flashchips[] = { > >> .probe = probe_spi_rdid, > >> .write = NULL, > >> }, > >> + > >> { > >> .vendor = "Generic", > >> .name = "unknown SPI chip (REMS)", > > Unrelated change - you might have it in accidentally. > > Right. Stefan, do you plan to move this to your tested_stuff branch? done -- Kind regards/Mit freundlichen Gr??en, Stefan Tauner From stefan.tauner at student.tuwien.ac.at Fri Nov 4 00:38:34 2011 From: stefan.tauner at student.tuwien.ac.at (Stefan Tauner) Date: Fri, 4 Nov 2011 00:38:34 +0100 Subject: [flashrom] [PATCH 5/7] warn if SMM BIOS Write Protection is detected in BIOS_CNTL In-Reply-To: <20111103180747.GA1545@coreboot.org> References: <1305671512-7267-1-git-send-email-stefan.tauner@student.tuwien.ac.at> <1306192994-4006-6-git-send-email-stefan.tauner@student.tuwien.ac.at> <4DDC5848.4050000@coreboot.org> <201111031104.pA3B42DE013508@mail2.student.tuwien.ac.at> <20111103180747.GA1545@coreboot.org> Message-ID: <201111032338.pA3NcIZ8019116@mail2.student.tuwien.ac.at> On Thu, 3 Nov 2011 19:08:37 +0100 Stefan Reinauer wrote: > * Stefan Tauner [111103 12:04]: > > > > - new = old | 1; > > > > + /* > > > > + * Quote from the 6 Series datasheet: > > > > + * "5: SMM BIOS Write Protect Disable (SMM_BWP) > > > > + * 1 = BIOS region SMM protection is enabled. > > > > + * The BIOS Region is not writable unless all processors are in SMM." > > > > + * In earlier chipsets this bit is reserved. */ > > > > + if (old& (5<< 1)) { > > > > + msg_pinfo("WARNING: BIOS region SMM protection is enabled!\n"); > > > > + return -1; > > > You might still be successful doing the write, in case the SMM handler > > > does not enforce the protection, so maybe you should just print a > > > warning but not return here? > > > > in chromium-os you are trying to unset that bit[1], but according to the > > data sheet this is impossible - it is R/W LO (read/write lock once). > > Maybe there is some confusion about R/W LO. The bit can be locked, but > that does not mean it is locked automatically by writing / clearing it. > Once it is locked, the lock can not be undone except by a chipset reset. hm. quote 6 series datasheet: "R/WLO Read/Write, Lock-Once. A register bit with this attribute can be written to the non-locked value multiple times, but to the locked value only once. After the locked value has been written, the bit becomes read only." > > and you degraded the warning to dbg level... certainly not suited for > > upstream, but maybe desirable for chromium(?). > > Yes, that was done on purpose, because the lock bit that prevents the > bit from being cleared also produces a warning. and that is? BLE? i do not interpret the public datasheet like that, but... > > have you tested this on a board where SMM_BWP is really set to 1? we > > may wanna try to write it anyway, but it would be far more interesting > > if it really works on some chipsets :) > > Yes, this was implemented to fix a problem I was seeing, and it solved > the problem. :-) hm ok, we should get this upstream then. -- Kind regards/Mit freundlichen Gr??en, Stefan Tauner From flashrom at mkarcher.dialup.fu-berlin.de Fri Nov 4 22:19:43 2011 From: flashrom at mkarcher.dialup.fu-berlin.de (Michael Karcher) Date: Fri, 04 Nov 2011 22:19:43 +0100 Subject: [flashrom] [PATCH 1/5] Add opaque programmer registration infrastructure. In-Reply-To: <4EB1C221.10900@gmx.net> References: <1319150349-24326-1-git-send-email-stefan.tauner@student.tuwien.ac.at> <1319150349-24326-2-git-send-email-stefan.tauner@student.tuwien.ac.at> <1320254997.12407.12.camel@localhost> <4EB1C221.10900@gmx.net> Message-ID: <1320441583.12407.18.camel@localhost> > >> + > >> +const struct opaque_programmer *opaque_programmer = &opaque_programmer_none; > >> + > >> +int probe_opaque(struct flashchip *flash) > >> +{ > >> + if (!opaque_programmer->probe) { > >> + msg_perr("%s called, but this is not an opaque programmer. " > >> + "Please report a bug at flashrom at flashrom.org\n", > >> + __func__); > > I don't really like the error message, I would prefer "%s called without > > register_opaque" or something like that. > > What about "%s called before register_opaque_programmer" ? Good idea, go for it. > Index: flashrom-register_opaque_programmer/opaque.c > =================================================================== > --- flashrom-register_opaque_programmer/opaque.c (Revision 0) > +++ flashrom-register_opaque_programmer/opaque.c (Revision 0) [...] > +#include Huh?! What's that strange BSD compatibility header doing here? > +#include > +#include "flash.h" > +#include "flashchips.h" [...] [in flashchips.c] > @@ -9005,6 +9027,7 @@ > .probe = probe_spi_rdid, > .write = NULL, > }, > + > { > .vendor = "Generic", > .name = "unknown SPI chip (REMS)", This extra line has already be claimed by Stefan Tauner - it's not yours anymore! ;) > Signed-off-by: Carl-Daniel Hailfinger If you remove the include or provide a good reason for it, this is Acked-by: Michael Karcher Regards, Michael Karcher From svn at flashrom.org Fri Nov 4 22:35:26 2011 From: svn at flashrom.org (repository service) Date: Fri, 04 Nov 2011 22:35:26 +0100 Subject: [flashrom] [commit] r1459 - trunk Message-ID: Author: hailfinger Date: Fri Nov 4 22:35:26 2011 New Revision: 1459 URL: http://flashrom.org/trac/flashrom/changeset/1459 Log: Add opaque programmer registration infrastructure An opaque programmer does not allow direct flash access and only offers abstract probe/read/erase/write methods. Due to that, opaque programmers need their own infrastructure and registration framework. Signed-off-by: Carl-Daniel Hailfinger Acked-by: Michael Karcher Added: trunk/opaque.c Modified: trunk/Makefile trunk/chipdrivers.h trunk/flash.h trunk/flashchips.c trunk/flashchips.h trunk/print.c trunk/programmer.h Modified: trunk/Makefile ============================================================================== --- trunk/Makefile Wed Nov 2 15:31:18 2011 (r1458) +++ trunk/Makefile Fri Nov 4 22:35:26 2011 (r1459) @@ -242,7 +242,7 @@ CHIP_OBJS = jedec.o stm50flw0x0x.o w39.o w29ee011.o \ sst28sf040.o m29f400bt.o 82802ab.o pm49fl00x.o \ sst49lfxxxc.o sst_fwhub.o flashchips.o spi.o spi25.o sharplhf00l04.o \ - a25.o at25.o + a25.o at25.o opaque.o LIB_OBJS = layout.o Modified: trunk/chipdrivers.h ============================================================================== --- trunk/chipdrivers.h Wed Nov 2 15:31:18 2011 (r1458) +++ trunk/chipdrivers.h Fri Nov 4 22:35:26 2011 (r1459) @@ -58,6 +58,12 @@ int spi_write_chunked(struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize); int spi_aai_write(struct flashchip *flash, uint8_t *buf, int start, int len); +/* opaque.c */ +int probe_opaque(struct flashchip *flash); +int read_opaque(struct flashchip *flash, uint8_t *buf, int start, int len); +int write_opaque(struct flashchip *flash, uint8_t *buf, int start, int len); +int erase_opaque(struct flashchip *flash, unsigned int blockaddr, unsigned int blocklen); + /* a25.c */ int spi_prettyprint_status_register_amic_a25l05p(struct flashchip *flash); int spi_prettyprint_status_register_amic_a25l40p(struct flashchip *flash); Modified: trunk/flash.h ============================================================================== --- trunk/flash.h Wed Nov 2 15:31:18 2011 (r1458) +++ trunk/flash.h Fri Nov 4 22:35:26 2011 (r1459) @@ -62,8 +62,8 @@ BUS_LPC = 1 << 1, BUS_FWH = 1 << 2, BUS_SPI = 1 << 3, + BUS_PROG = 1 << 4, BUS_NONSPI = BUS_PARALLEL | BUS_LPC | BUS_FWH, - BUS_UNKNOWN = BUS_PARALLEL | BUS_LPC | BUS_FWH | BUS_SPI, }; /* Modified: trunk/flashchips.c ============================================================================== --- trunk/flashchips.c Wed Nov 2 15:31:18 2011 (r1458) +++ trunk/flashchips.c Fri Nov 4 22:35:26 2011 (r1459) @@ -8874,6 +8874,28 @@ }, { + .vendor = "Programmer", + .name = "Opaque flash chip", + .bustype = BUS_PROG, + .manufacture_id = PROGMANUF_ID, + .model_id = PROGDEV_ID, + .total_size = 0, + .page_size = 256, + /* probe is assumed to work, rest will be filled in by probe */ + .tested = TEST_OK_PROBE, + .probe = probe_opaque, + /* eraseblock sizes will be set by the probing function */ + .block_erasers = + { + { + .block_erase = erase_opaque, + } + }, + .write = write_opaque, + .read = read_opaque, + }, + + { .vendor = "AMIC", .name = "unknown AMIC SPI chip", .bustype = BUS_SPI, Modified: trunk/flashchips.h ============================================================================== --- trunk/flashchips.h Wed Nov 2 15:31:18 2011 (r1458) +++ trunk/flashchips.h Fri Nov 4 22:35:26 2011 (r1459) @@ -646,4 +646,7 @@ #define WINBOND_W49V002A 0xB0 #define WINBOND_W49V002FA 0x32 +#define PROGMANUF_ID 0xFFFE /* dummy ID for opaque chips behind a programmer */ +#define PROGDEV_ID 0x01 /* dummy ID for opaque chips behind a programmer */ + #endif /* !FLASHCHIPS_H */ Added: trunk/opaque.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/opaque.c Fri Nov 4 22:35:26 2011 (r1459) @@ -0,0 +1,99 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2011 Carl-Daniel Hailfinger + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * Contains the opaque programmer framework. + * An opaque programmer is a programmer which does not provide direct access + * to the flash chip and which abstracts all flash chip properties into a + * programmer specific interface. + */ + +#include +#include "flash.h" +#include "flashchips.h" +#include "chipdrivers.h" +#include "programmer.h" + +const struct opaque_programmer opaque_programmer_none = { + .max_data_read = MAX_DATA_UNSPECIFIED, + .max_data_write = MAX_DATA_UNSPECIFIED, + .probe = NULL, + .read = NULL, + .write = NULL, + .erase = NULL, +}; + +const struct opaque_programmer *opaque_programmer = &opaque_programmer_none; + +int probe_opaque(struct flashchip *flash) +{ + if (!opaque_programmer->probe) { + msg_perr("%s called before register_opaque_programmer. " + "Please report a bug at flashrom at flashrom.org\n", + __func__); + return 0; + } + + return opaque_programmer->probe(flash); +} + +int read_opaque(struct flashchip *flash, uint8_t *buf, int start, int len) +{ + if (!opaque_programmer->read) { + msg_perr("%s called before register_opaque_programmer. " + "Please report a bug at flashrom at flashrom.org\n", + __func__); + return 1; + } + return opaque_programmer->read(flash, buf, start, len); +} + +int write_opaque(struct flashchip *flash, uint8_t *buf, int start, int len) +{ + if (!opaque_programmer->write) { + msg_perr("%s called before register_opaque_programmer. " + "Please report a bug at flashrom at flashrom.org\n", + __func__); + return 1; + } + return opaque_programmer->write(flash, buf, start, len); +} + +int erase_opaque(struct flashchip *flash, unsigned int blockaddr, unsigned int blocklen) +{ + if (!opaque_programmer->erase) { + msg_perr("%s called before register_opaque_programmer. " + "Please report a bug at flashrom at flashrom.org\n", + __func__); + return 1; + } + return opaque_programmer->erase(flash, blockaddr, blocklen); +} + +void register_opaque_programmer(const struct opaque_programmer *pgm) +{ + if (!pgm->probe || !pgm->read || !pgm->write || !pgm->erase) { + msg_perr("%s called with one of probe/read/write/erase being " + "NULL. Please report a bug at flashrom at flashrom.org\n", + __func__); + return; + } + opaque_programmer = pgm; + buses_supported |= BUS_PROG; +} Modified: trunk/print.c ============================================================================== --- trunk/print.c Wed Nov 2 15:31:18 2011 (r1458) +++ trunk/print.c Fri Nov 4 22:35:26 2011 (r1459) @@ -32,13 +32,11 @@ char *flashbuses_to_text(enum chipbustype bustype) { char *ret = calloc(1, 1); - if (bustype == BUS_UNKNOWN) { - ret = strcat_realloc(ret, "Unknown, "); /* * FIXME: Once all chipsets and flash chips have been updated, NONSPI * will cease to exist and should be eliminated here as well. */ - } else if (bustype == BUS_NONSPI) { + if (bustype == BUS_NONSPI) { ret = strcat_realloc(ret, "Non-SPI, "); } else { if (bustype & BUS_PARALLEL) @@ -49,6 +47,8 @@ ret = strcat_realloc(ret, "FWH, "); if (bustype & BUS_SPI) ret = strcat_realloc(ret, "SPI, "); + if (bustype & BUS_PROG) + ret = strcat_realloc(ret, "Programmer-specific, "); if (bustype == BUS_NONE) ret = strcat_realloc(ret, "None, "); } Modified: trunk/programmer.h ============================================================================== --- trunk/programmer.h Wed Nov 2 15:31:18 2011 (r1458) +++ trunk/programmer.h Fri Nov 4 22:35:26 2011 (r1459) @@ -24,6 +24,8 @@ #ifndef __PROGRAMMER_H__ #define __PROGRAMMER_H__ 1 +#include "flash.h" /* for chipaddr and flashchip */ + enum programmer { #if CONFIG_INTERNAL == 1 PROGRAMMER_INTERNAL, @@ -601,6 +603,19 @@ int wbsio_check_for_spi(void); #endif +/* opaque.c */ +struct opaque_programmer { + int max_data_read; + int max_data_write; + /* Specific functions for this programmer */ + int (*probe) (struct flashchip *flash); + int (*read) (struct flashchip *flash, uint8_t *buf, int start, int len); + int (*write) (struct flashchip *flash, uint8_t *buf, int start, int len); + int (*erase) (struct flashchip *flash, unsigned int blockaddr, unsigned int blocklen); +}; +extern const struct opaque_programmer *opaque_programmer; +void register_opaque_programmer(const struct opaque_programmer *pgm); + /* serprog.c */ #if CONFIG_SERPROG == 1 int serprog_init(void); From c-d.hailfinger.devel.2006 at gmx.net Fri Nov 4 22:37:30 2011 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Fri, 04 Nov 2011 22:37:30 +0100 Subject: [flashrom] [PATCH 1/5] Add opaque programmer registration infrastructure. In-Reply-To: <1320441583.12407.18.camel@localhost> References: <1319150349-24326-1-git-send-email-stefan.tauner@student.tuwien.ac.at> <1319150349-24326-2-git-send-email-stefan.tauner@student.tuwien.ac.at> <1320254997.12407.12.camel@localhost> <4EB1C221.10900@gmx.net> <1320441583.12407.18.camel@localhost> Message-ID: <4EB45B1A.9000608@gmx.net> Am 04.11.2011 22:19 schrieb Michael Karcher: > This extra line has already be claimed by Stefan Tauner - it's not yours > anymore! ;) Killed. >> Signed-off-by: Carl-Daniel Hailfinger > If you remove the include or provide a good reason for it, this is Killed. > Acked-by: Michael Karcher Thanks, committed in r1459. Regards, Carl-Daniel -- http://www.hailfinger.org/ From yarpr at pochta.ru Sat Nov 5 07:09:03 2011 From: yarpr at pochta.ru (yarpr at pochta.ru) Date: Sat, 05 Nov 2011 10:09:03 +0400 Subject: [flashrom] (no subject) Message-ID: <1e62f44c197d4810a55df63bda6ea34e558f3ecd@mail.qip.ru> ­­­­­ _ Pr.om_ot.ions on wee­­­­­­k­­e_nds ­ -------------- next part -------------- An HTML attachment was scrubbed... URL: From c-d.hailfinger.devel.2006 at gmx.net Sat Nov 5 10:50:08 2011 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Sat, 05 Nov 2011 10:50:08 +0100 Subject: [flashrom] (no subject) In-Reply-To: <1e62f44c197d4810a55df63bda6ea34e558f3ecd@mail.qip.ru> References: <1e62f44c197d4810a55df63bda6ea34e558f3ecd@mail.qip.ru> Message-ID: <4EB506D0.4080507@gmx.net> On 05.11.2011 07:09, yarpr at pochta.ru wrote: > [SPAM] Sorry, the sender was whitelisted due to an earlier flashrom report. I've removed the whitelisting for now. Regards, Carl-Daniel From c-d.hailfinger.devel.2006 at gmx.net Sun Nov 6 23:56:42 2011 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Sun, 06 Nov 2011 23:56:42 +0100 Subject: [flashrom] [PATCH] ichspi: use a variable to distinguish ich generations instead of spi_programmer->type In-Reply-To: <1320281901-15465-1-git-send-email-stefan.tauner@student.tuwien.ac.at> References: <4EB0A071.8020506@gmx.net> <1320281901-15465-1-git-send-email-stefan.tauner@student.tuwien.ac.at> Message-ID: <4EB710AA.7000201@gmx.net> Am 03.11.2011 01:58 schrieb Stefan Tauner: > The type member is enough most of the time to derive the wanted > information, but > - not always (e.g. ich_set_bbar), > - only available after registration, which we want to delay till the > end of init, and > - we really want to distinguish between chipset version-grained > attributes which are not reflected by the registered programmer. > > Hence this patch introduces a new static variable which is set up > early by the init functions and allows us to get rid of all "switch > (spi_programmer->type)" in ichspi.c. We reuse the enum introduced > for descriptor mode for the type of the new variable. > > Previously magic numbers were passed by chipset_enable wrappers. Now > they use the enumeration items too. To get this working the enum > definition had to be moved to programmer.h, which was fixed on the > way by adding necessary includes. > > Another noteworthy detail: previously we have checked for a valid > programmer/ich generation all over the place. I have removed those > checks and added one single check in the init method. Calling any > function of a programmer without executing the init method first, is > undefined behavior. > > Signed-off-by: Stefan Tauner Excellent. > On Wed, 02 Nov 2011 02:44:17 +0100 > Carl-Daniel Hailfinger wrote: > >>> i think it might be a good idea to get rid of the whole >>> switch(spi_programmer->type) >>> pattern and create a file-scope static ich_generation variable instead >>> of using the type member and the ich_generation parameters everywhere. >> Absolutely agreed. >> The only possible generic problem with that approach would be the >> registration of multiple ICH-style SPI programmers, but unless we see >> boards with two active ICH-style southbridges I think we can assume the >> static variable handles it well. (Note that boards with multiple MCP55 >> southbridges exist, but only one southbridge has an attached flash chip.) > and even then they would have to be from different incompatible generations... > i think we are quite safe ;) > >> There might be an issue for those who want to use flashrom as a >> standalone tool (e.g. on top of libpayload) where heap allocations for >> static variables are unwanted, but that's a huge can of worms and I'd >> rather ignore that issue until either static variables work well in that >> environment or until someone hacks a way around static variables being a >> problem there. >> >>> the type member is enough most of the time to derive the wanted >>> information, but >>> - not always (e.g. ich_set_bbar) >>> - only available after registration, which we want to delay till the end >>> of init. >>> - we really want to distinguish between chipset version-grained >>> attributes which are not reflected by the registered programmer. >> Indeed. So if you could rework the patch to use your static variable >> suggestion, it would reduce patch size and make the code more readable. > you may want to evaluate that "patch size" argument again... *sigh* Heh. > i have added the first applicable chipset to each default case for > documentation purposes. Good idea. Please go ahead. Acked-by: Carl-Daniel Hailfinger Regards, Carl-Daniel -- http://www.hailfinger.org/ From c-d.hailfinger.devel.2006 at gmx.net Mon Nov 7 00:15:53 2011 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Mon, 07 Nov 2011 00:15:53 +0100 Subject: [flashrom] [PATCH 2/2] ichspi: add support for Intel Hardware Sequencing In-Reply-To: <1319636118-15878-3-git-send-email-stefan.tauner@student.tuwien.ac.at> References: <1319636118-15878-1-git-send-email-stefan.tauner@student.tuwien.ac.at> <1319636118-15878-3-git-send-email-stefan.tauner@student.tuwien.ac.at> Message-ID: <4EB71529.1020005@gmx.net> Am 26.10.2011 15:35 schrieb Stefan Tauner: > Based on the new opaque programmer framework this patch adds support > for Intel Hardware Sequencing on ICH8 and its successors. > > By default (or when setting the ich_spi_mode option to auto) > the module tries to use swseq and only activates hwseq if need be: > - if important opcodes are inaccessible due to lockdown > - if more than one flash chip is attached. > The other options (swseq, hwseq) select the respective mode (if possible). > > A general description of Hardware Sequencing can be found in this blog entry: > http://blogs.coreboot.org/blog/2011/06/11/gsoc-2011-flashrom-part-1/ > > TODO: adding real documentation when we have a directory for it > > Signed-off-by: Stefan Tauner Acked-by: Carl-Daniel Hailfinger with a few small comments. > --- > flashrom.8 | 20 +++++ > ichspi.c | 268 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++- > 2 files changed, 283 insertions(+), 5 deletions(-) > > diff --git a/flashrom.8 b/flashrom.8 > index a8f4660..66cde4f 100644 > --- a/flashrom.8 > +++ b/flashrom.8 > @@ -303,6 +303,26 @@ is the I/O port number (must be a multiple of 8). In the unlikely case > flashrom doesn't detect an active IT87 LPC<->SPI bridge, please send a bug > report so we can diagnose the problem. > .sp > +If you have an Intel chipset with an ICH8 or later southbridge with SPI flash > +attached, and if a valid descriptor was written to it (e.g. by the vendor), the > +chipset provides an alternative way to access the flash chip(s) named > +.BR "Hardware Sequencing" . > +It is much simpler than the normal access method (called > +.BR "Software Sequencing" ")," > +but does not allow the software to choose the SPI commands to be sent. > +You can use the > +.sp > +.B " flashrom \-p internal:ich_spi_mode=value" > +.sp > +syntax where value can be > +.BR auto ", " swseq " or " hwseq . > +By default > +.RB "(or when setting " ich_spi_mode=auto ) > +the module tries to use swseq and only activates hwseq if need be (e.g. if > +important opcodes are inaccessible due to lockdown; or if more than one flash > +chip is attached). The other options (swseq, hwseq) select the respective mode > +(if possible). > +.sp > If you have an Intel chipset with an ICH6 or later southbridge and if you want > to set specific IDSEL values for a non-default flash chip or an embedded > controller (EC), you can use the > diff --git a/ichspi.c b/ichspi.c > index bc03554..1d5dd34 100644 > --- a/ichspi.c > +++ b/ichspi.c > @@ -575,6 +575,25 @@ static int program_opcodes(int ich_generation, OPCODES *op, int enable_undo) > return 0; > } > > +/* Returns true if the most important opcodes are accessible. */ You assume that some erase opcode will be available if BYTE_PROGRAM is available. I think that assumption is reasonable, but it could be documented in this comment above the function. > +static int ich_check_opcodes() > +{ > + uint8_t ops[] = { > + JEDEC_READ, > + JEDEC_BYTE_PROGRAM, > + JEDEC_RDSR, > + 0 > + }; > + int i = 0; > + while (ops[i] != 0) { > + msg_pspew("checking for opcode 0x%02x\n", ops[i]); > + if (find_opcode(curopcodes, ops[i]) == -1) > + return 0; > + i++; > + } > + return 1; > +} > + > /* > * Try to set BBAR (BIOS Base Address Register), but read back the value in case > * it didn't stick. > @@ -1325,6 +1525,14 @@ static const struct spi_programmer spi_programmer_ich9 = { > .write_256 = default_spi_write_256, > }; > > +static const struct opaque_programmer opaque_programmer_ich_hwseq = { > + .max_data_read = 64, > + .max_data_write = 64, > + .probe = ich_hwseq_probe, > + .read = ich_hwseq_read, > + .write = ich_hwseq_write, Please add ich_hwseq_block_erase here. > +}; > + > int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, > int ich_generation) > { > @@ -1332,7 +1540,14 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, > uint8_t old, new; > uint16_t spibar_offset, tmp2; > uint32_t tmp; > + char *arg; > int desc_valid = 0; > + struct ich_descriptors desc = {{ 0 }}; > + enum ich_spi_mode { > + ich_auto, > + ich_hwseq, > + ich_swseq > + } ich_spi_mode = ich_auto; > > switch (ich_generation) { > case 7: > @@ -1399,6 +1614,22 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, > case 9: > case 10: > default: /* Future version might behave the same */ > + arg = extract_programmer_param("ich_spi_mode"); > + if (arg && !strcmp(arg, "hwseq")) { > + ich_spi_mode = ich_hwseq; > + msg_pspew("user selected hwseq\n"); > + } else if (arg && !strcmp(arg, "swseq")) { > + ich_spi_mode = ich_swseq; > + msg_pspew("user selected swseq\n"); > + } else if (arg && !strcmp(arg, "auto")) { > + msg_pspew("user selected auto\n"); > + ich_spi_mode = ich_auto; > + } else if (arg && !strlen(arg)) > + msg_pinfo("Missing argument for ich_spi_mode.\n"); > + else if (arg) > + msg_pinfo("Unknown argument for ich_spi_mode: %s\n", arg); We should return an error all the way up to programmer init for both cases (and clean up everything). I know that this is a complicated code path, so if you decide not to fail programmer init here, please add a comment like the one below: /* FIXME: Return an error to programmer_init. */ > + free(arg); > + > tmp2 = mmio_readw(ich_spibar + ICH9_REG_HSFS); > msg_pdbg("0x04: 0x%04x (HSFS)\n", tmp2); > prettyprint_ich9_reg_hsfs(tmp2); > @@ -1484,14 +1715,41 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, > > msg_pdbg("\n"); > if (desc_valid) { > - struct ich_descriptors desc = {{ 0 }}; > if (read_ich_descriptors_via_fdo(ich_spibar, &desc) == > ICH_RET_OK) > prettyprint_ich_descriptors(CHIPSET_ICH_UNKNOWN, > &desc); > + /* If the descriptor is valid and indicates multiple > + * flash devices we need to use hwseq to be able to > + * access the second flash device. > + */ > + if (ich_spi_mode == ich_auto && desc.content.NC != 0) { > + msg_pinfo("Enabling hardware sequencing due to " > + "multiple flash chips detected.\n"); > + ich_spi_mode = ich_hwseq; > + } > + } > + > + if (ich_spi_mode == ich_auto && ichspi_lock && > + !ich_check_opcodes()) { > + msg_pinfo("Enabling hardware sequencing because " > + "some important opcodes are locked.\n"); > + ich_spi_mode = ich_hwseq; > + } > + > + if (ich_spi_mode == ich_hwseq) { > + if (!desc_valid) { > + msg_perr("Hardware sequencing was requested " > + "but the flash descriptor is not " > + "valid. Aborting.\n"); > + return 1; Can you check that this indeed causes flashrom to return an error from programmer_init? Chipset init IIRC ignores most errors unless they are somehow declared to be fatal. > + } > + hwseq_data.size_comp0 = getFCBA_component_density(&desc, 0); > + hwseq_data.size_comp1 = getFCBA_component_density(&desc, 1); > + register_opaque_programmer(&opaque_programmer_ich_hwseq); > + } else { > + register_spi_programmer(&spi_programmer_ich9); > } > - register_spi_programmer(&spi_programmer_ich9); > - ich_init_opcodes(); > break; > } > Regards, Carl-Daniel -- http://www.hailfinger.org/ From svn at flashrom.org Mon Nov 7 00:51:09 2011 From: svn at flashrom.org (repository service) Date: Mon, 07 Nov 2011 00:51:09 +0100 Subject: [flashrom] [commit] r1460 - trunk Message-ID: Author: stefanct Date: Mon Nov 7 00:51:09 2011 New Revision: 1460 URL: http://flashrom.org/trac/flashrom/changeset/1460 Log: ichspi: use a variable to distinguish ich generations instead of spi_programmer->type The type member is enough most of the time to derive the wanted information, but - not always (e.g. ich_set_bbar), - only available after registration, which we want to delay till the end of init, and - we really want to distinguish between chipset version-grained attributes which are not reflected by the registered programmer. Hence this patch introduces a new static variable which is set up early by the init functions and allows us to get rid of all "switch (spi_programmer->type)" in ichspi.c. We reuse the enum introduced for descriptor mode for the type of the new variable. Previously magic numbers were passed by chipset_enable wrappers. Now they use the enumeration items too. To get this working the enum definition had to be moved to programmer.h. Another noteworthy detail: previously we have checked for a valid programmer/ich generation all over the place. I have removed those checks and added one single check in the init method. Calling any function of a programmer without executing the init method first, is undefined behavior. Signed-off-by: Stefan Tauner Acked-by: Carl-Daniel Hailfinger Modified: trunk/chipset_enable.c trunk/ich_descriptors.h trunk/ichspi.c trunk/programmer.h Modified: trunk/chipset_enable.c ============================================================================== --- trunk/chipset_enable.c Fri Nov 4 22:35:26 2011 (r1459) +++ trunk/chipset_enable.c Mon Nov 7 00:51:09 2011 (r1460) @@ -489,7 +489,7 @@ } static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name, - int ich_generation) + enum ich_chipset ich_generation) { int ret; uint8_t bbs, buc; @@ -504,7 +504,7 @@ static const char *const straps_names_unknown[] = { "unknown", "unknown", "unknown", "unknown" }; switch (ich_generation) { - case 7: + case CHIPSET_ICH7: /* EP80579 may need further changes, but this is the least * intrusive way to get correct BOOT Strap printing without * changing the rest of its code path). */ @@ -513,13 +513,13 @@ else straps_names = straps_names_ich7_nm10; break; - case 8: - case 9: - case 10: + case CHIPSET_ICH8: + case CHIPSET_ICH9: + case CHIPSET_ICH10: straps_names = straps_names_ich8910; break; - case 11: - case 12: + case CHIPSET_5_SERIES_IBEX_PEAK: + case CHIPSET_6_SERIES_COUGAR_POINT: straps_names = straps_names_pch56; break; default: @@ -557,7 +557,7 @@ * on ICH7 when the southbridge is strapped to LPC */ buses_supported = BUS_FWH; - if (ich_generation == 7) { + if (ich_generation == CHIPSET_ICH7) { if (bbs == 0x03) { /* If strapped to LPC, no further SPI initialization is * required. */ @@ -579,34 +579,34 @@ static int enable_flash_ich7(struct pci_dev *dev, const char *name) { - return enable_flash_ich_dc_spi(dev, name, 7); + return enable_flash_ich_dc_spi(dev, name, CHIPSET_ICH7); } static int enable_flash_ich8(struct pci_dev *dev, const char *name) { - return enable_flash_ich_dc_spi(dev, name, 8); + return enable_flash_ich_dc_spi(dev, name, CHIPSET_ICH8); } static int enable_flash_ich9(struct pci_dev *dev, const char *name) { - return enable_flash_ich_dc_spi(dev, name, 9); + return enable_flash_ich_dc_spi(dev, name, CHIPSET_ICH9); } static int enable_flash_ich10(struct pci_dev *dev, const char *name) { - return enable_flash_ich_dc_spi(dev, name, 10); + return enable_flash_ich_dc_spi(dev, name, CHIPSET_ICH10); } /* Ibex Peak aka. 5 series & 3400 series */ static int enable_flash_pch5(struct pci_dev *dev, const char *name) { - return enable_flash_ich_dc_spi(dev, name, 11); + return enable_flash_ich_dc_spi(dev, name, CHIPSET_5_SERIES_IBEX_PEAK); } /* Cougar Point aka. 6 series & c200 series */ static int enable_flash_pch6(struct pci_dev *dev, const char *name) { - return enable_flash_ich_dc_spi(dev, name, 12); + return enable_flash_ich_dc_spi(dev, name, CHIPSET_6_SERIES_COUGAR_POINT); } static int via_no_byte_merge(struct pci_dev *dev, const char *name) Modified: trunk/ich_descriptors.h ============================================================================== --- trunk/ich_descriptors.h Fri Nov 4 22:35:26 2011 (r1459) +++ trunk/ich_descriptors.h Mon Nov 7 00:51:09 2011 (r1460) @@ -24,6 +24,7 @@ #define __ICH_DESCRIPTORS_H__ 1 #include +#include "programmer.h" /* for enum ich_chipset */ /* FIXME: Replace with generic return codes */ #define ICH_RET_OK 0 @@ -63,20 +64,6 @@ #define ICH_FREG_BASE(flreg) (((flreg) << 12) & 0x01fff000) #define ICH_FREG_LIMIT(flreg) (((flreg) >> 4) & 0x01fff000) -/* Used to select the right descriptor printing function. - * Currently only ICH8 and Ibex Peak are supported. - */ -enum ich_chipset { - CHIPSET_ICH_UNKNOWN, - CHIPSET_ICH7 = 7, - CHIPSET_ICH8, - CHIPSET_ICH9, - CHIPSET_ICH10, - CHIPSET_5_SERIES_IBEX_PEAK, - CHIPSET_6_SERIES_COUGAR_POINT, - CHIPSET_7_SERIES_PANTHER_POINT -}; - void prettyprint_ich_reg_vscc(uint32_t reg_val, int verbosity); struct ich_desc_content { Modified: trunk/ichspi.c ============================================================================== --- trunk/ichspi.c Fri Nov 4 22:35:26 2011 (r1459) +++ trunk/ichspi.c Mon Nov 7 00:51:09 2011 (r1460) @@ -172,6 +172,7 @@ /* ICH SPI configuration lock-down. May be set during chipset enabling. */ static int ichspi_lock = 0; +static enum ich_chipset ich_generation = CHIPSET_ICH_UNKNOWN; uint32_t ichspi_bbar = 0; static void *ich_spibar = NULL; @@ -454,23 +455,20 @@ return -1; } - switch (spi_programmer->type) { - case SPI_CONTROLLER_ICH7: - case SPI_CONTROLLER_VIA: + switch (ich_generation) { + case CHIPSET_ICH7: preop = REGREAD16(ICH7_REG_PREOP); optype = REGREAD16(ICH7_REG_OPTYPE); opmenu[0] = REGREAD32(ICH7_REG_OPMENU); opmenu[1] = REGREAD32(ICH7_REG_OPMENU + 4); break; - case SPI_CONTROLLER_ICH9: + case CHIPSET_ICH8: + default: /* Future version might behave the same */ preop = REGREAD16(ICH9_REG_PREOP); optype = REGREAD16(ICH9_REG_OPTYPE); opmenu[0] = REGREAD32(ICH9_REG_OPMENU); opmenu[1] = REGREAD32(ICH9_REG_OPMENU + 4); break; - default: - msg_perr("%s: unsupported chipset\n", __func__); - return -1; } op->preop[0] = (uint8_t) preop; @@ -529,9 +527,8 @@ } msg_pdbg("\n%s: preop=%04x optype=%04x opmenu=%08x%08x\n", __func__, preop, optype, opmenu[0], opmenu[1]); - switch (spi_programmer->type) { - case SPI_CONTROLLER_ICH7: - case SPI_CONTROLLER_VIA: + switch (ich_generation) { + case CHIPSET_ICH7: /* Register undo only for enable_undo=1, i.e. first call. */ if (enable_undo) { rmmio_valw(ich_spibar + ICH7_REG_PREOP); @@ -544,7 +541,8 @@ mmio_writel(opmenu[0], ich_spibar + ICH7_REG_OPMENU); mmio_writel(opmenu[1], ich_spibar + ICH7_REG_OPMENU + 4); break; - case SPI_CONTROLLER_ICH9: + case CHIPSET_ICH8: + default: /* Future version might behave the same */ /* Register undo only for enable_undo=1, i.e. first call. */ if (enable_undo) { rmmio_valw(ich_spibar + ICH9_REG_PREOP); @@ -557,9 +555,6 @@ mmio_writel(opmenu[0], ich_spibar + ICH9_REG_OPMENU); mmio_writel(opmenu[1], ich_spibar + ICH9_REG_OPMENU + 4); break; - default: - msg_perr("%s: unsupported chipset\n", __func__); - return -1; } return 0; @@ -569,16 +564,17 @@ * Try to set BBAR (BIOS Base Address Register), but read back the value in case * it didn't stick. */ -static void ich_set_bbar(int ich_generation, uint32_t min_addr) +static void ich_set_bbar(uint32_t min_addr) { int bbar_off; switch (ich_generation) { - case 7: + case CHIPSET_ICH7: bbar_off = 0x50; break; - case 8: + case CHIPSET_ICH8: msg_perr("BBAR offset is unknown on ICH8!\n"); return; + case CHIPSET_ICH9: default: /* Future version might behave the same */ bbar_off = ICH9_REG_BBAR; break; @@ -943,15 +939,12 @@ return SPI_INVALID_LENGTH; } - switch (spi_programmer->type) { - case SPI_CONTROLLER_VIA: - case SPI_CONTROLLER_ICH7: + switch (ich_generation) { + case CHIPSET_ICH7: return ich7_run_opcode(op, offset, datalength, data, maxlength); - case SPI_CONTROLLER_ICH9: + case CHIPSET_ICH8: + default: /* Future version might behave the same */ return ich9_run_opcode(op, offset, datalength, data); - default: - /* If we ever get here, something really weird happened */ - return -1; } } @@ -1022,19 +1015,11 @@ opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) { addr = (writearr[1] << 16) | (writearr[2] << 8) | (writearr[3] << 0); - switch (spi_programmer->type) { - case SPI_CONTROLLER_ICH7: - case SPI_CONTROLLER_VIA: - case SPI_CONTROLLER_ICH9: - if (addr < ichspi_bbar) { - msg_perr("%s: Address 0x%06x below allowed " - "range 0x%06x-0xffffff\n", __func__, - addr, ichspi_bbar); - return SPI_INVALID_ADDRESS; - } - break; - default: - break; + if (addr < ichspi_bbar) { + msg_perr("%s: Address 0x%06x below allowed " + "range 0x%06x-0xffffff\n", __func__, + addr, ichspi_bbar); + return SPI_INVALID_ADDRESS; } } @@ -1316,7 +1301,7 @@ }; int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, - int ich_generation) + enum ich_chipset ich_gen) { int i; uint8_t old, new; @@ -1324,15 +1309,16 @@ uint32_t tmp; int desc_valid = 0; + ich_generation = ich_gen; + switch (ich_generation) { - case 7: - spibar_offset = 0x3020; - break; - case 8: + case CHIPSET_ICH_UNKNOWN: + return -1; + case CHIPSET_ICH7: + case CHIPSET_ICH8: spibar_offset = 0x3020; break; - case 9: - case 10: + case CHIPSET_ICH9: default: /* Future version might behave the same */ spibar_offset = 0x3800; break; @@ -1345,7 +1331,7 @@ ich_spibar = rcrb + spibar_offset; switch (ich_generation) { - case 7: + case CHIPSET_ICH7: msg_pdbg("0x00: 0x%04x (SPIS)\n", mmio_readw(ich_spibar + 0)); msg_pdbg("0x02: 0x%04x (SPIC)\n", @@ -1381,13 +1367,11 @@ msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); ichspi_lock = 1; } - ich_set_bbar(ich_generation, 0); + ich_set_bbar(0); register_spi_programmer(&spi_programmer_ich7); ich_init_opcodes(); break; - case 8: - case 9: - case 10: + case CHIPSET_ICH8: default: /* Future version might behave the same */ tmp2 = mmio_readw(ich_spibar + ICH9_REG_HSFS); msg_pdbg("0x04: 0x%04x (HSFS)\n", tmp2); @@ -1447,7 +1431,7 @@ mmio_readl(ich_spibar + ICH9_REG_OPMENU)); msg_pdbg("0x9C: 0x%08x (OPMENU+4)\n", mmio_readl(ich_spibar + ICH9_REG_OPMENU + 4)); - if (ich_generation == 8) { + if (ich_generation == CHIPSET_ICH8) { tmp = mmio_readl(ich_spibar + ICH8_REG_VSCC); msg_pdbg("0xC1: 0x%08x (VSCC)\n", tmp); msg_pdbg("VSCC: "); @@ -1469,7 +1453,7 @@ tmp = mmio_readl(ich_spibar + ICH9_REG_FPB); msg_pdbg("0xD0: 0x%08x (FPB)\n", tmp); - ich_set_bbar(ich_generation, 0); + ich_set_bbar(0); } msg_pdbg("\n"); @@ -1524,6 +1508,7 @@ /* Not sure if it speaks all these bus protocols. */ buses_supported = BUS_LPC | BUS_FWH; + ich_generation = CHIPSET_ICH7; register_spi_programmer(&spi_programmer_via); msg_pdbg("0x00: 0x%04x (SPIS)\n", mmio_readw(ich_spibar + 0)); @@ -1556,7 +1541,7 @@ ichspi_lock = 1; } - ich_set_bbar(7, 0); + ich_set_bbar(0); ich_init_opcodes(); return 0; Modified: trunk/programmer.h ============================================================================== --- trunk/programmer.h Fri Nov 4 22:35:26 2011 (r1459) +++ trunk/programmer.h Mon Nov 7 00:51:09 2011 (r1460) @@ -579,9 +579,20 @@ /* ichspi.c */ #if CONFIG_INTERNAL == 1 +enum ich_chipset { + CHIPSET_ICH_UNKNOWN, + CHIPSET_ICH7 = 7, + CHIPSET_ICH8, + CHIPSET_ICH9, + CHIPSET_ICH10, + CHIPSET_5_SERIES_IBEX_PEAK, + CHIPSET_6_SERIES_COUGAR_POINT, + CHIPSET_7_SERIES_PANTHER_POINT +}; + extern uint32_t ichspi_bbar; int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, - int ich_generation); + enum ich_chipset ich_generation); int via_init_spi(struct pci_dev *dev); /* it85spi.c */ From stefan.tauner at student.tuwien.ac.at Mon Nov 7 00:55:07 2011 From: stefan.tauner at student.tuwien.ac.at (Stefan Tauner) Date: Mon, 7 Nov 2011 00:55:07 +0100 Subject: [flashrom] [PATCH] ichspi: use a variable to distinguish ich generations instead of spi_programmer->type In-Reply-To: <4EB710AA.7000201@gmx.net> References: <4EB0A071.8020506@gmx.net> <1320281901-15465-1-git-send-email-stefan.tauner@student.tuwien.ac.at> <4EB710AA.7000201@gmx.net> Message-ID: <201111062354.pA6NspmN015318@mail2.student.tuwien.ac.at> On Sun, 06 Nov 2011 23:56:42 +0100 Carl-Daniel Hailfinger wrote: > Acked-by: Carl-Daniel Hailfinger thanks! committed with minimal changes in r1460. as michael has pointed out on IRC i missed to convert ich_init_spi's argument "ich_gen" from int to enum ich_chipset. also, i forgot to convert a magic number. hopefully i got it right now. adding hwseq |########################-| ;) -- Kind regards/Mit freundlichen Gr??en, Stefan Tauner From c-d.hailfinger.devel.2006 at gmx.net Mon Nov 7 14:47:42 2011 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Mon, 07 Nov 2011 14:47:42 +0100 Subject: [flashrom] [PATCH] Register Parallel/LPC/FWH programmers In-Reply-To: <4E6A5322.8070003@gmx.net> References: <4DEDCE84.8020400@gmx.net> <4E6808CE.7010906@gmx.net> <201109082137.p88Lb3DF014751@mail2.student.tuwien.ac.at> <4E6A5322.8070003@gmx.net> Message-ID: <4EB7E17E.6070001@gmx.net> Am 09.09.2011 19:55 schrieb Carl-Daniel Hailfinger: > Am 08.09.2011 23:36 schrieb Stefan Tauner: >> On Thu, 08 Sep 2011 02:14:06 +0200 >> Carl-Daniel Hailfinger wrote: >> >>> RFC/TODO: >>> - Should register_par_programmer(...) be called before or after setting >>> max_rom_decode.*? >> why is that not a field in the different programmer structs (yet?)? > Given that the registration for parallel and SPI programmers is pretty > different but max_rom_decode.* is used from common code, it is not > immediately obvious to handle this sanely. Supply it as > register_par_programmer() parameter and extend register_spi_programmer > to accept that parameter as well? I'm now setting max_rom_decode before calling register_par_programmer. Given that such restrictions may exist for any programmer, I'll postpone handling max_rom_decode to the universal programmer registration patch where we get the infrastructure to deal with such programmer limitations. If you have any objections, please tell me. >>> - Should register_par_programmer(...) be called before or after >>> register_shutdown()? >>> >> like register_spi_programmer (no idea when that is, but consistency is >> the one main argument i can think of atm) >> > They should be called after register_shutdown, otherwise there is a time > when chip access functions are callable although the programmer has > already been shut down. Will audit the code and change where appropriate. Done. >>> - Is there a better name for register_par_programmer? >>> >> register_parallel_programmer ofc, and imho it is not too long, because >> it is seldom used, but i don't care that much (due to the same reason). >> > 80 column limit... I think that was one of the reasons we used a shorter > name. > >>> - Should max_rom_decode.* be part of the registration? >>> >> either that or declaration, see question above. if it has to be >> modified (board enables do this it seems...), this can't be done at >> registration (only)... >> > Same trick as buses_supported. Have a local static (not part of the > official interface) chipset_max_rom_decode variable which can be > modified by chipset/mainboard init, and then use the end result in > registration. max_rom_decode is conceptually different from buses_supported although that was not obvious when I wrote the paragraph above. It will be handled in the universal programmer registration patch. >>> - Should map_flash_region/unmap_flash_region be part of the registration? >>> >> no idea what that does exactly :P >> > It makes the flash chip accessible. This is essentially physmap for > programmers with memory mapped flash and a no-op for everything else. And moving it into the parallel programmer struct may not have been the best idea. Sure, that gets it out of the way conveniently, but once the universal programmer registration patch is in, we will not have any dummy parallel programmer struct for such fallbacks anymore. This will cause all sorts of design headaches which are not obvious right now. New version. Testing on all programmers is very appreciated. Register Parallel/LPC/FWH programmers the same way SPI programmers are registered. Additional fixes: Set max_rom_decode.parallel for drkaiser. Remove abuse of programmer_map_flash_region in it85spi. Annotate several FIXMEs in it85spi. Note: Programmers without parallel/LPC/FWH chip support should not call register_par_programmer(). I did not check for 80 column limit violations, but the rest should be OK. We need something like this patch to handle programmers with multiple flash chips (e.g. LPC/FWH chips mapped to different regions on mainboards). Signed-off-by: Carl-Daniel Hailfinger Index: flashrom-register_par_programmer/drkaiser.c =================================================================== --- flashrom-register_par_programmer/drkaiser.c (Revision 1460) +++ flashrom-register_par_programmer/drkaiser.c (Arbeitskopie) @@ -39,6 +39,17 @@ static uint8_t *drkaiser_bar; +static const struct par_programmer par_programmer_drkaiser = { + .chip_readb = drkaiser_chip_readb, + .chip_readw = fallback_chip_readw, + .chip_readl = fallback_chip_readl, + .chip_readn = fallback_chip_readn, + .chip_writeb = drkaiser_chip_writeb, + .chip_writew = fallback_chip_writew, + .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, +}; + static int drkaiser_shutdown(void *data) { physunmap(drkaiser_bar, DRKAISER_MEMMAP_SIZE); @@ -64,10 +75,12 @@ drkaiser_bar = physmap("Dr. Kaiser PC-Waechter flash memory", addr, DRKAISER_MEMMAP_SIZE); - buses_supported = BUS_PARALLEL; - if (register_shutdown(drkaiser_shutdown, NULL)) return 1; + + max_rom_decode.parallel = 131072; + register_par_programmer(&par_programmer_drkaiser, BUS_PARALLEL); + return 0; } Index: flashrom-register_par_programmer/it87spi.c =================================================================== --- flashrom-register_par_programmer/it87spi.c (Revision 1460) +++ flashrom-register_par_programmer/it87spi.c (Arbeitskopie) @@ -192,7 +192,7 @@ free(portpos); exit_conf_mode_ite(port); it8716f_flashport = flashport; - if (buses_supported & BUS_SPI) + if (internal_buses_supported & BUS_SPI) msg_pdbg("Overriding chipset SPI with IT87 SPI.\n"); /* FIXME: Add the SPI bus or replace the other buses with it? */ register_spi_programmer(&spi_programmer_it87xx); Index: flashrom-register_par_programmer/gfxnvidia.c =================================================================== --- flashrom-register_par_programmer/gfxnvidia.c (Revision 1460) +++ flashrom-register_par_programmer/gfxnvidia.c (Arbeitskopie) @@ -61,6 +61,17 @@ {}, }; +static const struct par_programmer par_programmer_gfxnvidia = { + .chip_readb = gfxnvidia_chip_readb, + .chip_readw = fallback_chip_readw, + .chip_readl = fallback_chip_readl, + .chip_readn = fallback_chip_readn, + .chip_writeb = gfxnvidia_chip_writeb, + .chip_writew = fallback_chip_writew, + .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, +}; + static int gfxnvidia_shutdown(void *data) { physunmap(nvidia_bar, GFXNVIDIA_MEMMAP_SIZE); @@ -94,10 +105,9 @@ reg32 &= ~(1 << 0); rpci_write_long(pcidev_dev, 0x50, reg32); - buses_supported = BUS_PARALLEL; - /* Write/erase doesn't work. */ programmer_may_write = 0; + register_par_programmer(&par_programmer_gfxnvidia, BUS_PARALLEL); return 0; } Index: flashrom-register_par_programmer/nicrealtek.c =================================================================== --- flashrom-register_par_programmer/nicrealtek.c (Revision 1460) +++ flashrom-register_par_programmer/nicrealtek.c (Arbeitskopie) @@ -36,6 +36,17 @@ {}, }; +static const struct par_programmer par_programmer_nicrealtek = { + .chip_readb = nicrealtek_chip_readb, + .chip_readw = fallback_chip_readw, + .chip_readl = fallback_chip_readl, + .chip_readn = fallback_chip_readn, + .chip_writeb = nicrealtek_chip_writeb, + .chip_writew = fallback_chip_writew, + .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, +}; + static int nicrealtek_shutdown(void *data) { /* FIXME: We forgot to disable software access again. */ @@ -50,10 +61,11 @@ io_base_addr = pcidev_init(PCI_BASE_ADDRESS_0, nics_realtek); - buses_supported = BUS_PARALLEL; - if (register_shutdown(nicrealtek_shutdown, NULL)) return 1; + + register_par_programmer(&par_programmer_nicrealtek, BUS_PARALLEL); + return 0; } Index: flashrom-register_par_programmer/serprog.c =================================================================== --- flashrom-register_par_programmer/serprog.c (Revision 1460) +++ flashrom-register_par_programmer/serprog.c (Arbeitskopie) @@ -299,6 +299,11 @@ return 0; } +static int serprog_spi_send_command(unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr, + unsigned char *readarr); +static int serprog_spi_read(struct flashchip *flash, uint8_t *buf, int start, + int len); static struct spi_programmer spi_programmer_serprog = { .type = SPI_CONTROLLER_SERPROG, .max_data_read = MAX_DATA_READ_UNLIMITED, @@ -309,6 +314,19 @@ .write_256 = default_spi_write_256, }; +static const struct par_programmer par_programmer_serprog = { + .chip_readb = serprog_chip_readb, + .chip_readw = fallback_chip_readw, + .chip_readl = fallback_chip_readl, + .chip_readn = serprog_chip_readn, + .chip_writeb = serprog_chip_writeb, + .chip_writew = fallback_chip_writew, + .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, +}; + +static enum chipbustype serprog_buses_supported = BUS_NONE; + int serprog_init(void) { uint16_t iface; @@ -400,41 +418,45 @@ if (sp_docommand(S_CMD_Q_IFACE, 0, NULL, 2, &iface)) { msg_perr("Error: NAK to query interface version\n"); - exit(1); + return 1; } if (iface != 1) { msg_perr("Error: Unknown interface version: %d\n", iface); - exit(1); + return 1; } msg_pdbg(MSGHEADER "Interface version ok.\n"); if (sp_docommand(S_CMD_Q_CMDMAP, 0, NULL, 32, sp_cmdmap)) { msg_perr("Error: query command map not supported\n"); - exit(1); + return 1; } sp_check_avail_automatic = 1; - + /* FIXME: This assumes that serprog device bustypes are always + * identical with flashrom bustype enums and that they all fit + * in a single byte. + */ if (sp_docommand(S_CMD_Q_BUSTYPE, 0, NULL, 1, &c)) { msg_perr("Warning: NAK to query supported buses\n"); c = BUS_NONSPI; /* A reasonable default for now. */ } - buses_supported = c; + serprog_buses_supported = c; + msg_pdbg(MSGHEADER "Bus support: parallel=%s, LPC=%s, FWH=%s, SPI=%s\n", (c & BUS_PARALLEL) ? "on" : "off", (c & BUS_LPC) ? "on" : "off", (c & BUS_FWH) ? "on" : "off", (c & BUS_SPI) ? "on" : "off"); /* Check for the minimum operational set of commands. */ - if (buses_supported & BUS_SPI) { + if (serprog_buses_supported & BUS_SPI) { uint8_t bt = BUS_SPI; if (sp_check_commandavail(S_CMD_O_SPIOP) == 0) { msg_perr("Error: SPI operation not supported while the " "bustype is SPI\n"); - exit(1); + return 1; } /* Success of any of these commands is optional. We don't need the programmer to tell us its limits, but if it doesn't, we @@ -461,40 +483,39 @@ spi_programmer_serprog.max_data_read = v; msg_pdbg(MSGHEADER "Maximum read-n length is %d\n", v); } - bt = buses_supported; + bt = serprog_buses_supported; sp_docommand(S_CMD_S_BUSTYPE, 1, &bt, 0, NULL); - register_spi_programmer(&spi_programmer_serprog); } - if (buses_supported & BUS_NONSPI) { + if (serprog_buses_supported & BUS_NONSPI) { if (sp_check_commandavail(S_CMD_O_INIT) == 0) { msg_perr("Error: Initialize operation buffer " "not supported\n"); - exit(1); + return 1; } if (sp_check_commandavail(S_CMD_O_DELAY) == 0) { msg_perr("Error: Write to opbuf: " "delay not supported\n"); - exit(1); + return 1; } /* S_CMD_O_EXEC availability checked later. */ if (sp_check_commandavail(S_CMD_R_BYTE) == 0) { msg_perr("Error: Single byte read not supported\n"); - exit(1); + return 1; } /* This could be translated to single byte reads (if missing), * but now we don't support that. */ if (sp_check_commandavail(S_CMD_R_NBYTES) == 0) { msg_perr("Error: Read n bytes not supported\n"); - exit(1); + return 1; } if (sp_check_commandavail(S_CMD_O_WRITEB) == 0) { msg_perr("Error: Write to opbuf: " "write byte not supported\n"); - exit(1); + return 1; } if (sp_docommand(S_CMD_Q_WRNMAXLEN, 0, NULL, 3, rbuf)) { @@ -513,7 +534,7 @@ if (!sp_write_n_buf) { msg_perr("Error: cannot allocate memory for " "Write-n buffer\n"); - exit(1); + return 1; } sp_write_n_bytes = 0; } @@ -551,12 +572,12 @@ if (sp_check_commandavail(S_CMD_O_EXEC) == 0) { msg_perr("Error: Execute operation buffer not " "supported\n"); - exit(1); + return 1; } if (sp_docommand(S_CMD_O_INIT, 0, NULL, 0, NULL)) { msg_perr("Error: NAK to initialize operation buffer\n"); - exit(1); + return 1; } if (sp_docommand(S_CMD_Q_OPBUF, 0, NULL, 2, @@ -572,6 +593,11 @@ sp_streamed_transmit_ops = 0; sp_streamed_transmit_bytes = 0; sp_opbuf_usage = 0; + if (serprog_buses_supported & BUS_SPI) + register_spi_programmer(&spi_programmer_serprog); + if (serprog_buses_supported & BUS_NONSPI) + register_par_programmer(&par_programmer_serprog, + serprog_buses_supported & BUS_NONSPI); return 0; } @@ -766,7 +792,7 @@ sp_prev_was_write = 0; } -int serprog_spi_send_command(unsigned int writecnt, unsigned int readcnt, +static int serprog_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { @@ -796,7 +822,7 @@ * the advantage that it is much faster for most chips, but breaks those with * non-contiguous address space (like AT45DB161D). When spi_read_chunked is * fixed this method can be removed. */ -int serprog_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) +static int serprog_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) { int i; int cur_len; Index: flashrom-register_par_programmer/satamv.c =================================================================== --- flashrom-register_par_programmer/satamv.c (Revision 1460) +++ flashrom-register_par_programmer/satamv.c (Arbeitskopie) @@ -41,6 +41,17 @@ #define PCI_BAR2_CONTROL 0x00c08 #define GPIO_PORT_CONTROL 0x104f0 +static const struct par_programmer par_programmer_satamv = { + .chip_readb = satamv_chip_readb, + .chip_readw = fallback_chip_readw, + .chip_readl = fallback_chip_readl, + .chip_readn = fallback_chip_readn, + .chip_writeb = satamv_chip_writeb, + .chip_writew = fallback_chip_writew, + .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, +}; + static int satamv_shutdown(void *data) { physunmap(mv_bar, 0x20000); @@ -137,11 +148,10 @@ mv_iobar = tmp & 0xffff; msg_pspew("Activating I/O BAR at 0x%04x\n", mv_iobar); - buses_supported = BUS_PARALLEL; - /* 512 kByte with two 8-bit latches, and * 4 MByte with additional 3-bit latch. */ max_rom_decode.parallel = 4 * 1024 * 1024; + register_par_programmer(&par_programmer_satamv, BUS_PARALLEL); return 0; Index: flashrom-register_par_programmer/dummyflasher.c =================================================================== --- flashrom-register_par_programmer/dummyflasher.c (Revision 1460) +++ flashrom-register_par_programmer/dummyflasher.c (Arbeitskopie) @@ -75,6 +75,19 @@ .write_256 = dummy_spi_write_256, }; +static const struct par_programmer par_programmer_dummy = { + .chip_readb = dummy_chip_readb, + .chip_readw = dummy_chip_readw, + .chip_readl = dummy_chip_readl, + .chip_readn = dummy_chip_readn, + .chip_writeb = dummy_chip_writeb, + .chip_writew = dummy_chip_writew, + .chip_writel = dummy_chip_writel, + .chip_writen = dummy_chip_writen, +}; + +enum chipbustype dummy_buses_supported = BUS_NONE; + static int dummy_shutdown(void *data) { msg_pspew("%s\n", __func__); @@ -108,24 +121,24 @@ /* Convert the parameters to lowercase. */ tolower_string(bustext); - buses_supported = BUS_NONE; + dummy_buses_supported = BUS_NONE; if (strstr(bustext, "parallel")) { - buses_supported |= BUS_PARALLEL; + dummy_buses_supported |= BUS_PARALLEL; msg_pdbg("Enabling support for %s flash.\n", "parallel"); } if (strstr(bustext, "lpc")) { - buses_supported |= BUS_LPC; + dummy_buses_supported |= BUS_LPC; msg_pdbg("Enabling support for %s flash.\n", "LPC"); } if (strstr(bustext, "fwh")) { - buses_supported |= BUS_FWH; + dummy_buses_supported |= BUS_FWH; msg_pdbg("Enabling support for %s flash.\n", "FWH"); } if (strstr(bustext, "spi")) { - register_spi_programmer(&spi_programmer_dummyflasher); + dummy_buses_supported |= BUS_SPI; msg_pdbg("Enabling support for %s flash.\n", "SPI"); } - if (buses_supported == BUS_NONE) + if (dummy_buses_supported == BUS_NONE) msg_pdbg("Support for all flash bus types disabled.\n"); free(bustext); @@ -226,6 +239,14 @@ free(flashchip_contents); return 1; } + if (dummy_buses_supported & (BUS_PARALLEL | BUS_LPC | BUS_FWH)) + register_par_programmer(&par_programmer_dummy, + dummy_buses_supported & + (BUS_PARALLEL | BUS_LPC | + BUS_FWH)); + if (dummy_buses_supported & BUS_SPI) + register_spi_programmer(&spi_programmer_dummyflasher); + return 0; } Index: flashrom-register_par_programmer/cli_classic.c =================================================================== --- flashrom-register_par_programmer/cli_classic.c (Revision 1460) +++ flashrom-register_par_programmer/cli_classic.c (Arbeitskopie) @@ -443,6 +443,10 @@ ret = 1; goto out_shutdown; } + tempstr = flashbuses_to_text(buses_supported); + msg_pdbg("This programmer supports the following protocols: %s.\n", + tempstr); + free(tempstr); for (i = 0; i < ARRAY_SIZE(flashes); i++) { startchip = probe_flash(startchip, &flashes[i], 0); Index: flashrom-register_par_programmer/internal.c =================================================================== --- flashrom-register_par_programmer/internal.c (Revision 1460) +++ flashrom-register_par_programmer/internal.c (Arbeitskopie) @@ -127,6 +127,19 @@ int is_laptop = 0; int laptop_ok = 0; +static const struct par_programmer par_programmer_internal = { + .chip_readb = internal_chip_readb, + .chip_readw = internal_chip_readw, + .chip_readl = internal_chip_readl, + .chip_readn = internal_chip_readn, + .chip_writeb = internal_chip_writeb, + .chip_writew = internal_chip_writew, + .chip_writel = internal_chip_writel, + .chip_writen = fallback_chip_writen, +}; + +enum chipbustype internal_buses_supported = BUS_NONE; + static int internal_shutdown(void *data) { release_io_perms(); @@ -191,9 +204,10 @@ return 1; /* Default to Parallel/LPC/FWH flash devices. If a known host controller - * is found, the init routine sets the buses_supported bitfield. + * is found, the host controller init routine sets the + * internal_buses_supported bitfield. */ - buses_supported = BUS_NONSPI; + internal_buses_supported = BUS_NONSPI; /* Initialize PCI access for flash enables */ pacc = pci_alloc(); /* Get the pci_access structure */ @@ -287,6 +301,7 @@ * Besides that, we don't check the board enable return code either. */ #if defined(__i386__) || defined(__x86_64__) || defined (__mips) + register_par_programmer(&par_programmer_internal, internal_buses_supported); return 0; #else msg_perr("Your platform is not supported yet for the internal " Index: flashrom-register_par_programmer/ichspi.c =================================================================== --- flashrom-register_par_programmer/ichspi.c (Revision 1460) +++ flashrom-register_par_programmer/ichspi.c (Arbeitskopie) @@ -1507,7 +1507,7 @@ ich_spibar = physmap("VT8237S MMIO registers", mmio_base, 0x70); /* Not sure if it speaks all these bus protocols. */ - buses_supported = BUS_LPC | BUS_FWH; + internal_buses_supported = BUS_LPC | BUS_FWH; ich_generation = CHIPSET_ICH7; register_spi_programmer(&spi_programmer_via); Index: flashrom-register_par_programmer/nicnatsemi.c =================================================================== --- flashrom-register_par_programmer/nicnatsemi.c (Revision 1460) +++ flashrom-register_par_programmer/nicnatsemi.c (Arbeitskopie) @@ -35,6 +35,17 @@ {}, }; +static const struct par_programmer par_programmer_nicnatsemi = { + .chip_readb = nicnatsemi_chip_readb, + .chip_readw = fallback_chip_readw, + .chip_readl = fallback_chip_readl, + .chip_readn = fallback_chip_readn, + .chip_writeb = nicnatsemi_chip_writeb, + .chip_writew = fallback_chip_writew, + .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, +}; + static int nicnatsemi_shutdown(void *data) { pci_cleanup(pacc); @@ -48,7 +59,8 @@ io_base_addr = pcidev_init(PCI_BASE_ADDRESS_0, nics_natsemi); - buses_supported = BUS_PARALLEL; + if (register_shutdown(nicnatsemi_shutdown, NULL)) + return 1; /* The datasheet shows address lines MA0-MA16 in one place and MA0-MA15 * in another. My NIC has MA16 connected to A16 on the boot ROM socket @@ -57,9 +69,8 @@ * functions below wants to be 0x0000FFFF. */ max_rom_decode.parallel = 131072; + register_par_programmer(&par_programmer_nicnatsemi, BUS_PARALLEL); - if (register_shutdown(nicnatsemi_shutdown, NULL)) - return 1; return 0; } Index: flashrom-register_par_programmer/it85spi.c =================================================================== --- flashrom-register_par_programmer/it85spi.c (Revision 1460) +++ flashrom-register_par_programmer/it85spi.c (Arbeitskopie) @@ -257,8 +257,10 @@ INDIRECT_A3(shm_io_base, (base >> 24)); #endif #ifdef LPC_MEMORY - base = (chipaddr)programmer_map_flash_region("it85 communication", - 0xFFFFF000, 0x1000); + /* FIXME: We should block accessing that region for anything else. + * Major TODO here, and it will be a lot of work. + */ + base = (chipaddr)physmap("it85 communication", 0xFFFFF000, 0x1000); msg_pdbg("%s():%d base=0x%08x\n", __func__, __LINE__, (unsigned int)base); ce_high = (unsigned char *)(base + 0xE00); /* 0xFFFFFE00 */ @@ -285,18 +287,26 @@ { int ret; - if (!(buses_supported & BUS_FWH)) { + if (!(internal_buses_supported & BUS_FWH)) { msg_pdbg("%s():%d buses not support FWH\n", __func__, __LINE__); return 1; } ret = it85xx_spi_common_init(s); msg_pdbg("FWH: %s():%d ret=%d\n", __func__, __LINE__, ret); if (!ret) { - msg_pdbg("%s():%d buses_supported=0x%x\n", __func__, __LINE__, - buses_supported); - if (buses_supported & BUS_FWH) - msg_pdbg("Overriding chipset SPI with IT85 FWH|SPI.\n"); - /* Really leave FWH enabled? */ + msg_pdbg("%s: internal_buses_supported=0x%x\n", __func__, + internal_buses_supported); + /* Check for FWH because IT85 listens to FWH cycles. + * FIXME: The big question is whether FWH cycles are necessary + * for communication even if LPC_IO is defined. + */ + if (internal_buses_supported & BUS_FWH) + msg_pdbg("Registering IT85 SPI.\n"); + /* FIXME: Really leave FWH enabled? We can't use this region + * anymore since accessing it would mess up IT85 communication. + * If we decide to disable FWH for this region, we should print + * a debug message about it. + */ /* Set this as SPI controller. */ register_spi_programmer(&spi_programmer_it85xx); } Index: flashrom-register_par_programmer/atahpt.c =================================================================== --- flashrom-register_par_programmer/atahpt.c (Revision 1460) +++ flashrom-register_par_programmer/atahpt.c (Arbeitskopie) @@ -40,6 +40,17 @@ {}, }; +static const struct par_programmer par_programmer_atahpt = { + .chip_readb = atahpt_chip_readb, + .chip_readw = fallback_chip_readw, + .chip_readl = fallback_chip_readl, + .chip_readn = fallback_chip_readn, + .chip_writeb = atahpt_chip_writeb, + .chip_writew = fallback_chip_writew, + .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, +}; + static int atahpt_shutdown(void *data) { /* Flash access is disabled automatically by PCI restore. */ @@ -61,10 +72,11 @@ reg32 |= (1 << 24); rpci_write_long(pcidev_dev, REG_FLASH_ACCESS, reg32); - buses_supported = BUS_PARALLEL; - if (register_shutdown(atahpt_shutdown, NULL)) return 1; + + register_par_programmer(&par_programmer_atahpt, BUS_PARALLEL); + return 0; } Index: flashrom-register_par_programmer/nic3com.c =================================================================== --- flashrom-register_par_programmer/nic3com.c (Revision 1460) +++ flashrom-register_par_programmer/nic3com.c (Arbeitskopie) @@ -55,6 +55,17 @@ {}, }; +static const struct par_programmer par_programmer_nic3com = { + .chip_readb = nic3com_chip_readb, + .chip_readw = fallback_chip_readw, + .chip_readl = fallback_chip_readl, + .chip_readn = fallback_chip_readn, + .chip_writeb = nic3com_chip_writeb, + .chip_writew = fallback_chip_writew, + .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, +}; + static int nic3com_shutdown(void *data) { /* 3COM 3C90xB cards need a special fixup. */ @@ -96,11 +107,12 @@ */ OUTW(SELECT_REG_WINDOW + 0, io_base_addr + INT_STATUS); - buses_supported = BUS_PARALLEL; + if (register_shutdown(nic3com_shutdown, NULL)) + return 1; + max_rom_decode.parallel = 128 * 1024; + register_par_programmer(&par_programmer_nic3com, BUS_PARALLEL); - if (register_shutdown(nic3com_shutdown, NULL)) - return 1; return 0; } Index: flashrom-register_par_programmer/satasii.c =================================================================== --- flashrom-register_par_programmer/satasii.c (Revision 1460) +++ flashrom-register_par_programmer/satasii.c (Arbeitskopie) @@ -42,6 +42,17 @@ {}, }; +static const struct par_programmer par_programmer_satasii = { + .chip_readb = satasii_chip_readb, + .chip_readw = fallback_chip_readw, + .chip_readl = fallback_chip_readl, + .chip_readn = fallback_chip_readn, + .chip_writeb = satasii_chip_writeb, + .chip_writew = fallback_chip_writew, + .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, +}; + static int satasii_shutdown(void *data) { physunmap(sii_bar, SATASII_MEMMAP_SIZE); @@ -76,10 +87,11 @@ if ((id != 0x0680) && (!(pci_mmio_readl(sii_bar) & (1 << 26)))) msg_pinfo("Warning: Flash seems unconnected.\n"); - buses_supported = BUS_PARALLEL; - if (register_shutdown(satasii_shutdown, NULL)) return 1; + + register_par_programmer(&par_programmer_satasii, BUS_PARALLEL); + return 0; } Index: flashrom-register_par_programmer/wbsio_spi.c =================================================================== --- flashrom-register_par_programmer/wbsio_spi.c (Revision 1460) +++ flashrom-register_par_programmer/wbsio_spi.c (Arbeitskopie) @@ -82,10 +82,10 @@ msg_pspew("\nwbsio_spibase = 0x%x\n", wbsio_spibase); - register_spi_programmer(&spi_programmer_wbsio); msg_pdbg("%s: Winbond saved on 4 register bits so max chip size is " "1024 kB!\n", __func__); max_rom_decode.spi = 1024 * 1024; + register_spi_programmer(&spi_programmer_wbsio); return 0; } Index: flashrom-register_par_programmer/nicintel.c =================================================================== --- flashrom-register_par_programmer/nicintel.c (Revision 1460) +++ flashrom-register_par_programmer/nicintel.c (Arbeitskopie) @@ -43,6 +43,17 @@ #define CSR_FCR 0x0c +static const struct par_programmer par_programmer_nicintel = { + .chip_readb = nicintel_chip_readb, + .chip_readw = fallback_chip_readw, + .chip_readl = fallback_chip_readl, + .chip_readn = fallback_chip_readn, + .chip_writeb = nicintel_chip_writeb, + .chip_writew = fallback_chip_writew, + .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, +}; + static int nicintel_shutdown(void *data) { physunmap(nicintel_control_bar, NICINTEL_CONTROL_MEMMAP_SIZE); @@ -93,9 +104,8 @@ */ pci_rmmio_writew(0x0001, nicintel_control_bar + CSR_FCR); - buses_supported = BUS_PARALLEL; - max_rom_decode.parallel = NICINTEL_MEMMAP_SIZE; + register_par_programmer(&par_programmer_nicintel, BUS_PARALLEL); return 0; Index: flashrom-register_par_programmer/chipset_enable.c =================================================================== --- flashrom-register_par_programmer/chipset_enable.c (Revision 1460) +++ flashrom-register_par_programmer/chipset_enable.c (Arbeitskopie) @@ -213,7 +213,7 @@ uint16_t old, new; uint16_t xbcs = 0x4e; /* X-Bus Chip Select register. */ - buses_supported = BUS_PARALLEL; + internal_buses_supported = BUS_PARALLEL; old = pci_read_word(dev, xbcs); @@ -303,7 +303,7 @@ * FWH_DEC_EN1, but they are called FB_SEL1, FB_SEL2, FB_DEC_EN1 and * FB_DEC_EN2. */ - buses_supported = BUS_FWH; + internal_buses_supported = BUS_FWH; return enable_flash_ich(dev, name, 0x4e); } @@ -412,9 +412,9 @@ msg_pdbg("\nMaximum FWH chip size: 0x%x bytes", max_rom_decode.fwh); /* If we're called by enable_flash_ich_dc_spi, it will override - * buses_supported anyway. + * internal_buses_supported anyway. */ - buses_supported = BUS_FWH; + internal_buses_supported = BUS_FWH; return enable_flash_ich(dev, name, 0xdc); } @@ -434,7 +434,7 @@ if (new != old) rpci_write_byte(dev, 0xd9, new); - buses_supported = BUS_FWH; + internal_buses_supported = BUS_FWH; return 0; } @@ -468,12 +468,11 @@ bnt = mmio_readl(rcrb + 0x3410); if (bnt & 0x02) { /* If strapped to LPC, no SPI initialization is required */ - buses_supported = BUS_FWH; + internal_buses_supported = BUS_FWH; return 0; } /* This adds BUS_SPI */ - buses_supported = BUS_SPI; if (ich_init_spi(dev, tmp, rcrb, 7) != 0) { if (!ret) ret = ERROR_NONFATAL; @@ -556,7 +555,7 @@ * time. At least not with our current code. So we prevent searching * on ICH7 when the southbridge is strapped to LPC */ - buses_supported = BUS_FWH; + internal_buses_supported = BUS_FWH; if (ich_generation == CHIPSET_ICH7) { if (bbs == 0x03) { /* If strapped to LPC, no further SPI initialization is @@ -564,7 +563,7 @@ return ret; } else { /* Disable LPC/FWH if strapped to PCI or SPI */ - buses_supported = 0; + internal_buses_supported = BUS_NONE; } } @@ -667,7 +666,7 @@ #define CS5530_ENABLE_SA2320 (1 << 2) #define CS5530_ENABLE_SA20 (1 << 6) - buses_supported = BUS_PARALLEL; + internal_buses_supported = BUS_PARALLEL; /* Decode 0x000E0000-0x000FFFFF (128 kB), not just 64 kB, and * decode 0xFF000000-0xFFFFFFFF (16 MB), not just 256 kB. * FIXME: Should we really touch the low mapping below 1 MB? Flashrom @@ -820,7 +819,7 @@ (prot & 0xfffff800) + (((prot & 0x7fc) << 8) | 0x3ff)); } - buses_supported = BUS_LPC | BUS_FWH; + internal_buses_supported = BUS_LPC | BUS_FWH; ret = sb600_probe_spi(dev); @@ -914,7 +913,7 @@ { uint8_t tmp; - buses_supported = BUS_PARALLEL; + internal_buses_supported = BUS_PARALLEL; tmp = INB(0xc06); tmp |= 0x1; @@ -1014,7 +1013,7 @@ switch ((val >> 5) & 0x3) { case 0x0: ret = enable_flash_mcp55(dev, name); - buses_supported = BUS_LPC; + internal_buses_supported = BUS_LPC; msg_pdbg("Flash bus type is LPC\n"); break; case 0x2: @@ -1022,7 +1021,7 @@ /* SPI is added in mcp6x_spi_init if it works. * Do we really want to disable LPC in this case? */ - buses_supported = BUS_NONE; + internal_buses_supported = BUS_NONE; msg_pdbg("Flash bus type is SPI\n"); msg_pinfo("SPI on this chipset is WIP. Please report any " "success or failure by mailing us the verbose " @@ -1030,7 +1029,7 @@ break; default: /* Should not happen. */ - buses_supported = BUS_NONE; + internal_buses_supported = BUS_NONE; msg_pdbg("Flash bus type is unknown (none)\n"); msg_pinfo("Something went wrong with bus type detection.\n"); goto out_msg; @@ -1323,7 +1322,6 @@ struct pci_dev *dev = NULL; int ret = -2; /* Nothing! */ int i; - char *s; /* Now let's try to find the chipset we have... */ for (i = 0; chipset_enables[i].vendor_name != NULL; i++) { @@ -1375,9 +1373,5 @@ } } - s = flashbuses_to_text(buses_supported); - msg_pinfo("This chipset supports the following protocols: %s.\n", s); - free(s); - return ret; } Index: flashrom-register_par_programmer/programmer.c =================================================================== --- flashrom-register_par_programmer/programmer.c (Revision 1460) +++ flashrom-register_par_programmer/programmer.c (Arbeitskopie) @@ -19,7 +19,21 @@ */ #include "flash.h" +#include "programmer.h" +static const struct par_programmer par_programmer_none = { + .chip_readb = noop_chip_readb, + .chip_readw = fallback_chip_readw, + .chip_readl = fallback_chip_readl, + .chip_readn = fallback_chip_readn, + .chip_writeb = noop_chip_writeb, + .chip_writew = fallback_chip_writew, + .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, +}; + +const struct par_programmer *par_programmer = &par_programmer_none; + /* No-op shutdown() for programmers which don't need special handling */ int noop_shutdown(void) { @@ -96,3 +110,9 @@ buf[i] = chip_readb(addr + i); return; } + +void register_par_programmer(const struct par_programmer *pgm, const enum chipbustype buses) +{ + par_programmer = pgm; + buses_supported |= buses; +} Index: flashrom-register_par_programmer/flashrom.c =================================================================== --- flashrom-register_par_programmer/flashrom.c (Revision 1460) +++ flashrom-register_par_programmer/flashrom.c (Arbeitskopie) @@ -68,14 +68,6 @@ .init = internal_init, .map_flash_region = physmap, .unmap_flash_region = physunmap, - .chip_readb = internal_chip_readb, - .chip_readw = internal_chip_readw, - .chip_readl = internal_chip_readl, - .chip_readn = internal_chip_readn, - .chip_writeb = internal_chip_writeb, - .chip_writew = internal_chip_writew, - .chip_writel = internal_chip_writel, - .chip_writen = fallback_chip_writen, .delay = internal_delay, }, #endif @@ -86,14 +78,6 @@ .init = dummy_init, .map_flash_region = dummy_map, .unmap_flash_region = dummy_unmap, - .chip_readb = dummy_chip_readb, - .chip_readw = dummy_chip_readw, - .chip_readl = dummy_chip_readl, - .chip_readn = dummy_chip_readn, - .chip_writeb = dummy_chip_writeb, - .chip_writew = dummy_chip_writew, - .chip_writel = dummy_chip_writel, - .chip_writen = dummy_chip_writen, .delay = internal_delay, }, #endif @@ -104,14 +88,6 @@ .init = nic3com_init, .map_flash_region = fallback_map, .unmap_flash_region = fallback_unmap, - .chip_readb = nic3com_chip_readb, - .chip_readw = fallback_chip_readw, - .chip_readl = fallback_chip_readl, - .chip_readn = fallback_chip_readn, - .chip_writeb = nic3com_chip_writeb, - .chip_writew = fallback_chip_writew, - .chip_writel = fallback_chip_writel, - .chip_writen = fallback_chip_writen, .delay = internal_delay, }, #endif @@ -124,14 +100,6 @@ .init = nicrealtek_init, .map_flash_region = fallback_map, .unmap_flash_region = fallback_unmap, - .chip_readb = nicrealtek_chip_readb, - .chip_readw = fallback_chip_readw, - .chip_readl = fallback_chip_readl, - .chip_readn = fallback_chip_readn, - .chip_writeb = nicrealtek_chip_writeb, - .chip_writew = fallback_chip_writew, - .chip_writel = fallback_chip_writel, - .chip_writen = fallback_chip_writen, .delay = internal_delay, }, #endif @@ -142,14 +110,6 @@ .init = nicnatsemi_init, .map_flash_region = fallback_map, .unmap_flash_region = fallback_unmap, - .chip_readb = nicnatsemi_chip_readb, - .chip_readw = fallback_chip_readw, - .chip_readl = fallback_chip_readl, - .chip_readn = fallback_chip_readn, - .chip_writeb = nicnatsemi_chip_writeb, - .chip_writew = fallback_chip_writew, - .chip_writel = fallback_chip_writel, - .chip_writen = fallback_chip_writen, .delay = internal_delay, }, #endif @@ -160,14 +120,6 @@ .init = gfxnvidia_init, .map_flash_region = fallback_map, .unmap_flash_region = fallback_unmap, - .chip_readb = gfxnvidia_chip_readb, - .chip_readw = fallback_chip_readw, - .chip_readl = fallback_chip_readl, - .chip_readn = fallback_chip_readn, - .chip_writeb = gfxnvidia_chip_writeb, - .chip_writew = fallback_chip_writew, - .chip_writel = fallback_chip_writel, - .chip_writen = fallback_chip_writen, .delay = internal_delay, }, #endif @@ -178,14 +130,6 @@ .init = drkaiser_init, .map_flash_region = fallback_map, .unmap_flash_region = fallback_unmap, - .chip_readb = drkaiser_chip_readb, - .chip_readw = fallback_chip_readw, - .chip_readl = fallback_chip_readl, - .chip_readn = fallback_chip_readn, - .chip_writeb = drkaiser_chip_writeb, - .chip_writew = fallback_chip_writew, - .chip_writel = fallback_chip_writel, - .chip_writen = fallback_chip_writen, .delay = internal_delay, }, #endif @@ -196,14 +140,6 @@ .init = satasii_init, .map_flash_region = fallback_map, .unmap_flash_region = fallback_unmap, - .chip_readb = satasii_chip_readb, - .chip_readw = fallback_chip_readw, - .chip_readl = fallback_chip_readl, - .chip_readn = fallback_chip_readn, - .chip_writeb = satasii_chip_writeb, - .chip_writew = fallback_chip_writew, - .chip_writel = fallback_chip_writel, - .chip_writen = fallback_chip_writen, .delay = internal_delay, }, #endif @@ -214,14 +150,6 @@ .init = atahpt_init, .map_flash_region = fallback_map, .unmap_flash_region = fallback_unmap, - .chip_readb = atahpt_chip_readb, - .chip_readw = fallback_chip_readw, - .chip_readl = fallback_chip_readl, - .chip_readn = fallback_chip_readn, - .chip_writeb = atahpt_chip_writeb, - .chip_writew = fallback_chip_writew, - .chip_writel = fallback_chip_writel, - .chip_writen = fallback_chip_writen, .delay = internal_delay, }, #endif @@ -232,14 +160,6 @@ .init = ft2232_spi_init, .map_flash_region = fallback_map, .unmap_flash_region = fallback_unmap, - .chip_readb = noop_chip_readb, - .chip_readw = fallback_chip_readw, - .chip_readl = fallback_chip_readl, - .chip_readn = fallback_chip_readn, - .chip_writeb = noop_chip_writeb, - .chip_writew = fallback_chip_writew, - .chip_writel = fallback_chip_writel, - .chip_writen = fallback_chip_writen, .delay = internal_delay, }, #endif @@ -250,14 +170,6 @@ .init = serprog_init, .map_flash_region = fallback_map, .unmap_flash_region = fallback_unmap, - .chip_readb = serprog_chip_readb, - .chip_readw = fallback_chip_readw, - .chip_readl = fallback_chip_readl, - .chip_readn = serprog_chip_readn, - .chip_writeb = serprog_chip_writeb, - .chip_writew = fallback_chip_writew, - .chip_writel = fallback_chip_writel, - .chip_writen = fallback_chip_writen, .delay = serprog_delay, }, #endif @@ -268,14 +180,6 @@ .init = buspirate_spi_init, .map_flash_region = fallback_map, .unmap_flash_region = fallback_unmap, - .chip_readb = noop_chip_readb, - .chip_readw = fallback_chip_readw, - .chip_readl = fallback_chip_readl, - .chip_readn = fallback_chip_readn, - .chip_writeb = noop_chip_writeb, - .chip_writew = fallback_chip_writew, - .chip_writel = fallback_chip_writel, - .chip_writen = fallback_chip_writen, .delay = internal_delay, }, #endif @@ -286,14 +190,6 @@ .init = dediprog_init, .map_flash_region = fallback_map, .unmap_flash_region = fallback_unmap, - .chip_readb = noop_chip_readb, - .chip_readw = fallback_chip_readw, - .chip_readl = fallback_chip_readl, - .chip_readn = fallback_chip_readn, - .chip_writeb = noop_chip_writeb, - .chip_writew = fallback_chip_writew, - .chip_writel = fallback_chip_writel, - .chip_writen = fallback_chip_writen, .delay = internal_delay, }, #endif @@ -304,14 +200,6 @@ .init = rayer_spi_init, .map_flash_region = fallback_map, .unmap_flash_region = fallback_unmap, - .chip_readb = noop_chip_readb, - .chip_readw = fallback_chip_readw, - .chip_readl = fallback_chip_readl, - .chip_readn = fallback_chip_readn, - .chip_writeb = noop_chip_writeb, - .chip_writew = fallback_chip_writew, - .chip_writel = fallback_chip_writel, - .chip_writen = fallback_chip_writen, .delay = internal_delay, }, #endif @@ -322,14 +210,6 @@ .init = nicintel_init, .map_flash_region = fallback_map, .unmap_flash_region = fallback_unmap, - .chip_readb = nicintel_chip_readb, - .chip_readw = fallback_chip_readw, - .chip_readl = fallback_chip_readl, - .chip_readn = fallback_chip_readn, - .chip_writeb = nicintel_chip_writeb, - .chip_writew = fallback_chip_writew, - .chip_writel = fallback_chip_writel, - .chip_writen = fallback_chip_writen, .delay = internal_delay, }, #endif @@ -340,14 +220,6 @@ .init = nicintel_spi_init, .map_flash_region = fallback_map, .unmap_flash_region = fallback_unmap, - .chip_readb = noop_chip_readb, - .chip_readw = fallback_chip_readw, - .chip_readl = fallback_chip_readl, - .chip_readn = fallback_chip_readn, - .chip_writeb = noop_chip_writeb, - .chip_writew = fallback_chip_writew, - .chip_writel = fallback_chip_writel, - .chip_writen = fallback_chip_writen, .delay = internal_delay, }, #endif @@ -358,14 +230,6 @@ .init = ogp_spi_init, .map_flash_region = fallback_map, .unmap_flash_region = fallback_unmap, - .chip_readb = noop_chip_readb, - .chip_readw = fallback_chip_readw, - .chip_readl = fallback_chip_readl, - .chip_readn = fallback_chip_readn, - .chip_writeb = noop_chip_writeb, - .chip_writew = fallback_chip_writew, - .chip_writel = fallback_chip_writel, - .chip_writen = fallback_chip_writen, .delay = internal_delay, }, #endif @@ -376,14 +240,6 @@ .init = satamv_init, .map_flash_region = fallback_map, .unmap_flash_region = fallback_unmap, - .chip_readb = satamv_chip_readb, - .chip_readw = fallback_chip_readw, - .chip_readl = fallback_chip_readl, - .chip_readn = fallback_chip_readn, - .chip_writeb = satamv_chip_writeb, - .chip_writew = fallback_chip_writew, - .chip_writel = fallback_chip_writel, - .chip_writen = fallback_chip_writen, .delay = internal_delay, }, #endif @@ -394,14 +250,6 @@ .init = linux_spi_init, .map_flash_region = fallback_map, .unmap_flash_region = fallback_unmap, - .chip_readb = noop_chip_readb, - .chip_readw = fallback_chip_readw, - .chip_readl = fallback_chip_readl, - .chip_readn = fallback_chip_readn, - .chip_writeb = noop_chip_writeb, - .chip_writew = fallback_chip_writew, - .chip_writel = fallback_chip_writel, - .chip_writen = fallback_chip_writen, .delay = internal_delay, }, #endif @@ -513,42 +361,42 @@ void chip_writeb(uint8_t val, chipaddr addr) { - programmer_table[programmer].chip_writeb(val, addr); + par_programmer->chip_writeb(val, addr); } void chip_writew(uint16_t val, chipaddr addr) { - programmer_table[programmer].chip_writew(val, addr); + par_programmer->chip_writew(val, addr); } void chip_writel(uint32_t val, chipaddr addr) { - programmer_table[programmer].chip_writel(val, addr); + par_programmer->chip_writel(val, addr); } void chip_writen(uint8_t *buf, chipaddr addr, size_t len) { - programmer_table[programmer].chip_writen(buf, addr, len); + par_programmer->chip_writen(buf, addr, len); } uint8_t chip_readb(const chipaddr addr) { - return programmer_table[programmer].chip_readb(addr); + return par_programmer->chip_readb(addr); } uint16_t chip_readw(const chipaddr addr) { - return programmer_table[programmer].chip_readw(addr); + return par_programmer->chip_readw(addr); } uint32_t chip_readl(const chipaddr addr) { - return programmer_table[programmer].chip_readl(addr); + return par_programmer->chip_readl(addr); } void chip_readn(uint8_t *buf, chipaddr addr, size_t len) { - programmer_table[programmer].chip_readn(buf, addr, len); + par_programmer->chip_readn(buf, addr, len); } void programmer_delay(int usecs) Index: flashrom-register_par_programmer/programmer.h =================================================================== --- flashrom-register_par_programmer/programmer.h (Revision 1460) +++ flashrom-register_par_programmer/programmer.h (Arbeitskopie) @@ -97,14 +97,6 @@ size_t len); void (*unmap_flash_region) (void *virt_addr, size_t len); - void (*chip_writeb) (uint8_t val, chipaddr addr); - void (*chip_writew) (uint16_t val, chipaddr addr); - void (*chip_writel) (uint32_t val, chipaddr addr); - void (*chip_writen) (uint8_t *buf, chipaddr addr, size_t len); - uint8_t (*chip_readb) (const chipaddr addr); - uint16_t (*chip_readw) (const chipaddr addr); - uint32_t (*chip_readl) (const chipaddr addr); - void (*chip_readn) (uint8_t *buf, const chipaddr addr, size_t len); void (*delay) (int usecs); }; @@ -306,6 +298,7 @@ extern int force_boardmismatch; void probe_superio(void); int register_superio(struct superio s); +extern enum chipbustype internal_buses_supported; int internal_init(void); void internal_chip_writeb(uint8_t val, chipaddr addr); void internal_chip_writew(uint16_t val, chipaddr addr); @@ -360,6 +353,18 @@ uint16_t fallback_chip_readw(const chipaddr addr); uint32_t fallback_chip_readl(const chipaddr addr); void fallback_chip_readn(uint8_t *buf, const chipaddr addr, size_t len); +struct par_programmer { + void (*chip_writeb) (uint8_t val, chipaddr addr); + void (*chip_writew) (uint16_t val, chipaddr addr); + void (*chip_writel) (uint32_t val, chipaddr addr); + void (*chip_writen) (uint8_t *buf, chipaddr addr, size_t len); + uint8_t (*chip_readb) (const chipaddr addr); + uint16_t (*chip_readw) (const chipaddr addr); + uint32_t (*chip_readl) (const chipaddr addr); + void (*chip_readn) (uint8_t *buf, const chipaddr addr, size_t len); +}; +extern const struct par_programmer *par_programmer; +void register_par_programmer(const struct par_programmer *pgm, const enum chipbustype buses); /* dummyflasher.c */ #if CONFIG_DUMMY == 1 @@ -634,10 +639,6 @@ uint8_t serprog_chip_readb(const chipaddr addr); void serprog_chip_readn(uint8_t *buf, const chipaddr addr, size_t len); void serprog_delay(int usecs); -int serprog_spi_send_command(unsigned int writecnt, unsigned int readcnt, - const unsigned char *writearr, - unsigned char *readarr); -int serprog_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); #endif /* serial.c */ Index: flashrom-register_par_programmer/board_enable.c =================================================================== --- flashrom-register_par_programmer/board_enable.c (Revision 1460) +++ flashrom-register_par_programmer/board_enable.c (Arbeitskopie) @@ -425,7 +425,7 @@ /* Check if at least one flash segment is enabled. */ if (tmp & 0xf0) { /* The IT8705F will respond to LPC cycles and translate them. */ - buses_supported = BUS_PARALLEL; + internal_buses_supported = BUS_PARALLEL; /* Flash ROM I/F Writes Enable */ tmp |= 0x04; msg_pdbg("Enabling IT8705F flash ROM interface write.\n"); -- http://www.hailfinger.org/ From stefan.tauner at student.tuwien.ac.at Mon Nov 7 19:37:27 2011 From: stefan.tauner at student.tuwien.ac.at (Stefan Tauner) Date: Mon, 7 Nov 2011 19:37:27 +0100 Subject: [flashrom] report_flashrom_H55_chipset In-Reply-To: <20111027192948.16e69a03@arcor.de> References: <20111027192948.16e69a03@arcor.de> Message-ID: <201111071837.pA7IbDAO019911@mail2.student.tuwien.ac.at> Hello Greg, thanks for your report! On Thu, 27 Oct 2011 19:29:48 +0200 gregina wrote: > 0x5C: 0x05ff0001 (FREG2: Management Engine) > 0x00001000-0x005fffff is locked The problem is the locked ME region as quoted above. We are working on unlocking it, but intel does not provide us any documentation so please do not expect a solution soon. I have added the board to our list of (un)supported boards (with an appropriate note) and will commit that later together with other small changes. -- Kind regards/Mit freundlichen Gr??en, Stefan Tauner From stefan.tauner at student.tuwien.ac.at Mon Nov 7 19:56:11 2011 From: stefan.tauner at student.tuwien.ac.at (Stefan Tauner) Date: Mon, 7 Nov 2011 19:56:11 +0100 Subject: [flashrom] Addition to working hardware Asus Z8PE-D12 In-Reply-To: <4EB31572.70607@scarletline.com> References: <4EB31572.70607@scarletline.com> Message-ID: <201111071856.pA7Itv2j006014@mail2.student.tuwien.ac.at> On Thu, 03 Nov 2011 22:28:02 +0000 Kevin Shepherd wrote: > I would like to report complete success in upgrading my motherboard > BIOS, and to thank the developers for their hard work. My motherboard > is not yet listed in your working hardware lists. > > Motherboard: Asus Z8PE-D12 > OS: Ubuntu 11.04 amd64 > Please find attached my verbose log of the erase/write > (flashrom-asus-z8pe-d12.log), as well as the three requested logs from > your board testing page. > Here is the command run: > flashrom -V -w Z8PE-D12X-ASUS-1103.ROM > > - Kevin Shepherd > Hello Kevin, thanks for your report! I have marked the mainboard as supported and will commit that later together with other small changes. -- Kind regards/Mit freundlichen Gr??en, Stefan Tauner From stefan.tauner at student.tuwien.ac.at Mon Nov 7 20:21:45 2011 From: stefan.tauner at student.tuwien.ac.at (Stefan Tauner) Date: Mon, 7 Nov 2011 20:21:45 +0100 Subject: [flashrom] PMC Flash Pm29F002T-90PC - Write OK In-Reply-To: References: Message-ID: <201111071921.pA7JLWjh002955@mail2.student.tuwien.ac.at> On Mon, 31 Oct 2011 20:24:17 -0200 Marcos Felipe Rasia de Mello wrote: > It was tested in an Asus TUV4X (the original flash is a Winbond W49F002U-12B). > > Unfortunately this board uses the infamous AS99127F: > http://www.flashrom.org/pipermail/flashrom/2010-February/002339.html > > After "modprobe i2c-dev; i2cset 0 0x48 0x80 0x80" flashrom works > normally and update both chips without problems. > (didn't need to unload w83781d because I don't have lm-sensors installed here) > > Log attached. Hello Marcos, thanks for your report! I have marked the flash chip as fully tested and will commit that later together with other small changes. I won't touch anything else till someone answers my previous question(s) regarding the VIA chipset enables. Also, i have no idea about the needed i2c integration or if any progress have been made so far. The TUV4X should probably be added to our list with an appropriate note. Also, the A7V133 is already on the list although it probably does not work out of the box either(?) -- Kind regards/Mit freundlichen Gr??en, Stefan Tauner From stefan.tauner at student.tuwien.ac.at Mon Nov 7 23:51:58 2011 From: stefan.tauner at student.tuwien.ac.at (Stefan Tauner) Date: Mon, 7 Nov 2011 23:51:58 +0100 Subject: [flashrom] [PATCH 2/2] ichspi: add support for Intel Hardware Sequencing In-Reply-To: <4EB71529.1020005@gmx.net> References: <1319636118-15878-1-git-send-email-stefan.tauner@student.tuwien.ac.at> <1319636118-15878-3-git-send-email-stefan.tauner@student.tuwien.ac.at> <4EB71529.1020005@gmx.net> Message-ID: <201111072251.pA7MpkJN019593@mail2.student.tuwien.ac.at> On Mon, 07 Nov 2011 00:15:53 +0100 Carl-Daniel Hailfinger wrote: > Am 26.10.2011 15:35 schrieb Stefan Tauner: > > Based on the new opaque programmer framework this patch adds support > > for Intel Hardware Sequencing on ICH8 and its successors. > > > > By default (or when setting the ich_spi_mode option to auto) > > the module tries to use swseq and only activates hwseq if need be: > > - if important opcodes are inaccessible due to lockdown > > - if more than one flash chip is attached. > > The other options (swseq, hwseq) select the respective mode (if possible). > > > > A general description of Hardware Sequencing can be found in this blog entry: > > http://blogs.coreboot.org/blog/2011/06/11/gsoc-2011-flashrom-part-1/ > > > > TODO: adding real documentation when we have a directory for it > > > > Signed-off-by: Stefan Tauner > > Acked-by: Carl-Daniel Hailfinger thanks, but ignored for now. > with a few small comments. in contrast to those of course ;) > > --- > > flashrom.8 | 20 +++++ > > ichspi.c | 268 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++- > > 2 files changed, 283 insertions(+), 5 deletions(-) > > > > diff --git a/flashrom.8 b/flashrom.8 > > index a8f4660..66cde4f 100644 > > --- a/flashrom.8 > > +++ b/flashrom.8 > > @@ -303,6 +303,26 @@ is the I/O port number (must be a multiple of 8). In the unlikely case > > flashrom doesn't detect an active IT87 LPC<->SPI bridge, please send a bug > > report so we can diagnose the problem. > > .sp > > +If you have an Intel chipset with an ICH8 or later southbridge with SPI flash > > +attached, and if a valid descriptor was written to it (e.g. by the vendor), the > > +chipset provides an alternative way to access the flash chip(s) named > > +.BR "Hardware Sequencing" . > > +It is much simpler than the normal access method (called > > +.BR "Software Sequencing" ")," > > +but does not allow the software to choose the SPI commands to be sent. > > +You can use the > > +.sp > > +.B " flashrom \-p internal:ich_spi_mode=value" > > +.sp > > +syntax where value can be > > +.BR auto ", " swseq " or " hwseq . > > +By default > > +.RB "(or when setting " ich_spi_mode=auto ) > > +the module tries to use swseq and only activates hwseq if need be (e.g. if > > +important opcodes are inaccessible due to lockdown; or if more than one flash > > +chip is attached). The other options (swseq, hwseq) select the respective mode > > +(if possible). > > +.sp > > If you have an Intel chipset with an ICH6 or later southbridge and if you want > > to set specific IDSEL values for a non-default flash chip or an embedded > > controller (EC), you can use the > > diff --git a/ichspi.c b/ichspi.c > > index bc03554..1d5dd34 100644 > > --- a/ichspi.c > > +++ b/ichspi.c > > @@ -575,6 +575,25 @@ static int program_opcodes(int ich_generation, OPCODES *op, int enable_undo) > > return 0; > > } > > > > +/* Returns true if the most important opcodes are accessible. */ > > You assume that some erase opcode will be available if BYTE_PROGRAM is > available. I think that assumption is reasonable, but it could be > documented in this comment above the function. this was just a basis for discussion actually. sorry for not explaining that bit. there are more problems than just the missing check for *any* available erase opcode. i do not intend to fix this soon. OTOH it is not really a problem imho. if this trigger would enable hwseq the bios has probably not only locked down the opcodes, but also set up PR or FREG/FRAP protections, which we can not deal with correctly yet, not even with hwseq. so *not* selecting hwseq due to a too simple ich_check_opcodes method will not hurt us, because it would not have saved us from failure anyway. i have reduced the method to the absolute minimum (see patch) and added the following comment: * FIXME: this should also check for * - at least one probing opcode (RDID (incl. AT25F variants?), REMS, RES?) * - at least one erasing opcode (lots.) * - at least one program opcode (BYTE_PROGRAM, AAI_WORD_PROGRAM, ...?) * - necessary preops? (EWSR, WREN, ...?) > > [?] > > +static const struct opaque_programmer opaque_programmer_ich_hwseq = { > > + .max_data_read = 64, > > + .max_data_write = 64, > > + .probe = ich_hwseq_probe, > > + .read = ich_hwseq_read, > > + .write = ich_hwseq_write, > > Please add ich_hwseq_block_erase here. done > > [?] > > + arg = extract_programmer_param("ich_spi_mode"); > > + if (arg && !strcmp(arg, "hwseq")) { > > + ich_spi_mode = ich_hwseq; > > + msg_pspew("user selected hwseq\n"); > > + } else if (arg && !strcmp(arg, "swseq")) { > > + ich_spi_mode = ich_swseq; > > + msg_pspew("user selected swseq\n"); > > + } else if (arg && !strcmp(arg, "auto")) { > > + msg_pspew("user selected auto\n"); > > + ich_spi_mode = ich_auto; > > + } else if (arg && !strlen(arg)) > > + msg_pinfo("Missing argument for ich_spi_mode.\n"); > > + else if (arg) > > + msg_pinfo("Unknown argument for ich_spi_mode: %s\n", arg); > > We should return an error all the way up to programmer init for both > cases (and clean up everything). I know that this is a complicated code > path, so if you decide not to fail programmer init here, please add a > comment like the one below: > /* FIXME: Return an error to programmer_init. */ fixing this was not that easy, because the ich code in chipset_enable.c was not passing the fatal error further; see patch. > > [?] > > + if (ich_spi_mode == ich_hwseq) { > > + if (!desc_valid) { > > + msg_perr("Hardware sequencing was requested " > > + "but the flash descriptor is not " > > + "valid. Aborting.\n"); > > + return 1; > > Can you check that this indeed causes flashrom to return an error from > programmer_init? Chipset init IIRC ignores most errors unless they are > somehow declared to be fatal. done. and also if a bogus ich_gen is passed to ichspi_init at the beginning of the function. i am not sure if it was due to the changes to the previous patches, but ich_init_opcodes() were missing from the ich8+ code path (again). besides that i have also added null-pointer guards to find_opcode and find_preop, because i think it matches the other opcode methods better (curopcodes == NULL has some meaning and is actively used/checked in other functions). ps: you like to abort when the user gets the command line wrong for safety. there is a case we do not handle in this manner. for example with this patch set one can do: flashrom -p internal:laptop=force_I_want_a_brick,ich_spi_mode it prints "Unhandled programmer parameters: ich_spi_mode" but continues, you may wanna look into this. -- Kind regards/Mit freundlichen Gr??en, Stefan Tauner -------------- next part -------------- A non-text attachment was scrubbed... Name: 0001-squash-ichspi-add-support-for-Intel-Hardware-Sequenc.patch Type: text/x-patch Size: 5855 bytes Desc: not available URL: From c-d.hailfinger.devel.2006 at gmx.net Tue Nov 8 01:05:01 2011 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Tue, 08 Nov 2011 01:05:01 +0100 Subject: [flashrom] [PATCH 2/2] ichspi: add support for Intel Hardware Sequencing In-Reply-To: <201111072251.pA7MpkJN019593@mail2.student.tuwien.ac.at> References: <1319636118-15878-1-git-send-email-stefan.tauner@student.tuwien.ac.at> <1319636118-15878-3-git-send-email-stefan.tauner@student.tuwien.ac.at> <4EB71529.1020005@gmx.net> <201111072251.pA7MpkJN019593@mail2.student.tuwien.ac.at> Message-ID: <4EB8722D.6010605@gmx.net> Am 07.11.2011 23:51 schrieb Stefan Tauner: > On Mon, 07 Nov 2011 00:15:53 +0100 > Carl-Daniel Hailfinger wrote: > >> > Am 26.10.2011 15:35 schrieb Stefan Tauner: >>> > > Based on the new opaque programmer framework this patch adds support >>> > > for Intel Hardware Sequencing on ICH8 and its successors. >>> > > >>> > > By default (or when setting the ich_spi_mode option to auto) >>> > > the module tries to use swseq and only activates hwseq if need be: >>> > > - if important opcodes are inaccessible due to lockdown >>> > > - if more than one flash chip is attached. >>> > > The other options (swseq, hwseq) select the respective mode (if possible). >>> > > >>> > > A general description of Hardware Sequencing can be found in this blog entry: >>> > > http://blogs.coreboot.org/blog/2011/06/11/gsoc-2011-flashrom-part-1/ >>> > > >>> > > TODO: adding real documentation when we have a directory for it >>> > > >>> > > Signed-off-by: Stefan Tauner >> > >> > Acked-by: Carl-Daniel Hailfinger > thanks, but ignored for now. Hm, so if I ack this patch as well, will you commit one combined patch? >> > with a few small comments. > in contrast to those of course ;) > >>> > > --- >>> > > flashrom.8 | 20 +++++ >>> > > ichspi.c | 268 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++- >>> > > 2 files changed, 283 insertions(+), 5 deletions(-) >>> > > >>> > > diff --git a/flashrom.8 b/flashrom.8 >>> > > index a8f4660..66cde4f 100644 >>> > > --- a/flashrom.8 >>> > > +++ b/flashrom.8 >>> > > @@ -303,6 +303,26 @@ is the I/O port number (must be a multiple of 8). In the unlikely case >>> > > flashrom doesn't detect an active IT87 LPC<->SPI bridge, please send a bug >>> > > report so we can diagnose the problem. >>> > > .sp >>> > > +If you have an Intel chipset with an ICH8 or later southbridge with SPI flash >>> > > +attached, and if a valid descriptor was written to it (e.g. by the vendor), the >>> > > +chipset provides an alternative way to access the flash chip(s) named >>> > > +.BR "Hardware Sequencing" . >>> > > +It is much simpler than the normal access method (called >>> > > +.BR "Software Sequencing" ")," >>> > > +but does not allow the software to choose the SPI commands to be sent. >>> > > +You can use the >>> > > +.sp >>> > > +.B " flashrom \-p internal:ich_spi_mode=value" >>> > > +.sp >>> > > +syntax where value can be >>> > > +.BR auto ", " swseq " or " hwseq . >>> > > +By default >>> > > +.RB "(or when setting " ich_spi_mode=auto ) >>> > > +the module tries to use swseq and only activates hwseq if need be (e.g. if >>> > > +important opcodes are inaccessible due to lockdown; or if more than one flash >>> > > +chip is attached). The other options (swseq, hwseq) select the respective mode >>> > > +(if possible). >>> > > +.sp >>> > > If you have an Intel chipset with an ICH6 or later southbridge and if you want >>> > > to set specific IDSEL values for a non-default flash chip or an embedded >>> > > controller (EC), you can use the >>> > > diff --git a/ichspi.c b/ichspi.c >>> > > index bc03554..1d5dd34 100644 >>> > > --- a/ichspi.c >>> > > +++ b/ichspi.c >>> > > @@ -575,6 +575,25 @@ static int program_opcodes(int ich_generation, OPCODES *op, int enable_undo) >>> > > return 0; >>> > > } >>> > > >>> > > +/* Returns true if the most important opcodes are accessible. */ >> > >> > You assume that some erase opcode will be available if BYTE_PROGRAM is >> > available. I think that assumption is reasonable, but it could be >> > documented in this comment above the function. > this was just a basis for discussion actually. sorry for not explaining > that bit. there are more problems than just the missing check for *any* > available erase opcode. > > i do not intend to fix this soon. OTOH it is not really a problem imho. > if this trigger would enable hwseq the bios has probably not only > locked down the opcodes, but also set up PR or FREG/FRAP protections, > which we can not deal with correctly yet, not even with hwseq. so *not* > selecting hwseq due to a too simple ich_check_opcodes method will not > hurt us, because it would not have saved us from failure anyway. > > i have reduced the method to the absolute minimum (see patch) and > added the following comment: > * FIXME: this should also check for > * - at least one probing opcode (RDID (incl. AT25F variants?), REMS, RES?) > * - at least one erasing opcode (lots.) > * - at least one program opcode (BYTE_PROGRAM, AAI_WORD_PROGRAM, ...?) > * - necessary preops? (EWSR, WREN, ...?) Nice. > >>> > > [?] >>> > > + arg = extract_programmer_param("ich_spi_mode"); >>> > > + if (arg && !strcmp(arg, "hwseq")) { >>> > > + ich_spi_mode = ich_hwseq; >>> > > + msg_pspew("user selected hwseq\n"); >>> > > + } else if (arg && !strcmp(arg, "swseq")) { >>> > > + ich_spi_mode = ich_swseq; >>> > > + msg_pspew("user selected swseq\n"); >>> > > + } else if (arg && !strcmp(arg, "auto")) { >>> > > + msg_pspew("user selected auto\n"); >>> > > + ich_spi_mode = ich_auto; >>> > > + } else if (arg && !strlen(arg)) >>> > > + msg_pinfo("Missing argument for ich_spi_mode.\n"); >>> > > + else if (arg) >>> > > + msg_pinfo("Unknown argument for ich_spi_mode: %s\n", arg); >> > >> > We should return an error all the way up to programmer init for both >> > cases (and clean up everything). I know that this is a complicated code >> > path, so if you decide not to fail programmer init here, please add a >> > comment like the one below: >> > /* FIXME: Return an error to programmer_init. */ > fixing this was not that easy, because the ich code in chipset_enable.c > was not passing the fatal error further; see patch. This code was indeed suboptimal. Thanks for fixing it! >>> > > [?] >>> > > + if (ich_spi_mode == ich_hwseq) { >>> > > + if (!desc_valid) { >>> > > + msg_perr("Hardware sequencing was requested " >>> > > + "but the flash descriptor is not " >>> > > + "valid. Aborting.\n"); >>> > > + return 1; >> > >> > Can you check that this indeed causes flashrom to return an error from >> > programmer_init? Chipset init IIRC ignores most errors unless they are >> > somehow declared to be fatal. > done. and also if a bogus ich_gen is passed to ichspi_init at the > beginning of the function. > > i am not sure if it was due to the changes to the previous patches, but > ich_init_opcodes() were missing from the ich8+ code path (again). > > besides that i have also added null-pointer guards to find_opcode and > find_preop, because i think it matches the other opcode methods better > (curopcodes == NULL has some meaning and is actively used/checked in > other functions). Nice. > ps: you like to abort when the user gets the command line wrong for > safety. there is a case we do not handle in this manner. for example > with this patch set one can do: > flashrom -p internal:laptop=force_I_want_a_brick,ich_spi_mode > it prints "Unhandled programmer parameters: ich_spi_mode" but > continues, you may wanna look into this. I have a fix handy, I just didn't want to push such a patch in before hwseq because that would feel like jumping the review queue. > >From 9d85001930afc54ca724d75dc80a7ca7e26c1b6d Mon Sep 17 00:00:00 2001 > From: Stefan Tauner > Date: Mon, 7 Nov 2011 21:06:36 +0100 > Subject: [PATCH] squash! ichspi: add support for Intel Hardware Sequencing > > - Fix enable_flash_ich_dc_spi to pass ERROR_FATAL from ich_init_spi. > The whole error handling looks a bit odd to me, so this patch does change very > little. Also, it does not touch the tunnelcreek method, which should be refactored > anyway. > > - Add null-pointer guards to find_opcode and find_preop > to matches the other opcode methods better: > curopcodes == NULL has some meaning and is actively used/checked in other > functions. > > Signed-off-by: Stefan Tauner Acked-by: Carl-Daniel Hailfinger with comments. > diff --git a/ichspi.c b/ichspi.c > index 85456cd..3c3b7f1 100644 > --- a/ichspi.c > +++ b/ichspi.c > @@ -560,23 +570,29 @@ static int program_opcodes(OPCODES *op, int enable_undo) > return 0; > } > > -/* Returns true if the most important opcodes are accessible. */ > +/* > + * Checks if all of the most important opcodes are accessible. > + * Returns 0 if they are, or the first opcode to be found inaccessible. > + * FIXME: this should also check for > + * - at least one probing opcode (RDID (incl. AT25F variants?), REMS, RES?) > + * - at least one erasing opcode (lots.) > + * - at least one program opcode (BYTE_PROGRAM, AAI_WORD_PROGRAM, ...?) > + * - necessary preops? (EWSR, WREN, ...?) > + */ > static int ich_check_opcodes() > { > uint8_t ops[] = { > JEDEC_READ, > - JEDEC_BYTE_PROGRAM, > JEDEC_RDSR, > 0 > }; > int i = 0; > while (ops[i] != 0) { > - msg_pspew("checking for opcode 0x%02x\n", ops[i]); > if (find_opcode(curopcodes, ops[i]) == -1) > - return 0; > + return ops[i]; Can you return 1 (or -1 or some other nonzero value) instead? Returning one missing opcode reduces redability and provides no gain (other missing opcodes are ignored). Unless I'm mistaken, we'll see the available opcodes anyway in the verbose log. > i++; > } > - return 1; > + return 0; > } > > /* > @@ -1705,9 +1729,9 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, > } > > if (ich_spi_mode == ich_auto && ichspi_lock && > - !ich_check_opcodes()) { > + (i = ich_check_opcodes()) != 0) { ich_check_opcodes()) { > msg_pinfo("Enabling hardware sequencing because " > - "some important opcodes are locked.\n"); > + "opcode 0x%02x is inaccessible.\n", i); Please keep the old message or at least replace "opcode 0x%02x" with "some important opcode". > ich_spi_mode = ich_hwseq; > } > Regards, Carl-Daniel -- http://www.hailfinger.org/ From marcosfrm at gmail.com Tue Nov 8 11:19:55 2011 From: marcosfrm at gmail.com (Marcos Felipe Rasia de Mello) Date: Tue, 8 Nov 2011 08:19:55 -0200 Subject: [flashrom] PMC Flash Pm29F002T-90PC - Write OK In-Reply-To: <201111071921.pA7JLWjh002955@mail2.student.tuwien.ac.at> References: <201111071921.pA7JLWjh002955@mail2.student.tuwien.ac.at> Message-ID: 2011/11/7 Stefan Tauner > > thanks for your report! > I have marked the flash chip as fully tested and will commit that later > together with other small changes. I won't touch anything else till > someone answers my previous question(s) regarding the VIA chipset > enables. > > Also, i have no idea about the needed i2c integration or if > any progress have been made so far. The TUV4X should probably be added > to our list with an appropriate note. Also, the A7V133 is already on the > list although it probably does not work out of the box either(?) > Without setting the register with i2cset flashrom doesn't detect the flash chip. I supose the same applies to the A7V133. If you need more info about the board please ask. Marcos From svn at flashrom.org Tue Nov 8 11:55:55 2011 From: svn at flashrom.org (repository service) Date: Tue, 08 Nov 2011 11:55:55 +0100 Subject: [flashrom] [commit] r1461 - trunk Message-ID: Author: stefanct Date: Tue Nov 8 11:55:54 2011 New Revision: 1461 URL: http://flashrom.org/trac/flashrom/changeset/1461 Log: ichspi: add support for Intel Hardware Sequencing Based on the new opaque programmer framework this patch adds support for Intel Hardware Sequencing on ICH8 and its successors. By default (or when setting the ich_spi_mode option to auto) the module tries to use swseq and only activates hwseq if need be: - if important opcodes are inaccessible due to lockdown - if more than one flash chip is attached. The other options (swseq, hwseq) select the respective mode (if possible). A general description of Hardware Sequencing can be found in this blog entry: http://blogs.coreboot.org/blog/2011/06/11/gsoc-2011-flashrom-part-1/ Besides adding hwseq this patch also introduces these unrelated changes: - Fix enable_flash_ich_dc_spi to pass ERROR_FATAL from ich_init_spi. The whole error handling looks a bit odd to me, so this patch does change very little. Also, it does not touch the tunnelcreek method, which should be refactored anyway. - Add null-pointer guards to find_opcode and find_preop to matches the other opcode methods better: curopcodes == NULL has some meaning and is actively used/checked in other functions. TODO: adding real documentation when we have a directory for it Signed-off-by: Stefan Tauner Acked-by: Carl-Daniel Hailfinger Modified: trunk/chipset_enable.c trunk/flashrom.8 trunk/ichspi.c Modified: trunk/chipset_enable.c ============================================================================== --- trunk/chipset_enable.c Mon Nov 7 00:51:09 2011 (r1460) +++ trunk/chipset_enable.c Tue Nov 8 11:55:54 2011 (r1461) @@ -491,7 +491,7 @@ static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name, enum ich_chipset ich_generation) { - int ret; + int ret, ret_spi; uint8_t bbs, buc; uint32_t tmp, gcs; void *rcrb; @@ -569,10 +569,12 @@ } /* This adds BUS_SPI */ - if (ich_init_spi(dev, tmp, rcrb, ich_generation) != 0) { - if (!ret) - ret = ERROR_NONFATAL; - } + ret_spi = ich_init_spi(dev, tmp, rcrb, ich_generation); + if (ret_spi == ERROR_FATAL) + return ret_spi; + + if (ret || ret_spi) + ret = ERROR_NONFATAL; return ret; } Modified: trunk/flashrom.8 ============================================================================== --- trunk/flashrom.8 Mon Nov 7 00:51:09 2011 (r1460) +++ trunk/flashrom.8 Tue Nov 8 11:55:54 2011 (r1461) @@ -303,6 +303,26 @@ flashrom doesn't detect an active IT87 LPC<->SPI bridge, please send a bug report so we can diagnose the problem. .sp +If you have an Intel chipset with an ICH8 or later southbridge with SPI flash +attached, and if a valid descriptor was written to it (e.g. by the vendor), the +chipset provides an alternative way to access the flash chip(s) named +.BR "Hardware Sequencing" . +It is much simpler than the normal access method (called +.BR "Software Sequencing" ")," +but does not allow the software to choose the SPI commands to be sent. +You can use the +.sp +.B " flashrom \-p internal:ich_spi_mode=value" +.sp +syntax where value can be +.BR auto ", " swseq " or " hwseq . +By default +.RB "(or when setting " ich_spi_mode=auto ) +the module tries to use swseq and only activates hwseq if need be (e.g. if +important opcodes are inaccessible due to lockdown; or if more than one flash +chip is attached). The other options (swseq, hwseq) select the respective mode +(if possible). +.sp If you have an Intel chipset with an ICH6 or later southbridge and if you want to set specific IDSEL values for a non-default flash chip or an embedded controller (EC), you can use the Modified: trunk/ichspi.c ============================================================================== --- trunk/ichspi.c Mon Nov 7 00:51:09 2011 (r1460) +++ trunk/ichspi.c Tue Nov 8 11:55:54 2011 (r1461) @@ -423,6 +423,11 @@ { int a; + if (op == NULL) { + msg_perr("\n%s: null OPCODES pointer!\n", __func__); + return -1; + } + for (a = 0; a < 8; a++) { if (op->opcode[a].opcode == opcode) return a; @@ -435,6 +440,11 @@ { int a; + if (op == NULL) { + msg_perr("\n%s: null OPCODES pointer!\n", __func__); + return -1; + } + for (a = 0; a < 2; a++) { if (op->preop[a] == preop) return a; @@ -561,6 +571,31 @@ } /* + * Returns -1 if at least one mandatory opcode is inaccessible, 0 otherwise. + * FIXME: this should also check for + * - at least one probing opcode (RDID (incl. AT25F variants?), REMS, RES?) + * - at least one erasing opcode (lots.) + * - at least one program opcode (BYTE_PROGRAM, AAI_WORD_PROGRAM, ...?) + * - necessary preops? (EWSR, WREN, ...?) + */ +static int ich_missing_opcodes() +{ + uint8_t ops[] = { + JEDEC_READ, + JEDEC_RDSR, + 0 + }; + int i = 0; + while (ops[i] != 0) { + msg_pspew("checking for opcode 0x%02x\n", ops[i]); + if (find_opcode(curopcodes, ops[i]) == -1) + return -1; + i++; + } + return 0; +} + +/* * Try to set BBAR (BIOS Base Address Register), but read back the value in case * it didn't stick. */ @@ -1066,7 +1101,11 @@ return result; } -#if 0 +static struct hwseq_data { + uint32_t size_comp0; + uint32_t size_comp1; +} hwseq_data; + /* Sets FLA in FADDR to (addr & 0x01FFFFFF) without touching other bits. */ static void ich_hwseq_set_addr(uint32_t addr) { @@ -1117,8 +1156,8 @@ if (!timeout) { addr = REGREAD32(ICH9_REG_FADDR) & 0x01FFFFFF; msg_perr("Timeout error between offset 0x%08x and " - "0x%08x + %d (=0x%08x)!\n", - addr, addr, len - 1, addr + len - 1); + "0x%08x (= 0x%08x + %d)!\n", + addr, addr + len - 1, addr, len - 1); prettyprint_ich9_reg_hsfs(hsfs); prettyprint_ich9_reg_hsfc(REGREAD16(ICH9_REG_HSFC)); return 1; @@ -1127,7 +1166,7 @@ if (hsfs & HSFS_FCERR) { addr = REGREAD32(ICH9_REG_FADDR) & 0x01FFFFFF; msg_perr("Transaction error between offset 0x%08x and " - "0x%08x (=0x%08x + %d)!\n", + "0x%08x (= 0x%08x + %d)!\n", addr, addr + len - 1, addr, len - 1); prettyprint_ich9_reg_hsfs(hsfs); prettyprint_ich9_reg_hsfc(REGREAD16(ICH9_REG_HSFC)); @@ -1135,7 +1174,184 @@ } return 0; } -#endif + +int ich_hwseq_probe(struct flashchip *flash) +{ + uint32_t total_size, boundary; + uint32_t erase_size_low, size_low, erase_size_high, size_high; + struct block_eraser *eraser; + + total_size = hwseq_data.size_comp0 + hwseq_data.size_comp1; + msg_cdbg("Found %d attached SPI flash chip", + (hwseq_data.size_comp1 != 0) ? 2 : 1); + if (hwseq_data.size_comp1 != 0) + msg_cdbg("s with a combined"); + else + msg_cdbg(" with a"); + msg_cdbg(" density of %d kB.\n", total_size / 1024); + flash->total_size = total_size / 1024; + + eraser = &(flash->block_erasers[0]); + boundary = (REGREAD32(ICH9_REG_FPB) & FPB_FPBA) << 12; + size_high = total_size - boundary; + erase_size_high = ich_hwseq_get_erase_block_size(boundary); + + if (boundary == 0) { + msg_cdbg("There is only one partition containing the whole " + "address space (0x%06x - 0x%06x).\n", 0, size_high-1); + eraser->eraseblocks[0].size = erase_size_high; + eraser->eraseblocks[0].count = size_high / erase_size_high; + msg_cdbg("There are %d erase blocks with %d B each.\n", + size_high / erase_size_high, erase_size_high); + } else { + msg_cdbg("The flash address space (0x%06x - 0x%06x) is divided " + "at address 0x%06x in two partitions.\n", + 0, size_high-1, boundary); + size_low = total_size - size_high; + erase_size_low = ich_hwseq_get_erase_block_size(0); + + eraser->eraseblocks[0].size = erase_size_low; + eraser->eraseblocks[0].count = size_low / erase_size_low; + msg_cdbg("The first partition ranges from 0x%06x to 0x%06x.\n", + 0, size_low-1); + msg_cdbg("In that range are %d erase blocks with %d B each.\n", + size_low / erase_size_low, erase_size_low); + + eraser->eraseblocks[1].size = erase_size_high; + eraser->eraseblocks[1].count = size_high / erase_size_high; + msg_cdbg("The second partition ranges from 0x%06x to 0x%06x.\n", + boundary, size_high-1); + msg_cdbg("In that range are %d erase blocks with %d B each.\n", + size_high / erase_size_high, erase_size_high); + } + flash->tested = TEST_OK_PREW; + return 1; +} + +int ich_hwseq_block_erase(struct flashchip *flash, + unsigned int addr, + unsigned int len) +{ + uint32_t erase_block; + uint16_t hsfc; + uint32_t timeout = 5000 * 1000; /* 5 s for max 64 kB */ + + erase_block = ich_hwseq_get_erase_block_size(addr); + if (len != erase_block) { + msg_cerr("Erase block size for address 0x%06x is %d B, " + "but requested erase block size is %d B. " + "Not erasing anything.\n", addr, erase_block, len); + return -1; + } + + /* Although the hardware supports this (it would erase the whole block + * containing the address) we play safe here. */ + if (addr % erase_block != 0) { + msg_cerr("Erase address 0x%06x is not aligned to the erase " + "block boundary (any multiple of %d). " + "Not erasing anything.\n", addr, erase_block); + return -1; + } + + if (addr + len > flash->total_size * 1024) { + msg_perr("Request to erase some inaccessible memory address(es)" + " (addr=0x%x, len=%d). " + "Not erasing anything.\n", addr, len); + return -1; + } + + msg_pdbg("Erasing %d bytes starting at 0x%06x.\n", len, addr); + + /* make sure FDONE, FCERR, AEL are cleared by writing 1 to them */ + REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS)); + + hsfc = REGREAD16(ICH9_REG_HSFC); + hsfc &= ~HSFC_FCYCLE; /* clear operation */ + hsfc |= (0x3 << HSFC_FCYCLE_OFF); /* set erase operation */ + hsfc |= HSFC_FGO; /* start */ + msg_pdbg("HSFC used for block erasing: "); + prettyprint_ich9_reg_hsfc(hsfc); + REGWRITE16(ICH9_REG_HSFC, hsfc); + + if (ich_hwseq_wait_for_cycle_complete(timeout, len)) + return -1; + return 0; +} + +int ich_hwseq_read(struct flashchip *flash, uint8_t *buf, int addr, int len) +{ + uint16_t hsfc; + uint16_t timeout = 100 * 60; + uint8_t block_len; + + if (addr < 0 || addr + len > flash->total_size * 1024) { + msg_perr("Request to read from an inaccessible memory address " + "(addr=0x%x, len=%d).\n", addr, len); + return -1; + } + + msg_pdbg("Reading %d bytes starting at 0x%06x.\n", len, addr); + /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */ + REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS)); + + while (len > 0) { + block_len = min(len, opaque_programmer->max_data_read); + ich_hwseq_set_addr(addr); + hsfc = REGREAD16(ICH9_REG_HSFC); + hsfc &= ~HSFC_FCYCLE; /* set read operation */ + hsfc &= ~HSFC_FDBC; /* clear byte count */ + /* set byte count */ + hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC); + hsfc |= HSFC_FGO; /* start */ + REGWRITE16(ICH9_REG_HSFC, hsfc); + + if (ich_hwseq_wait_for_cycle_complete(timeout, block_len)) + return 1; + ich_read_data(buf, block_len, ICH9_REG_FDATA0); + addr += block_len; + buf += block_len; + len -= block_len; + } + return 0; +} + +int ich_hwseq_write(struct flashchip *flash, uint8_t *buf, int addr, int len) +{ + uint16_t hsfc; + uint16_t timeout = 100 * 60; + uint8_t block_len; + + if (addr < 0 || addr + len > flash->total_size * 1024) { + msg_perr("Request to write to an inaccessible memory address " + "(addr=0x%x, len=%d).\n", addr, len); + return -1; + } + + msg_pdbg("Writing %d bytes starting at 0x%06x.\n", len, addr); + /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */ + REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS)); + + while (len > 0) { + ich_hwseq_set_addr(addr); + block_len = min(len, opaque_programmer->max_data_write); + ich_fill_data(buf, block_len, ICH9_REG_FDATA0); + hsfc = REGREAD16(ICH9_REG_HSFC); + hsfc &= ~HSFC_FCYCLE; /* clear operation */ + hsfc |= (0x2 << HSFC_FCYCLE_OFF); /* set write operation */ + hsfc &= ~HSFC_FDBC; /* clear byte count */ + /* set byte count */ + hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC); + hsfc |= HSFC_FGO; /* start */ + REGWRITE16(ICH9_REG_HSFC, hsfc); + + if (ich_hwseq_wait_for_cycle_complete(timeout, block_len)) + return -1; + addr += block_len; + buf += block_len; + len -= block_len; + } + return 0; +} static int ich_spi_send_multicommand(struct spi_command *cmds) { @@ -1300,6 +1516,15 @@ .write_256 = default_spi_write_256, }; +static const struct opaque_programmer opaque_programmer_ich_hwseq = { + .max_data_read = 64, + .max_data_write = 64, + .probe = ich_hwseq_probe, + .read = ich_hwseq_read, + .write = ich_hwseq_write, + .erase = ich_hwseq_block_erase, +}; + int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, enum ich_chipset ich_gen) { @@ -1307,13 +1532,20 @@ uint8_t old, new; uint16_t spibar_offset, tmp2; uint32_t tmp; + char *arg; int desc_valid = 0; + struct ich_descriptors desc = {{ 0 }}; + enum ich_spi_mode { + ich_auto, + ich_hwseq, + ich_swseq + } ich_spi_mode = ich_auto; ich_generation = ich_gen; switch (ich_generation) { case CHIPSET_ICH_UNKNOWN: - return -1; + return ERROR_FATAL; case CHIPSET_ICH7: case CHIPSET_ICH8: spibar_offset = 0x3020; @@ -1330,6 +1562,8 @@ /* Assign Virtual Address */ ich_spibar = rcrb + spibar_offset; + ich_init_opcodes(); + switch (ich_generation) { case CHIPSET_ICH7: msg_pdbg("0x00: 0x%04x (SPIS)\n", @@ -1369,10 +1603,31 @@ } ich_set_bbar(0); register_spi_programmer(&spi_programmer_ich7); - ich_init_opcodes(); break; case CHIPSET_ICH8: default: /* Future version might behave the same */ + arg = extract_programmer_param("ich_spi_mode"); + if (arg && !strcmp(arg, "hwseq")) { + ich_spi_mode = ich_hwseq; + msg_pspew("user selected hwseq\n"); + } else if (arg && !strcmp(arg, "swseq")) { + ich_spi_mode = ich_swseq; + msg_pspew("user selected swseq\n"); + } else if (arg && !strcmp(arg, "auto")) { + msg_pspew("user selected auto\n"); + ich_spi_mode = ich_auto; + } else if (arg && !strlen(arg)) { + msg_perr("Missing argument for ich_spi_mode.\n"); + free(arg); + return ERROR_FATAL; + } else if (arg) { + msg_perr("Unknown argument for ich_spi_mode: %s\n", + arg); + free(arg); + return ERROR_FATAL; + } + free(arg); + tmp2 = mmio_readw(ich_spibar + ICH9_REG_HSFS); msg_pdbg("0x04: 0x%04x (HSFS)\n", tmp2); prettyprint_ich9_reg_hsfs(tmp2); @@ -1458,14 +1713,41 @@ msg_pdbg("\n"); if (desc_valid) { - struct ich_descriptors desc = {{ 0 }}; if (read_ich_descriptors_via_fdo(ich_spibar, &desc) == ICH_RET_OK) prettyprint_ich_descriptors(CHIPSET_ICH_UNKNOWN, &desc); + /* If the descriptor is valid and indicates multiple + * flash devices we need to use hwseq to be able to + * access the second flash device. + */ + if (ich_spi_mode == ich_auto && desc.content.NC != 0) { + msg_pinfo("Enabling hardware sequencing due to " + "multiple flash chips detected.\n"); + ich_spi_mode = ich_hwseq; + } + } + + if (ich_spi_mode == ich_auto && ichspi_lock && + ich_missing_opcodes()) { + msg_pinfo("Enabling hardware sequencing because " + "some important opcode is locked.\n"); + ich_spi_mode = ich_hwseq; + } + + if (ich_spi_mode == ich_hwseq) { + if (!desc_valid) { + msg_perr("Hardware sequencing was requested " + "but the flash descriptor is not " + "valid. Aborting.\n"); + return ERROR_FATAL; + } + hwseq_data.size_comp0 = getFCBA_component_density(&desc, 0); + hwseq_data.size_comp1 = getFCBA_component_density(&desc, 1); + register_opaque_programmer(&opaque_programmer_ich_hwseq); + } else { + register_spi_programmer(&spi_programmer_ich9); } - register_spi_programmer(&spi_programmer_ich9); - ich_init_opcodes(); break; } From stefan.tauner at student.tuwien.ac.at Tue Nov 8 11:59:29 2011 From: stefan.tauner at student.tuwien.ac.at (Stefan Tauner) Date: Tue, 8 Nov 2011 11:59:29 +0100 Subject: [flashrom] [PATCH 2/2] ichspi: add support for Intel Hardware Sequencing In-Reply-To: <4EB8722D.6010605@gmx.net> References: <1319636118-15878-1-git-send-email-stefan.tauner@student.tuwien.ac.at> <1319636118-15878-3-git-send-email-stefan.tauner@student.tuwien.ac.at> <4EB71529.1020005@gmx.net> <201111072251.pA7MpkJN019593@mail2.student.tuwien.ac.at> <4EB8722D.6010605@gmx.net> Message-ID: <201111081059.pA8AxG1Z007265@mail2.student.tuwien.ac.at> On Tue, 08 Nov 2011 01:05:01 +0100 Carl-Daniel Hailfinger wrote: > > while (ops[i] != 0) { > > - msg_pspew("checking for opcode 0x%02x\n", ops[i]); > > if (find_opcode(curopcodes, ops[i]) == -1) > > - return 0; > > + return ops[i]; > > Can you return 1 (or -1 or some other nonzero value) instead? Returning > one missing opcode reduces redability and provides no gain (other > missing opcodes are ignored). Unless I'm mistaken, we'll see the > available opcodes anyway in the verbose log. IF there is a verbose log, you are right (the error mentioning the missing opcode was msg_pinfo iirc). if not and flashrom bricks the computer we wont get far without a verbose log anyway :) i have also renamed the function as discussed on IRC. > Acked-by: Carl-Daniel Hailfinger \o/ eventually committed in r1461. there might be some things in the commit that you frowned upon before, but my reply to your mails remained unanswered. one example is mixing hex with decimal output in error messages. -- Kind regards/Mit freundlichen Gr??en, Stefan Tauner From svn at flashrom.org Tue Nov 8 12:55:25 2011 From: svn at flashrom.org (repository service) Date: Tue, 08 Nov 2011 12:55:25 +0100 Subject: [flashrom] [commit] r1462 - trunk Message-ID: Author: stefanct Date: Tue Nov 8 12:55:24 2011 New Revision: 1462 URL: http://flashrom.org/trac/flashrom/changeset/1462 Log: ichspi: print flash descriptor dependent information only when it is valid Also, fix some coding style issues. Signed-off-by: Stefan Tauner Acked-by: Carl-Daniel Hailfinger Modified: trunk/ichspi.c Modified: trunk/ichspi.c ============================================================================== --- trunk/ichspi.c Tue Nov 8 11:55:54 2011 (r1461) +++ trunk/ichspi.c Tue Nov 8 12:55:24 2011 (r1462) @@ -1092,7 +1092,7 @@ (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)) { int i; msg_pspew("The data was:\n"); - for(i=0; i References: <1319150349-24326-1-git-send-email-stefan.tauner@student.tuwien.ac.at> <1319150349-24326-4-git-send-email-stefan.tauner@student.tuwien.ac.at> Message-ID: <201111081157.pA8Bv14D004353@mail2.student.tuwien.ac.at> On Fri, 21 Oct 2011 00:39:07 +0200 Stefan Tauner wrote: > Also, fix some coding style issues. > > Signed-off-by: Stefan Tauner > Acked-by: Carl-Daniel Hailfinger now that hwseq is merged the way is free for this. committed in r1462. -- Kind regards/Mit freundlichen Gr??en, Stefan Tauner From c-d.hailfinger.devel.2006 at gmx.net Tue Nov 8 23:06:52 2011 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Tue, 08 Nov 2011 23:06:52 +0100 Subject: [flashrom] [PATCH 2/2] ichspi: add support for Intel Hardware Sequencing In-Reply-To: <201111081059.pA8AxG1Z007265@mail2.student.tuwien.ac.at> References: <1319636118-15878-1-git-send-email-stefan.tauner@student.tuwien.ac.at> <1319636118-15878-3-git-send-email-stefan.tauner@student.tuwien.ac.at> <4EB71529.1020005@gmx.net> <201111072251.pA7MpkJN019593@mail2.student.tuwien.ac.at> <4EB8722D.6010605@gmx.net> <201111081059.pA8AxG1Z007265@mail2.student.tuwien.ac.at> Message-ID: <4EB9A7FC.8060005@gmx.net> Am 08.11.2011 11:59 schrieb Stefan Tauner: > On Tue, 08 Nov 2011 01:05:01 +0100 > Carl-Daniel Hailfinger wrote: > >> Acked-by: Carl-Daniel Hailfinger > \o/ > > eventually committed in r1461. Great, thank you for your persistence! > there might be some things in the commit that you frowned upon before, > but my reply to your mails remained unanswered. one example is mixing > hex with decimal output in error messages. Sorry, I tried to reply to all mails, but I seem to have missed quite a few. The code is now in, and any remaining issues can be handled afterwards. Regards, Carl-Daniel -- http://www.hailfinger.org/ From c-d.hailfinger.devel.2006 at gmx.net Wed Nov 9 01:16:58 2011 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Wed, 09 Nov 2011 01:16:58 +0100 Subject: [flashrom] [RFC] Add struct flashchip * everywhere In-Reply-To: <4EB31089.7000902@gmx.net> References: <4EB0BEB2.1040701@gmx.net> <201111021241.pA2CfGHH021689@mail2.student.tuwien.ac.at> <4EB31089.7000902@gmx.net> Message-ID: <4EB9C67A.50502@gmx.net> Am 03.11.2011 23:07 schrieb Carl-Daniel Hailfinger: > Am 02.11.2011 13:41 schrieb Stefan Tauner: > > another layer of redirection is - as always - also a > > possibility: introducing a new struct with pointers to the actual chip > > and the programmer to be used (and other information related to the > > actual situation/probing... e.g. access right ranges). but that's > > probably not needed (yet) and the splitting could be done later anyway > > if need be. OTOH if it is clear that there will be more information > > stuffed into struct flashchip, that is not really static and does not > > need to/should not reside in flashchips.c/struct flashchip, we may > > better discuss a separation now(?). > We have a big problem: There is almost no information in struct > flashchip which is constant in all cases. > The name, size and erase structures could be filled in automatically for > SFDP stuff. That alone kills the separation idea IMHO. Turns out separating struct flashchip and struct flashctx (the flash context) is possible, but it required some sed and manual care. The only difference between struct flashchip and struct flashctx right now are the virtual_memory and virtual_registers members. Compared to my earlier patch, no function signatures have been changed except for flashchip->flashctx replacements. This should make reviews easier. TODO: Test if flashing still works on hardware (I tested with dummy). Test if printing and wiki printing still works as expected. Maybe-TODO: Check if it makes sense to convert some function signatures to use constant. Deferred to another patch: Adding struct flashctx to the remaining function signatures. If you want to verify this patch, run the following command in an unmodified tree: sed -i "s/struct flashchip/struct flashctx/g" *.[ch] and then compare the result to this patch. A few places like print.c and print_wiki.c kept struct flashchip because they don't care about the context and act directly on the flashchips array. Signed-off-by: Carl-Daniel Hailfinger Index: flashrom-struct_flashctx/flash.h =================================================================== --- flashrom-struct_flashctx/flash.h (Revision 1462) +++ flashrom-struct_flashctx/flash.h (Arbeitskopie) @@ -93,6 +93,8 @@ #define FEATURE_WRSR_WREN (1 << 7) #define FEATURE_WRSR_EITHER (FEATURE_WRSR_EWSR | FEATURE_WRSR_WREN) +struct flashctx; + struct flashchip { const char *vendor; const char *name; @@ -119,7 +121,7 @@ */ uint32_t tested; - int (*probe) (struct flashchip *flash); + int (*probe) (struct flashctx *flash); /* Delay after "enter/exit ID mode" commands in microseconds. */ int probe_timing; @@ -138,20 +140,42 @@ } eraseblocks[NUM_ERASEREGIONS]; /* a block_erase function should try to erase one block of size * 'blocklen' at address 'blockaddr' and return 0 on success. */ - int (*block_erase) (struct flashchip *flash, unsigned int blockaddr, unsigned int blocklen); + int (*block_erase) (struct flashctx *flash, unsigned int blockaddr, unsigned int blocklen); } block_erasers[NUM_ERASEFUNCTIONS]; - int (*printlock) (struct flashchip *flash); - int (*unlock) (struct flashchip *flash); - int (*write) (struct flashchip *flash, uint8_t *buf, int start, int len); - int (*read) (struct flashchip *flash, uint8_t *buf, int start, int len); - struct { + int (*printlock) (struct flashctx *flash); + int (*unlock) (struct flashctx *flash); + int (*write) (struct flashctx *flash, uint8_t *buf, int start, int len); + int (*read) (struct flashctx *flash, uint8_t *buf, int start, int len); + struct voltage { uint16_t min; uint16_t max; } voltage; +}; +/* struct flashctx must always contain struct flashchip at the beginning. */ +struct flashctx { + const char *vendor; + const char *name; + enum chipbustype bustype; + uint32_t manufacture_id; + uint32_t model_id; + int total_size; + int page_size; + int feature_bits; + uint32_t tested; + int (*probe) (struct flashctx *flash); + int probe_timing; + struct block_eraser block_erasers[NUM_ERASEFUNCTIONS]; + int (*printlock) (struct flashctx *flash); + int (*unlock) (struct flashctx *flash); + int (*write) (struct flashctx *flash, uint8_t *buf, int start, int len); + int (*read) (struct flashctx *flash, uint8_t *buf, int start, int len); + struct voltage voltage; + /* struct flashchip ends here. */ + + chipaddr virtual_memory; /* Some flash devices have an additional register space. */ - chipaddr virtual_memory; chipaddr virtual_registers; }; @@ -201,23 +225,23 @@ extern int verbose; extern const char flashrom_version[]; extern char *chip_to_probe; -void map_flash_registers(struct flashchip *flash); -int read_memmapped(struct flashchip *flash, uint8_t *buf, int start, int len); -int erase_flash(struct flashchip *flash); -int probe_flash(int startchip, struct flashchip *fill_flash, int force); -int read_flash_to_file(struct flashchip *flash, const char *filename); +void map_flash_registers(struct flashctx *flash); +int read_memmapped(struct flashctx *flash, uint8_t *buf, int start, int len); +int erase_flash(struct flashctx *flash); +int probe_flash(int startchip, struct flashctx *fill_flash, int force); +int read_flash_to_file(struct flashctx *flash, const char *filename); int min(int a, int b); int max(int a, int b); void tolower_string(char *str); char *extract_param(char **haystack, const char *needle, const char *delim); -int verify_range(struct flashchip *flash, uint8_t *cmpbuf, int start, int len, const char *message); +int verify_range(struct flashctx *flash, uint8_t *cmpbuf, int start, int len, const char *message); int need_erase(uint8_t *have, uint8_t *want, int len, enum write_granularity gran); char *strcat_realloc(char *dest, const char *src); void print_version(void); void print_banner(void); void list_programmers_linebreak(int startcol, int cols, int paren); int selfcheck(void); -int doit(struct flashchip *flash, int force, const char *filename, int read_it, int write_it, int erase_it, int verify_it); +int doit(struct flashctx *flash, int force, const char *filename, int read_it, int write_it, int erase_it, int verify_it); int read_buf_from_file(unsigned char *buf, unsigned long size, const char *filename); int write_buf_to_file(unsigned char *buf, unsigned long size, const char *filename); @@ -257,7 +281,7 @@ /* layout.c */ int read_romlayout(char *name); int find_romentry(char *name); -int handle_romentries(struct flashchip *flash, uint8_t *oldcontents, uint8_t *newcontents); +int handle_romentries(struct flashctx *flash, uint8_t *oldcontents, uint8_t *newcontents); /* spi.c */ struct spi_command { Index: flashrom-struct_flashctx/it87spi.c =================================================================== --- flashrom-struct_flashctx/it87spi.c (Revision 1462) +++ flashrom-struct_flashctx/it87spi.c (Arbeitskopie) @@ -105,9 +105,9 @@ static int it8716f_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); -static int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf, +static int it8716f_spi_chip_read(struct flashctx *flash, uint8_t *buf, int start, int len); -static int it8716f_spi_chip_write_256(struct flashchip *flash, uint8_t *buf, +static int it8716f_spi_chip_write_256(struct flashctx *flash, uint8_t *buf, int start, int len); static const struct spi_programmer spi_programmer_it87xx = { @@ -312,7 +312,7 @@ } /* Page size is usually 256 bytes */ -static int it8716f_spi_page_program(struct flashchip *flash, uint8_t *buf, +static int it8716f_spi_page_program(struct flashctx *flash, uint8_t *buf, int start) { int i, result; @@ -339,7 +339,7 @@ * IT8716F only allows maximum of 512 kb SPI mapped to LPC memory cycles * Need to read this big flash using firmware cycles 3 byte at a time. */ -static int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf, +static int it8716f_spi_chip_read(struct flashctx *flash, uint8_t *buf, int start, int len) { fast_spi = 0; @@ -357,7 +357,7 @@ return 0; } -static int it8716f_spi_chip_write_256(struct flashchip *flash, uint8_t *buf, +static int it8716f_spi_chip_write_256(struct flashctx *flash, uint8_t *buf, int start, int len) { /* Index: flashrom-struct_flashctx/jedec.c =================================================================== --- flashrom-struct_flashctx/jedec.c (Revision 1462) +++ flashrom-struct_flashctx/jedec.c (Arbeitskopie) @@ -91,7 +91,7 @@ msg_cdbg("%s: excessive loops, i=0x%x\n", __func__, i); } -static int getaddrmask(struct flashchip *flash) +static int getaddrmask(struct flashctx *flash) { switch (flash->feature_bits & FEATURE_ADDR_MASK) { case FEATURE_ADDR_FULL: @@ -110,7 +110,7 @@ } } -static void start_program_jedec_common(struct flashchip *flash, unsigned int mask) +static void start_program_jedec_common(struct flashctx *flash, unsigned int mask) { chipaddr bios = flash->virtual_memory; chip_writeb(0xAA, bios + (0x5555 & mask)); @@ -118,7 +118,7 @@ chip_writeb(0xA0, bios + (0x5555 & mask)); } -static int probe_jedec_common(struct flashchip *flash, unsigned int mask) +static int probe_jedec_common(struct flashctx *flash, unsigned int mask) { chipaddr bios = flash->virtual_memory; uint8_t id1, id2; @@ -237,7 +237,7 @@ return 1; } -static int erase_sector_jedec_common(struct flashchip *flash, unsigned int page, +static int erase_sector_jedec_common(struct flashctx *flash, unsigned int page, unsigned int pagesize, unsigned int mask) { chipaddr bios = flash->virtual_memory; @@ -267,7 +267,7 @@ return 0; } -static int erase_block_jedec_common(struct flashchip *flash, unsigned int block, +static int erase_block_jedec_common(struct flashctx *flash, unsigned int block, unsigned int blocksize, unsigned int mask) { chipaddr bios = flash->virtual_memory; @@ -297,7 +297,7 @@ return 0; } -static int erase_chip_jedec_common(struct flashchip *flash, unsigned int mask) +static int erase_chip_jedec_common(struct flashctx *flash, unsigned int mask) { chipaddr bios = flash->virtual_memory; int delay_us = 0; @@ -325,7 +325,7 @@ return 0; } -static int write_byte_program_jedec_common(struct flashchip *flash, uint8_t *src, +static int write_byte_program_jedec_common(struct flashctx *flash, uint8_t *src, chipaddr dst, unsigned int mask) { int tried = 0, failed = 0; @@ -355,7 +355,7 @@ } /* chunksize is 1 */ -int write_jedec_1(struct flashchip *flash, uint8_t *src, int start, int len) +int write_jedec_1(struct flashctx *flash, uint8_t *src, int start, int len) { int i, failed = 0; chipaddr dst = flash->virtual_memory + start; @@ -376,7 +376,7 @@ return failed; } -int write_page_write_jedec_common(struct flashchip *flash, uint8_t *src, int start, int page_size) +int write_page_write_jedec_common(struct flashctx *flash, uint8_t *src, int start, int page_size) { int i, tried = 0, failed; uint8_t *s = src; @@ -424,11 +424,11 @@ * This function is a slightly modified copy of spi_write_chunked. * Each page is written separately in chunks with a maximum size of chunksize. */ -int write_jedec(struct flashchip *flash, uint8_t *buf, int start, int len) +int write_jedec(struct flashctx *flash, uint8_t *buf, int start, int len) { int i, starthere, lenhere; /* FIXME: page_size is the wrong variable. We need max_writechunk_size - * in struct flashchip to do this properly. All chips using + * in struct flashctx to do this properly. All chips using * write_jedec have page_size set to max_writechunk_size, so * we're OK for now. */ @@ -458,7 +458,7 @@ } /* erase chip with block_erase() prototype */ -int erase_chip_block_jedec(struct flashchip *flash, unsigned int addr, +int erase_chip_block_jedec(struct flashctx *flash, unsigned int addr, unsigned int blocksize) { int mask; @@ -472,7 +472,7 @@ return erase_chip_jedec_common(flash, mask); } -int probe_jedec(struct flashchip *flash) +int probe_jedec(struct flashctx *flash) { int mask; @@ -480,7 +480,7 @@ return probe_jedec_common(flash, mask); } -int erase_sector_jedec(struct flashchip *flash, unsigned int page, unsigned int size) +int erase_sector_jedec(struct flashctx *flash, unsigned int page, unsigned int size) { int mask; @@ -488,7 +488,7 @@ return erase_sector_jedec_common(flash, page, size, mask); } -int erase_block_jedec(struct flashchip *flash, unsigned int page, unsigned int size) +int erase_block_jedec(struct flashctx *flash, unsigned int page, unsigned int size) { int mask; @@ -496,7 +496,7 @@ return erase_block_jedec_common(flash, page, size, mask); } -int erase_chip_jedec(struct flashchip *flash) +int erase_chip_jedec(struct flashctx *flash) { int mask; Index: flashrom-struct_flashctx/serprog.c =================================================================== --- flashrom-struct_flashctx/serprog.c (Revision 1462) +++ flashrom-struct_flashctx/serprog.c (Arbeitskopie) @@ -796,7 +796,7 @@ * the advantage that it is much faster for most chips, but breaks those with * non-contiguous address space (like AT45DB161D). When spi_read_chunked is * fixed this method can be removed. */ -int serprog_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) +int serprog_spi_read(struct flashctx *flash, uint8_t *buf, int start, int len) { int i; int cur_len; Index: flashrom-struct_flashctx/w39.c =================================================================== --- flashrom-struct_flashctx/w39.c (Revision 1462) +++ flashrom-struct_flashctx/w39.c (Arbeitskopie) @@ -21,7 +21,7 @@ #include "flash.h" -static int printlock_w39_fwh_block(struct flashchip *flash, int offset) +static int printlock_w39_fwh_block(struct flashctx *flash, int offset) { chipaddr wrprotect = flash->virtual_registers + offset + 2; uint8_t locking; @@ -59,7 +59,7 @@ return (locking & ((1 << 2) | (1 << 0))) ? -1 : 0; } -static int unlock_w39_fwh_block(struct flashchip *flash, int offset) +static int unlock_w39_fwh_block(struct flashctx *flash, int offset) { chipaddr wrprotect = flash->virtual_registers + offset + 2; uint8_t locking; @@ -80,7 +80,7 @@ return 0; } -static uint8_t w39_idmode_readb(struct flashchip *flash, int offset) +static uint8_t w39_idmode_readb(struct flashctx *flash, int offset) { chipaddr bios = flash->virtual_memory; uint8_t val; @@ -127,7 +127,7 @@ return 0; } -static int printlock_w39_common(struct flashchip *flash, int offset) +static int printlock_w39_common(struct flashctx *flash, int offset) { uint8_t lock; @@ -136,7 +136,7 @@ return printlock_w39_tblwp(lock); } -static int printlock_w39_fwh(struct flashchip *flash) +static int printlock_w39_fwh(struct flashctx *flash) { int i, total_size = flash->total_size * 1024; int ret = 0; @@ -148,7 +148,7 @@ return ret; } -static int unlock_w39_fwh(struct flashchip *flash) +static int unlock_w39_fwh(struct flashctx *flash) { int i, total_size = flash->total_size * 1024; @@ -160,7 +160,7 @@ return 0; } -int printlock_w39l040(struct flashchip * flash) +int printlock_w39l040(struct flashctx * flash) { uint8_t lock; int ret; @@ -176,7 +176,7 @@ return ret; } -int printlock_w39v040a(struct flashchip *flash) +int printlock_w39v040a(struct flashctx *flash) { uint8_t lock; int ret = 0; @@ -194,18 +194,18 @@ return ret; } -int printlock_w39v040b(struct flashchip *flash) +int printlock_w39v040b(struct flashctx *flash) { return printlock_w39_common(flash, 0x7fff2); } -int printlock_w39v040c(struct flashchip *flash) +int printlock_w39v040c(struct flashctx *flash) { /* Typo in the datasheet? The other chips use 0x7fff2. */ return printlock_w39_common(flash, 0xfff2); } -int printlock_w39v040fa(struct flashchip *flash) +int printlock_w39v040fa(struct flashctx *flash) { int ret = 0; @@ -215,7 +215,7 @@ return ret; } -int printlock_w39v040fb(struct flashchip *flash) +int printlock_w39v040fb(struct flashctx *flash) { int ret = 0; @@ -225,7 +225,7 @@ return ret; } -int printlock_w39v040fc(struct flashchip *flash) +int printlock_w39v040fc(struct flashctx *flash) { int ret = 0; @@ -236,12 +236,12 @@ return ret; } -int printlock_w39v080a(struct flashchip *flash) +int printlock_w39v080a(struct flashctx *flash) { return printlock_w39_common(flash, 0xffff2); } -int printlock_w39v080fa(struct flashchip *flash) +int printlock_w39v080fa(struct flashctx *flash) { int ret = 0; @@ -251,7 +251,7 @@ return ret; } -int printlock_w39v080fa_dual(struct flashchip *flash) +int printlock_w39v080fa_dual(struct flashctx *flash) { msg_cinfo("Block locking for W39V080FA in dual mode is " "undocumented.\n"); @@ -259,7 +259,7 @@ return -1; } -int unlock_w39v040fb(struct flashchip *flash) +int unlock_w39v040fb(struct flashctx *flash) { if (unlock_w39_fwh(flash)) return -1; @@ -269,7 +269,7 @@ return 0; } -int unlock_w39v080fa(struct flashchip *flash) +int unlock_w39v080fa(struct flashctx *flash) { if (unlock_w39_fwh(flash)) return -1; Index: flashrom-struct_flashctx/sst49lfxxxc.c =================================================================== --- flashrom-struct_flashctx/sst49lfxxxc.c (Revision 1462) +++ flashrom-struct_flashctx/sst49lfxxxc.c (Arbeitskopie) @@ -23,7 +23,7 @@ #include "flash.h" #include "chipdrivers.h" -static int write_lockbits_block_49lfxxxc(struct flashchip *flash, unsigned long address, unsigned char bits) +static int write_lockbits_block_49lfxxxc(struct flashctx *flash, unsigned long address, unsigned char bits) { unsigned long lock = flash->virtual_registers + address + 2; msg_cdbg("lockbits at address=0x%08lx is 0x%01x\n", lock, chip_readb(lock)); @@ -32,7 +32,7 @@ return 0; } -static int write_lockbits_49lfxxxc(struct flashchip *flash, unsigned char bits) +static int write_lockbits_49lfxxxc(struct flashctx *flash, unsigned char bits) { chipaddr registers = flash->virtual_registers; int i, left = flash->total_size * 1024; @@ -54,12 +54,12 @@ return 0; } -int unlock_49lfxxxc(struct flashchip *flash) +int unlock_49lfxxxc(struct flashctx *flash) { return write_lockbits_49lfxxxc(flash, 0); } -int erase_sector_49lfxxxc(struct flashchip *flash, unsigned int address, unsigned int sector_size) +int erase_sector_49lfxxxc(struct flashctx *flash, unsigned int address, unsigned int sector_size) { uint8_t status; chipaddr bios = flash->virtual_memory; Index: flashrom-struct_flashctx/sharplhf00l04.c =================================================================== --- flashrom-struct_flashctx/sharplhf00l04.c (Revision 1462) +++ flashrom-struct_flashctx/sharplhf00l04.c (Arbeitskopie) @@ -26,7 +26,7 @@ * FIXME: This file is unused. */ -int erase_lhf00l04_block(struct flashchip *flash, unsigned int blockaddr, unsigned int blocklen) +int erase_lhf00l04_block(struct flashctx *flash, unsigned int blockaddr, unsigned int blocklen) { chipaddr bios = flash->virtual_memory + blockaddr; chipaddr wrprotect = flash->virtual_registers + blockaddr + 2; Index: flashrom-struct_flashctx/a25.c =================================================================== --- flashrom-struct_flashctx/a25.c (Revision 1462) +++ flashrom-struct_flashctx/a25.c (Arbeitskopie) @@ -29,7 +29,7 @@ "(SRWD) is %sset\n", (status & (1 << 7)) ? "" : "not "); } -int spi_prettyprint_status_register_amic_a25l05p(struct flashchip *flash) +int spi_prettyprint_status_register_amic_a25l05p(struct flashctx *flash) { uint8_t status; @@ -45,7 +45,7 @@ return 0; } -int spi_prettyprint_status_register_amic_a25l40p(struct flashchip *flash) +int spi_prettyprint_status_register_amic_a25l40p(struct flashctx *flash) { uint8_t status; @@ -60,7 +60,7 @@ return 0; } -int spi_prettyprint_status_register_amic_a25l032(struct flashchip *flash) +int spi_prettyprint_status_register_amic_a25l032(struct flashctx *flash) { uint8_t status; @@ -78,7 +78,7 @@ return 0; } -int spi_prettyprint_status_register_amic_a25lq032(struct flashchip *flash) +int spi_prettyprint_status_register_amic_a25lq032(struct flashctx *flash) { uint8_t status; Index: flashrom-struct_flashctx/dummyflasher.c =================================================================== --- flashrom-struct_flashctx/dummyflasher.c (Revision 1462) +++ flashrom-struct_flashctx/dummyflasher.c (Arbeitskopie) @@ -62,7 +62,7 @@ static int dummy_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); -static int dummy_spi_write_256(struct flashchip *flash, uint8_t *buf, +static int dummy_spi_write_256(struct flashctx *flash, uint8_t *buf, int start, int len); static const struct spi_programmer spi_programmer_dummyflasher = { @@ -527,7 +527,7 @@ return 0; } -static int dummy_spi_write_256(struct flashchip *flash, uint8_t *buf, +static int dummy_spi_write_256(struct flashctx *flash, uint8_t *buf, int start, int len) { return spi_write_chunked(flash, buf, start, len, Index: flashrom-struct_flashctx/sst_fwhub.c =================================================================== --- flashrom-struct_flashctx/sst_fwhub.c (Revision 1462) +++ flashrom-struct_flashctx/sst_fwhub.c (Arbeitskopie) @@ -24,7 +24,7 @@ #include "flash.h" -static int check_sst_fwhub_block_lock(struct flashchip *flash, int offset) +static int check_sst_fwhub_block_lock(struct flashctx *flash, int offset) { chipaddr registers = flash->virtual_registers; uint8_t blockstatus; @@ -50,7 +50,7 @@ return blockstatus & 0x1; } -static int clear_sst_fwhub_block_lock(struct flashchip *flash, int offset) +static int clear_sst_fwhub_block_lock(struct flashctx *flash, int offset) { chipaddr registers = flash->virtual_registers; uint8_t blockstatus; @@ -68,7 +68,7 @@ return blockstatus; } -int printlock_sst_fwhub(struct flashchip *flash) +int printlock_sst_fwhub(struct flashctx *flash) { int i; @@ -78,7 +78,7 @@ return 0; } -int unlock_sst_fwhub(struct flashchip *flash) +int unlock_sst_fwhub(struct flashctx *flash) { int i, ret=0; Index: flashrom-struct_flashctx/cli_classic.c =================================================================== --- flashrom-struct_flashctx/cli_classic.c (Revision 1462) +++ flashrom-struct_flashctx/cli_classic.c (Arbeitskopie) @@ -169,8 +169,8 @@ unsigned long size; /* Probe for up to three flash chips. */ const struct flashchip *flash; - struct flashchip flashes[3]; - struct flashchip *fill_flash; + struct flashctx flashes[3]; + struct flashctx *fill_flash; const char *name; int namelen, opt, i; int startchip = 0, chipcount = 0, option_index = 0, force = 0; @@ -409,6 +409,7 @@ } #endif + /* Does a chip with the requested name exist in the flashchips array? */ if (chip_to_probe) { for (flash = flashchips; flash && flash->name; flash++) if (!strcmp(flash->name, chip_to_probe)) Index: flashrom-struct_flashctx/at25.c =================================================================== --- flashrom-struct_flashctx/at25.c (Revision 1462) +++ flashrom-struct_flashctx/at25.c (Arbeitskopie) @@ -57,7 +57,7 @@ } } -int spi_prettyprint_status_register_at25df(struct flashchip *flash) +int spi_prettyprint_status_register_at25df(struct flashctx *flash) { uint8_t status; @@ -72,7 +72,7 @@ return 0; } -int spi_prettyprint_status_register_at25df_sec(struct flashchip *flash) +int spi_prettyprint_status_register_at25df_sec(struct flashctx *flash) { /* FIXME: We should check the security lockdown. */ msg_cdbg("Ignoring security lockdown (if present)\n"); @@ -80,7 +80,7 @@ return spi_prettyprint_status_register_at25df(flash); } -int spi_prettyprint_status_register_at25f(struct flashchip *flash) +int spi_prettyprint_status_register_at25f(struct flashctx *flash) { uint8_t status; @@ -99,7 +99,7 @@ return 0; } -int spi_prettyprint_status_register_at25fs010(struct flashchip *flash) +int spi_prettyprint_status_register_at25fs010(struct flashctx *flash) { uint8_t status; @@ -123,7 +123,7 @@ return 0; } -int spi_prettyprint_status_register_at25fs040(struct flashchip *flash) +int spi_prettyprint_status_register_at25fs040(struct flashctx *flash) { uint8_t status; @@ -147,7 +147,7 @@ return 0; } -int spi_prettyprint_status_register_atmel_at26df081a(struct flashchip *flash) +int spi_prettyprint_status_register_atmel_at26df081a(struct flashctx *flash) { uint8_t status; @@ -163,7 +163,7 @@ return 0; } -int spi_disable_blockprotect_at25df(struct flashchip *flash) +int spi_disable_blockprotect_at25df(struct flashctx *flash) { uint8_t status; int result; @@ -203,14 +203,14 @@ return 0; } -int spi_disable_blockprotect_at25df_sec(struct flashchip *flash) +int spi_disable_blockprotect_at25df_sec(struct flashctx *flash) { /* FIXME: We should check the security lockdown. */ msg_cinfo("Ignoring security lockdown (if present)\n"); return spi_disable_blockprotect_at25df(flash); } -int spi_disable_blockprotect_at25f(struct flashchip *flash) +int spi_disable_blockprotect_at25f(struct flashctx *flash) { /* spi_disable_blockprotect_at25df is not really the right way to do * this, but the side effects of said function work here as well. @@ -218,7 +218,7 @@ return spi_disable_blockprotect_at25df(flash); } -int spi_disable_blockprotect_at25fs010(struct flashchip *flash) +int spi_disable_blockprotect_at25fs010(struct flashctx *flash) { uint8_t status; int result; @@ -252,7 +252,7 @@ return 0; } -int spi_disable_blockprotect_at25fs040(struct flashchip *flash) +int spi_disable_blockprotect_at25fs040(struct flashctx *flash) { uint8_t status; int result; Index: flashrom-struct_flashctx/layout.c =================================================================== --- flashrom-struct_flashctx/layout.c (Revision 1462) +++ flashrom-struct_flashctx/layout.c (Arbeitskopie) @@ -240,7 +240,7 @@ return best_entry; } -int handle_romentries(struct flashchip *flash, uint8_t *oldcontents, uint8_t *newcontents) +int handle_romentries(struct flashctx *flash, uint8_t *oldcontents, uint8_t *newcontents) { unsigned int start = 0; int entry; Index: flashrom-struct_flashctx/ichspi.c =================================================================== --- flashrom-struct_flashctx/ichspi.c (Revision 1462) +++ flashrom-struct_flashctx/ichspi.c (Arbeitskopie) @@ -1175,7 +1175,7 @@ return 0; } -int ich_hwseq_probe(struct flashchip *flash) +int ich_hwseq_probe(struct flashctx *flash) { uint32_t total_size, boundary; uint32_t erase_size_low, size_low, erase_size_high, size_high; @@ -1228,7 +1228,7 @@ return 1; } -int ich_hwseq_block_erase(struct flashchip *flash, +int ich_hwseq_block_erase(struct flashctx *flash, unsigned int addr, unsigned int len) { @@ -1278,7 +1278,7 @@ return 0; } -int ich_hwseq_read(struct flashchip *flash, uint8_t *buf, int addr, int len) +int ich_hwseq_read(struct flashctx *flash, uint8_t *buf, int addr, int len) { uint16_t hsfc; uint16_t timeout = 100 * 60; @@ -1315,7 +1315,7 @@ return 0; } -int ich_hwseq_write(struct flashchip *flash, uint8_t *buf, int addr, int len) +int ich_hwseq_write(struct flashctx *flash, uint8_t *buf, int addr, int len) { uint16_t hsfc; uint16_t timeout = 100 * 60; Index: flashrom-struct_flashctx/82802ab.c =================================================================== --- flashrom-struct_flashctx/82802ab.c (Revision 1462) +++ flashrom-struct_flashctx/82802ab.c (Arbeitskopie) @@ -40,7 +40,7 @@ msg_cdbg("%s", status & 0x2 ? "WP|TBL#|WP#,ABORT:" : "UNLOCK:"); } -int probe_82802ab(struct flashchip *flash) +int probe_82802ab(struct flashctx *flash) { chipaddr bios = flash->virtual_memory; uint8_t id1, id2, flashcontent1, flashcontent2; @@ -89,7 +89,7 @@ return 1; } -uint8_t wait_82802ab(struct flashchip *flash) +uint8_t wait_82802ab(struct flashctx *flash) { uint8_t status; chipaddr bios = flash->virtual_memory; @@ -107,7 +107,7 @@ return status; } -int unlock_82802ab(struct flashchip *flash) +int unlock_82802ab(struct flashctx *flash) { int i; //chipaddr wrprotect = flash->virtual_registers + page + 2; @@ -118,7 +118,7 @@ return 0; } -int erase_block_82802ab(struct flashchip *flash, unsigned int page, +int erase_block_82802ab(struct flashctx *flash, unsigned int page, unsigned int pagesize) { chipaddr bios = flash->virtual_memory; @@ -141,7 +141,7 @@ } /* chunksize is 1 */ -int write_82802ab(struct flashchip *flash, uint8_t *src, int start, int len) +int write_82802ab(struct flashctx *flash, uint8_t *src, int start, int len) { int i; chipaddr dst = flash->virtual_memory + start; @@ -157,7 +157,7 @@ return 0; } -int unlock_28f004s5(struct flashchip *flash) +int unlock_28f004s5(struct flashctx *flash) { chipaddr bios = flash->virtual_memory; uint8_t mcfg, bcfg, need_unlock = 0, can_unlock = 0; @@ -209,7 +209,7 @@ return 0; } -int unlock_lh28f008bjt(struct flashchip *flash) +int unlock_lh28f008bjt(struct flashctx *flash) { chipaddr bios = flash->virtual_memory; uint8_t mcfg, bcfg; Index: flashrom-struct_flashctx/opaque.c =================================================================== --- flashrom-struct_flashctx/opaque.c (Revision 1462) +++ flashrom-struct_flashctx/opaque.c (Arbeitskopie) @@ -41,7 +41,7 @@ const struct opaque_programmer *opaque_programmer = &opaque_programmer_none; -int probe_opaque(struct flashchip *flash) +int probe_opaque(struct flashctx *flash) { if (!opaque_programmer->probe) { msg_perr("%s called before register_opaque_programmer. " @@ -53,7 +53,7 @@ return opaque_programmer->probe(flash); } -int read_opaque(struct flashchip *flash, uint8_t *buf, int start, int len) +int read_opaque(struct flashctx *flash, uint8_t *buf, int start, int len) { if (!opaque_programmer->read) { msg_perr("%s called before register_opaque_programmer. " @@ -64,7 +64,7 @@ return opaque_programmer->read(flash, buf, start, len); } -int write_opaque(struct flashchip *flash, uint8_t *buf, int start, int len) +int write_opaque(struct flashctx *flash, uint8_t *buf, int start, int len) { if (!opaque_programmer->write) { msg_perr("%s called before register_opaque_programmer. " @@ -75,7 +75,7 @@ return opaque_programmer->write(flash, buf, start, len); } -int erase_opaque(struct flashchip *flash, unsigned int blockaddr, unsigned int blocklen) +int erase_opaque(struct flashctx *flash, unsigned int blockaddr, unsigned int blocklen) { if (!opaque_programmer->erase) { msg_perr("%s called before register_opaque_programmer. " Index: flashrom-struct_flashctx/dediprog.c =================================================================== --- flashrom-struct_flashctx/dediprog.c (Revision 1462) +++ flashrom-struct_flashctx/dediprog.c (Arbeitskopie) @@ -205,7 +205,7 @@ * @len length * @return 0 on success, 1 on failure */ -static int dediprog_spi_bulk_read(struct flashchip *flash, uint8_t *buf, +static int dediprog_spi_bulk_read(struct flashctx *flash, uint8_t *buf, int start, int len) { int ret; @@ -253,7 +253,7 @@ return 0; } -static int dediprog_spi_read(struct flashchip *flash, uint8_t *buf, int start, +static int dediprog_spi_read(struct flashctx *flash, uint8_t *buf, int start, int len) { int ret; @@ -299,7 +299,7 @@ return 0; } -static int dediprog_spi_write_256(struct flashchip *flash, uint8_t *buf, +static int dediprog_spi_write_256(struct flashctx *flash, uint8_t *buf, int start, int len) { int ret; Index: flashrom-struct_flashctx/spi25.c =================================================================== --- flashrom-struct_flashctx/spi25.c (Revision 1462) +++ flashrom-struct_flashctx/spi25.c (Arbeitskopie) @@ -113,7 +113,7 @@ return spi_send_command(sizeof(cmd), 0, cmd, NULL); } -static int probe_spi_rdid_generic(struct flashchip *flash, int bytes) +static int probe_spi_rdid_generic(struct flashctx *flash, int bytes) { unsigned char readarr[4]; uint32_t id1; @@ -167,12 +167,12 @@ return 0; } -int probe_spi_rdid(struct flashchip *flash) +int probe_spi_rdid(struct flashctx *flash) { return probe_spi_rdid_generic(flash, 3); } -int probe_spi_rdid4(struct flashchip *flash) +int probe_spi_rdid4(struct flashctx *flash) { /* Some SPI controllers do not support commands with writecnt=1 and * readcnt=4. @@ -194,7 +194,7 @@ return 0; } -int probe_spi_rems(struct flashchip *flash) +int probe_spi_rems(struct flashctx *flash) { unsigned char readarr[JEDEC_REMS_INSIZE]; uint32_t id1, id2; @@ -230,7 +230,7 @@ return 0; } -int probe_spi_res1(struct flashchip *flash) +int probe_spi_res1(struct flashctx *flash) { static const unsigned char allff[] = {0xff, 0xff, 0xff}; static const unsigned char all00[] = {0x00, 0x00, 0x00}; @@ -274,7 +274,7 @@ return 1; } -int probe_spi_res2(struct flashchip *flash) +int probe_spi_res2(struct flashctx *flash) { unsigned char readarr[2]; uint32_t id1, id2; @@ -410,7 +410,7 @@ bpt[(status & 0x1c) >> 2]); } -int spi_prettyprint_status_register(struct flashchip *flash) +int spi_prettyprint_status_register(struct flashctx *flash) { uint8_t status; @@ -444,7 +444,7 @@ return 0; } -int spi_chip_erase_60(struct flashchip *flash) +int spi_chip_erase_60(struct flashctx *flash) { int result; struct spi_command cmds[] = { @@ -481,7 +481,7 @@ return 0; } -int spi_chip_erase_c7(struct flashchip *flash) +int spi_chip_erase_c7(struct flashctx *flash) { int result; struct spi_command cmds[] = { @@ -517,7 +517,7 @@ return 0; } -int spi_block_erase_52(struct flashchip *flash, unsigned int addr, unsigned int blocklen) +int spi_block_erase_52(struct flashctx *flash, unsigned int addr, unsigned int blocklen) { int result; struct spi_command cmds[] = { @@ -563,7 +563,7 @@ * 32k for SST * 4-32k non-uniform for EON */ -int spi_block_erase_d8(struct flashchip *flash, unsigned int addr, unsigned int blocklen) +int spi_block_erase_d8(struct flashctx *flash, unsigned int addr, unsigned int blocklen) { int result; struct spi_command cmds[] = { @@ -607,7 +607,7 @@ /* Block size is usually * 4k for PMC */ -int spi_block_erase_d7(struct flashchip *flash, unsigned int addr, unsigned int blocklen) +int spi_block_erase_d7(struct flashctx *flash, unsigned int addr, unsigned int blocklen) { int result; struct spi_command cmds[] = { @@ -649,7 +649,7 @@ } /* Sector size is usually 4k, though Macronix eliteflash has 64k */ -int spi_block_erase_20(struct flashchip *flash, unsigned int addr, unsigned int blocklen) +int spi_block_erase_20(struct flashctx *flash, unsigned int addr, unsigned int blocklen) { int result; struct spi_command cmds[] = { @@ -690,7 +690,7 @@ return 0; } -int spi_block_erase_60(struct flashchip *flash, unsigned int addr, unsigned int blocklen) +int spi_block_erase_60(struct flashctx *flash, unsigned int addr, unsigned int blocklen) { if ((addr != 0) || (blocklen != flash->total_size * 1024)) { msg_cerr("%s called with incorrect arguments\n", @@ -700,7 +700,7 @@ return spi_chip_erase_60(flash); } -int spi_block_erase_c7(struct flashchip *flash, unsigned int addr, unsigned int blocklen) +int spi_block_erase_c7(struct flashctx *flash, unsigned int addr, unsigned int blocklen) { if ((addr != 0) || (blocklen != flash->total_size * 1024)) { msg_cerr("%s called with incorrect arguments\n", @@ -728,7 +728,7 @@ * This is according the SST25VF016 datasheet, who knows it is more * generic that this... */ -static int spi_write_status_register_ewsr(struct flashchip *flash, int status) +static int spi_write_status_register_ewsr(struct flashctx *flash, int status) { int result; int i = 0; @@ -776,7 +776,7 @@ return 0; } -static int spi_write_status_register_wren(struct flashchip *flash, int status) +static int spi_write_status_register_wren(struct flashctx *flash, int status) { int result; int i = 0; @@ -824,7 +824,7 @@ return 0; } -int spi_write_status_register(struct flashchip *flash, int status) +int spi_write_status_register(struct flashctx *flash, int status) { int ret = 1; @@ -926,7 +926,7 @@ * Write 0x00 to the status register. Check if any locks are still set (that * part is chip specific). Repeat once. */ -int spi_disable_blockprotect(struct flashchip *flash) +int spi_disable_blockprotect(struct flashctx *flash) { uint8_t status; int result; @@ -968,7 +968,7 @@ * FIXME: Use the chunk code from Michael Karcher instead. * Each page is read separately in chunks with a maximum size of chunksize. */ -int spi_read_chunked(struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize) +int spi_read_chunked(struct flashctx *flash, uint8_t *buf, int start, int len, int chunksize) { int rc = 0; int i, j, starthere, lenhere; @@ -1008,12 +1008,12 @@ * FIXME: Use the chunk code from Michael Karcher instead. * Each page is written separately in chunks with a maximum size of chunksize. */ -int spi_write_chunked(struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize) +int spi_write_chunked(struct flashctx *flash, uint8_t *buf, int start, int len, int chunksize) { int rc = 0; int i, j, starthere, lenhere; /* FIXME: page_size is the wrong variable. We need max_writechunk_size - * in struct flashchip to do this properly. All chips using + * in struct flashctx to do this properly. All chips using * spi_chip_write_256 have page_size set to max_writechunk_size, so * we're OK for now. */ @@ -1057,7 +1057,7 @@ * (e.g. due to size constraints in IT87* for over 512 kB) */ /* real chunksize is 1, logical chunksize is 1 */ -int spi_chip_write_1(struct flashchip *flash, uint8_t *buf, int start, int len) +int spi_chip_write_1(struct flashctx *flash, uint8_t *buf, int start, int len) { int i, result = 0; @@ -1072,7 +1072,7 @@ return 0; } -int spi_aai_write(struct flashchip *flash, uint8_t *buf, int start, int len) +int spi_aai_write(struct flashctx *flash, uint8_t *buf, int start, int len) { uint32_t pos = start; int result; Index: flashrom-struct_flashctx/pm49fl00x.c =================================================================== --- flashrom-struct_flashctx/pm49fl00x.c (Revision 1462) +++ flashrom-struct_flashctx/pm49fl00x.c (Arbeitskopie) @@ -36,13 +36,13 @@ } } -int unlock_49fl00x(struct flashchip *flash) +int unlock_49fl00x(struct flashctx *flash) { write_lockbits_49fl00x(flash->virtual_registers, flash->total_size * 1024, 0, flash->page_size); return 0; } -int lock_49fl00x(struct flashchip *flash) +int lock_49fl00x(struct flashctx *flash) { write_lockbits_49fl00x(flash->virtual_registers, flash->total_size * 1024, 1, flash->page_size); return 0; Index: flashrom-struct_flashctx/linux_spi.c =================================================================== --- flashrom-struct_flashctx/linux_spi.c (Revision 1462) +++ flashrom-struct_flashctx/linux_spi.c (Arbeitskopie) @@ -36,9 +36,9 @@ static int linux_spi_shutdown(void *data); static int linux_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *txbuf, unsigned char *rxbuf); -static int linux_spi_read(struct flashchip *flash, uint8_t *buf, int start, +static int linux_spi_read(struct flashctx *flash, uint8_t *buf, int start, int len); -static int linux_spi_write_256(struct flashchip *flash, uint8_t *buf, +static int linux_spi_write_256(struct flashctx *flash, uint8_t *buf, int start, int len); static const struct spi_programmer spi_programmer_linux = { @@ -131,13 +131,13 @@ return 0; } -static int linux_spi_read(struct flashchip *flash, uint8_t *buf, int start, +static int linux_spi_read(struct flashctx *flash, uint8_t *buf, int start, int len) { return spi_read_chunked(flash, buf, start, len, getpagesize()); } -static int linux_spi_write_256(struct flashchip *flash, uint8_t *buf, +static int linux_spi_write_256(struct flashctx *flash, uint8_t *buf, int start, int len) { return spi_write_chunked(flash, buf, start, len, getpagesize() - 4); Index: flashrom-struct_flashctx/w29ee011.c =================================================================== --- flashrom-struct_flashctx/w29ee011.c (Revision 1462) +++ flashrom-struct_flashctx/w29ee011.c (Arbeitskopie) @@ -24,7 +24,7 @@ /* According to the Winbond W29EE011, W29EE012, W29C010M, W29C011A * datasheets this is the only valid probe function for those chips. */ -int probe_w29ee011(struct flashchip *flash) +int probe_w29ee011(struct flashctx *flash) { chipaddr bios = flash->virtual_memory; uint8_t id1, id2; Index: flashrom-struct_flashctx/spi.c =================================================================== --- flashrom-struct_flashctx/spi.c (Revision 1462) +++ flashrom-struct_flashctx/spi.c (Arbeitskopie) @@ -97,7 +97,7 @@ return result; } -int default_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) +int default_spi_read(struct flashctx *flash, uint8_t *buf, int start, int len) { int max_data = spi_programmer->max_data_read; if (max_data == MAX_DATA_UNSPECIFIED) { @@ -109,7 +109,7 @@ return spi_read_chunked(flash, buf, start, len, max_data); } -int default_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) +int default_spi_write_256(struct flashctx *flash, uint8_t *buf, int start, int len) { int max_data = spi_programmer->max_data_write; if (max_data == MAX_DATA_UNSPECIFIED) { @@ -121,7 +121,7 @@ return spi_write_chunked(flash, buf, start, len, max_data); } -int spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len) +int spi_chip_read(struct flashctx *flash, uint8_t *buf, int start, int len) { int addrbase = 0; if (!spi_programmer->read) { @@ -160,7 +160,7 @@ * .write_256 = spi_chip_write_1 */ /* real chunksize is up to 256, logical chunksize is 256 */ -int spi_chip_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) +int spi_chip_write_256(struct flashctx *flash, uint8_t *buf, int start, int len) { if (!spi_programmer->write_256) { msg_perr("%s called, but SPI page write is unsupported on this " Index: flashrom-struct_flashctx/wbsio_spi.c =================================================================== --- flashrom-struct_flashctx/wbsio_spi.c (Revision 1462) +++ flashrom-struct_flashctx/wbsio_spi.c (Arbeitskopie) @@ -62,7 +62,7 @@ static int wbsio_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); -static int wbsio_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); +static int wbsio_spi_read(struct flashctx *flash, uint8_t *buf, int start, int len); static const struct spi_programmer spi_programmer_wbsio = { .type = SPI_CONTROLLER_WBSIO, @@ -194,7 +194,7 @@ return 0; } -static int wbsio_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) +static int wbsio_spi_read(struct flashctx *flash, uint8_t *buf, int start, int len) { return read_memmapped(flash, buf, start, len); } Index: flashrom-struct_flashctx/sst28sf040.c =================================================================== --- flashrom-struct_flashctx/sst28sf040.c (Revision 1462) +++ flashrom-struct_flashctx/sst28sf040.c (Arbeitskopie) @@ -30,7 +30,7 @@ #define RESET 0xFF #define READ_ID 0x90 -int protect_28sf040(struct flashchip *flash) +int protect_28sf040(struct flashctx *flash) { chipaddr bios = flash->virtual_memory; @@ -45,7 +45,7 @@ return 0; } -int unprotect_28sf040(struct flashchip *flash) +int unprotect_28sf040(struct flashctx *flash) { chipaddr bios = flash->virtual_memory; @@ -60,7 +60,7 @@ return 0; } -int erase_sector_28sf040(struct flashchip *flash, unsigned int address, unsigned int sector_size) +int erase_sector_28sf040(struct flashctx *flash, unsigned int address, unsigned int sector_size) { chipaddr bios = flash->virtual_memory; @@ -76,7 +76,7 @@ } /* chunksize is 1 */ -int write_28sf040(struct flashchip *flash, uint8_t *src, int start, int len) +int write_28sf040(struct flashctx *flash, uint8_t *src, int start, int len) { int i; chipaddr bios = flash->virtual_memory; @@ -100,7 +100,7 @@ return 0; } -static int erase_28sf040(struct flashchip *flash) +static int erase_28sf040(struct flashctx *flash) { chipaddr bios = flash->virtual_memory; @@ -114,7 +114,7 @@ return 0; } -int erase_chip_28sf040(struct flashchip *flash, unsigned int addr, unsigned int blocklen) +int erase_chip_28sf040(struct flashctx *flash, unsigned int addr, unsigned int blocklen) { if ((addr != 0) || (blocklen != flash->total_size * 1024)) { msg_cerr("%s called with incorrect arguments\n", Index: flashrom-struct_flashctx/stm50flw0x0x.c =================================================================== --- flashrom-struct_flashctx/stm50flw0x0x.c (Revision 1462) +++ flashrom-struct_flashctx/stm50flw0x0x.c (Arbeitskopie) @@ -36,7 +36,7 @@ * The ST M50FLW080B and STM50FLW080B chips have to be unlocked, * before you can erase them or write to them. */ -static int unlock_block_stm50flw0x0x(struct flashchip *flash, int offset) +static int unlock_block_stm50flw0x0x(struct flashctx *flash, int offset) { chipaddr wrprotect = flash->virtual_registers + 2; static const uint8_t unlock_sector = 0x00; @@ -79,7 +79,7 @@ return 0; } -int unlock_stm50flw0x0x(struct flashchip *flash) +int unlock_stm50flw0x0x(struct flashctx *flash) { int i; @@ -94,7 +94,7 @@ } /* This function is unused. */ -int erase_sector_stm50flw0x0x(struct flashchip *flash, unsigned int sector, unsigned int sectorsize) +int erase_sector_stm50flw0x0x(struct flashctx *flash, unsigned int sector, unsigned int sectorsize) { chipaddr bios = flash->virtual_memory + sector; Index: flashrom-struct_flashctx/flashrom.c =================================================================== --- flashrom-struct_flashctx/flashrom.c (Revision 1462) +++ flashrom-struct_flashctx/flashrom.c (Arbeitskopie) @@ -420,7 +420,7 @@ */ static int may_register_shutdown = 0; -static int check_block_eraser(const struct flashchip *flash, int k, int log); +static int check_block_eraser(const struct flashctx *flash, int k, int log); /* Register a function to be executed on programmer shutdown. * The advantage over atexit() is that you can supply a void pointer which will @@ -556,7 +556,7 @@ programmer_table[programmer].delay(usecs); } -void map_flash_registers(struct flashchip *flash) +void map_flash_registers(struct flashctx *flash) { size_t size = flash->total_size * 1024; /* Flash registers live 4 MByte below the flash. */ @@ -564,7 +564,7 @@ flash->virtual_registers = (chipaddr)programmer_map_flash_region("flash chip registers", (0xFFFFFFFF - 0x400000 - size + 1), size); } -int read_memmapped(struct flashchip *flash, uint8_t *buf, int start, int len) +int read_memmapped(struct flashctx *flash, uint8_t *buf, int start, int len) { chip_readn(buf, flash->virtual_memory + start, len); @@ -675,7 +675,7 @@ } /* Returns the number of well-defined erasers for a chip. */ -static unsigned int count_usable_erasers(const struct flashchip *flash) +static unsigned int count_usable_erasers(const struct flashctx *flash) { unsigned int usable_erasefunctions = 0; int k; @@ -687,7 +687,7 @@ } /* start is an offset to the base address of the flash chip */ -int check_erased_range(struct flashchip *flash, int start, int len) +int check_erased_range(struct flashctx *flash, int start, int len) { int ret; uint8_t *cmpbuf = malloc(len); @@ -710,7 +710,7 @@ * @message string to print in the "FAILED" message * @return 0 for success, -1 for failure */ -int verify_range(struct flashchip *flash, uint8_t *cmpbuf, int start, int len, +int verify_range(struct flashctx *flash, uint8_t *cmpbuf, int start, int len, const char *message) { int i; @@ -1088,7 +1088,7 @@ return 1; } -int probe_flash(int startchip, struct flashchip *fill_flash, int force) +int probe_flash(int startchip, struct flashctx *fill_flash, int force) { const struct flashchip *flash; unsigned long base = 0; @@ -1126,7 +1126,7 @@ check_max_decode(buses_common, size); /* Start filling in the dynamic data. */ - *fill_flash = *flash; + memcpy(fill_flash, flash, sizeof(struct flashchip)); base = flashbase ? flashbase : (0xffffffff - size + 1); fill_flash->virtual_memory = (chipaddr)programmer_map_flash_region("flash chip", base, size); @@ -1179,7 +1179,7 @@ return flash - flashchips; } -int verify_flash(struct flashchip *flash, uint8_t *buf) +int verify_flash(struct flashctx *flash, uint8_t *buf) { int ret; int total_size = flash->total_size * 1024; @@ -1253,7 +1253,7 @@ return 0; } -int read_flash_to_file(struct flashchip *flash, const char *filename) +int read_flash_to_file(struct flashctx *flash, const char *filename) { unsigned long size = flash->total_size * 1024; unsigned char *buf = calloc(size, sizeof(char)); @@ -1352,11 +1352,11 @@ return ret; } -static int erase_and_write_block_helper(struct flashchip *flash, +static int erase_and_write_block_helper(struct flashctx *flash, unsigned int start, unsigned int len, uint8_t *curcontents, uint8_t *newcontents, - int (*erasefn) (struct flashchip *flash, + int (*erasefn) (struct flashctx *flash, unsigned int addr, unsigned int len)) { @@ -1402,14 +1402,14 @@ return ret; } -static int walk_eraseregions(struct flashchip *flash, int erasefunction, - int (*do_something) (struct flashchip *flash, +static int walk_eraseregions(struct flashctx *flash, int erasefunction, + int (*do_something) (struct flashctx *flash, unsigned int addr, unsigned int len, uint8_t *param1, uint8_t *param2, int (*erasefn) ( - struct flashchip *flash, + struct flashctx *flash, unsigned int addr, unsigned int len)), void *param1, void *param2) @@ -1441,7 +1441,7 @@ return 0; } -static int check_block_eraser(const struct flashchip *flash, int k, int log) +static int check_block_eraser(const struct flashctx *flash, int k, int log) { struct block_eraser eraser = flash->block_erasers[k]; @@ -1465,7 +1465,7 @@ return 0; } -int erase_and_write_flash(struct flashchip *flash, uint8_t *oldcontents, +int erase_and_write_flash(struct flashctx *flash, uint8_t *oldcontents, uint8_t *newcontents) { int k, ret = 1; @@ -1683,6 +1683,13 @@ msg_gerr("Flashchips table miscompilation!\n"); ret = 1; } + /* Check that virtual_memory in struct flashctx is placed directly + * after the members copied from struct flashchip. + */ + if (sizeof(struct flashchip) != offsetof(struct flashctx, virtual_memory)) { + msg_gerr("struct flashctx broken!\n"); + ret = 1; + } for (flash = flashchips; flash && flash->name; flash++) if (selfcheck_eraseblocks(flash)) ret = 1; @@ -1708,7 +1715,7 @@ return ret; } -void check_chip_supported(const struct flashchip *flash) +void check_chip_supported(const struct flashctx *flash) { if (TEST_OK_MASK != (flash->tested & TEST_OK_MASK)) { msg_cinfo("===\n"); @@ -1760,7 +1767,7 @@ /* FIXME: This function signature needs to be improved once doit() has a better * function signature. */ -int chip_safety_check(struct flashchip *flash, int force, int read_it, int write_it, int erase_it, int verify_it) +int chip_safety_check(struct flashctx *flash, int force, int read_it, int write_it, int erase_it, int verify_it) { if (!programmer_may_write && (write_it || erase_it)) { msg_perr("Write/erase is not working yet on your programmer in " @@ -1821,7 +1828,7 @@ * but right now it allows us to split off the CLI code. * Besides that, the function itself is a textbook example of abysmal code flow. */ -int doit(struct flashchip *flash, int force, const char *filename, int read_it, int write_it, int erase_it, int verify_it) +int doit(struct flashctx *flash, int force, const char *filename, int read_it, int write_it, int erase_it, int verify_it) { uint8_t *oldcontents; uint8_t *newcontents; Index: flashrom-struct_flashctx/programmer.h =================================================================== --- flashrom-struct_flashctx/programmer.h (Revision 1462) +++ flashrom-struct_flashctx/programmer.h (Arbeitskopie) @@ -24,7 +24,7 @@ #ifndef __PROGRAMMER_H__ #define __PROGRAMMER_H__ 1 -#include "flash.h" /* for chipaddr and flashchip */ +#include "flash.h" /* for chipaddr and flashctx */ enum programmer { #if CONFIG_INTERNAL == 1 @@ -508,7 +508,7 @@ extern struct decode_sizes max_rom_decode; extern int programmer_may_write; extern unsigned long flashbase; -void check_chip_supported(const struct flashchip *flash); +void check_chip_supported(const struct flashctx *flash); int check_max_decode(enum chipbustype buses, uint32_t size); char *extract_programmer_param(const char *param_name); @@ -565,16 +565,16 @@ int (*multicommand)(struct spi_command *cmds); /* Optimized functions for this programmer */ - int (*read)(struct flashchip *flash, uint8_t *buf, int start, int len); - int (*write_256)(struct flashchip *flash, uint8_t *buf, int start, int len); + int (*read)(struct flashctx *flash, uint8_t *buf, int start, int len); + int (*write_256)(struct flashctx *flash, uint8_t *buf, int start, int len); }; extern const struct spi_programmer *spi_programmer; int default_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int default_spi_send_multicommand(struct spi_command *cmds); -int default_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); -int default_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); +int default_spi_read(struct flashctx *flash, uint8_t *buf, int start, int len); +int default_spi_write_256(struct flashctx *flash, uint8_t *buf, int start, int len); void register_spi_programmer(const struct spi_programmer *programmer); /* ichspi.c */ @@ -619,10 +619,10 @@ int max_data_read; int max_data_write; /* Specific functions for this programmer */ - int (*probe) (struct flashchip *flash); - int (*read) (struct flashchip *flash, uint8_t *buf, int start, int len); - int (*write) (struct flashchip *flash, uint8_t *buf, int start, int len); - int (*erase) (struct flashchip *flash, unsigned int blockaddr, unsigned int blocklen); + int (*probe) (struct flashctx *flash); + int (*read) (struct flashctx *flash, uint8_t *buf, int start, int len); + int (*write) (struct flashctx *flash, uint8_t *buf, int start, int len); + int (*erase) (struct flashctx *flash, unsigned int blockaddr, unsigned int blocklen); }; extern const struct opaque_programmer *opaque_programmer; void register_opaque_programmer(const struct opaque_programmer *pgm); @@ -637,7 +637,7 @@ int serprog_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); -int serprog_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); +int serprog_spi_read(struct flashctx *flash, uint8_t *buf, int start, int len); #endif /* serial.c */ Index: flashrom-struct_flashctx/chipdrivers.h =================================================================== --- flashrom-struct_flashctx/chipdrivers.h (Revision 1462) +++ flashrom-struct_flashctx/chipdrivers.h (Arbeitskopie) @@ -19,79 +19,79 @@ * * Header file for flash chip drivers. Included from flash.h. * As a general rule, every function listed here should take a pointer to - * struct flashchip as first parameter. + * struct flashctx as first parameter. */ #ifndef __CHIPDRIVERS_H__ #define __CHIPDRIVERS_H__ 1 -#include "flash.h" /* for chipaddr and flashchip */ +#include "flash.h" /* for chipaddr and flashctx */ /* spi.c, should probably be in spi_chip.c */ -int probe_spi_rdid(struct flashchip *flash); -int probe_spi_rdid4(struct flashchip *flash); -int probe_spi_rems(struct flashchip *flash); -int probe_spi_res1(struct flashchip *flash); -int probe_spi_res2(struct flashchip *flash); +int probe_spi_rdid(struct flashctx *flash); +int probe_spi_rdid4(struct flashctx *flash); +int probe_spi_rems(struct flashctx *flash); +int probe_spi_res1(struct flashctx *flash); +int probe_spi_res2(struct flashctx *flash); int spi_write_enable(void); int spi_write_disable(void); -int spi_block_erase_20(struct flashchip *flash, unsigned int addr, unsigned int blocklen); -int spi_block_erase_52(struct flashchip *flash, unsigned int addr, unsigned int blocklen); -int spi_block_erase_d7(struct flashchip *flash, unsigned int addr, unsigned int blocklen); -int spi_block_erase_d8(struct flashchip *flash, unsigned int addr, unsigned int blocklen); -int spi_block_erase_60(struct flashchip *flash, unsigned int addr, unsigned int blocklen); -int spi_block_erase_c7(struct flashchip *flash, unsigned int addr, unsigned int blocklen); -int spi_chip_write_1(struct flashchip *flash, uint8_t *buf, int start, int len); -int spi_chip_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); -int spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len); +int spi_block_erase_20(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_52(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_d7(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_d8(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_60(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_c7(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_chip_write_1(struct flashctx *flash, uint8_t *buf, int start, int len); +int spi_chip_write_256(struct flashctx *flash, uint8_t *buf, int start, int len); +int spi_chip_read(struct flashctx *flash, uint8_t *buf, int start, int len); uint8_t spi_read_status_register(void); -int spi_write_status_register(struct flashchip *flash, int status); +int spi_write_status_register(struct flashctx *flash, int status); void spi_prettyprint_status_register_bit(uint8_t status, int bit); void spi_prettyprint_status_register_bp3210(uint8_t status, int bp); void spi_prettyprint_status_register_welwip(uint8_t status); -int spi_prettyprint_status_register(struct flashchip *flash); -int spi_disable_blockprotect(struct flashchip *flash); +int spi_prettyprint_status_register(struct flashctx *flash); +int spi_disable_blockprotect(struct flashctx *flash); int spi_byte_program(int addr, uint8_t databyte); int spi_nbyte_program(int addr, uint8_t *bytes, int len); int spi_nbyte_read(int addr, uint8_t *bytes, int len); -int spi_read_chunked(struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize); -int spi_write_chunked(struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize); -int spi_aai_write(struct flashchip *flash, uint8_t *buf, int start, int len); +int spi_read_chunked(struct flashctx *flash, uint8_t *buf, int start, int len, int chunksize); +int spi_write_chunked(struct flashctx *flash, uint8_t *buf, int start, int len, int chunksize); +int spi_aai_write(struct flashctx *flash, uint8_t *buf, int start, int len); /* opaque.c */ -int probe_opaque(struct flashchip *flash); -int read_opaque(struct flashchip *flash, uint8_t *buf, int start, int len); -int write_opaque(struct flashchip *flash, uint8_t *buf, int start, int len); -int erase_opaque(struct flashchip *flash, unsigned int blockaddr, unsigned int blocklen); +int probe_opaque(struct flashctx *flash); +int read_opaque(struct flashctx *flash, uint8_t *buf, int start, int len); +int write_opaque(struct flashctx *flash, uint8_t *buf, int start, int len); +int erase_opaque(struct flashctx *flash, unsigned int blockaddr, unsigned int blocklen); /* a25.c */ -int spi_prettyprint_status_register_amic_a25l05p(struct flashchip *flash); -int spi_prettyprint_status_register_amic_a25l40p(struct flashchip *flash); -int spi_prettyprint_status_register_amic_a25l032(struct flashchip *flash); -int spi_prettyprint_status_register_amic_a25lq032(struct flashchip *flash); +int spi_prettyprint_status_register_amic_a25l05p(struct flashctx *flash); +int spi_prettyprint_status_register_amic_a25l40p(struct flashctx *flash); +int spi_prettyprint_status_register_amic_a25l032(struct flashctx *flash); +int spi_prettyprint_status_register_amic_a25lq032(struct flashctx *flash); /* at25.c */ -int spi_prettyprint_status_register_at25df(struct flashchip *flash); -int spi_prettyprint_status_register_at25df_sec(struct flashchip *flash); -int spi_prettyprint_status_register_at25f(struct flashchip *flash); -int spi_prettyprint_status_register_at25fs010(struct flashchip *flash); -int spi_prettyprint_status_register_at25fs040(struct flashchip *flash); -int spi_prettyprint_status_register_atmel_at26df081a(struct flashchip *flash); -int spi_disable_blockprotect_at25df(struct flashchip *flash); -int spi_disable_blockprotect_at25df_sec(struct flashchip *flash); -int spi_disable_blockprotect_at25f(struct flashchip *flash); -int spi_disable_blockprotect_at25fs010(struct flashchip *flash); -int spi_disable_blockprotect_at25fs040(struct flashchip *flash); +int spi_prettyprint_status_register_at25df(struct flashctx *flash); +int spi_prettyprint_status_register_at25df_sec(struct flashctx *flash); +int spi_prettyprint_status_register_at25f(struct flashctx *flash); +int spi_prettyprint_status_register_at25fs010(struct flashctx *flash); +int spi_prettyprint_status_register_at25fs040(struct flashctx *flash); +int spi_prettyprint_status_register_atmel_at26df081a(struct flashctx *flash); +int spi_disable_blockprotect_at25df(struct flashctx *flash); +int spi_disable_blockprotect_at25df_sec(struct flashctx *flash); +int spi_disable_blockprotect_at25f(struct flashctx *flash); +int spi_disable_blockprotect_at25fs010(struct flashctx *flash); +int spi_disable_blockprotect_at25fs040(struct flashctx *flash); /* 82802ab.c */ -uint8_t wait_82802ab(struct flashchip *flash); -int probe_82802ab(struct flashchip *flash); -int erase_block_82802ab(struct flashchip *flash, unsigned int page, unsigned int pagesize); -int write_82802ab(struct flashchip *flash, uint8_t *buf, int start, int len); +uint8_t wait_82802ab(struct flashctx *flash); +int probe_82802ab(struct flashctx *flash); +int erase_block_82802ab(struct flashctx *flash, unsigned int page, unsigned int pagesize); +int write_82802ab(struct flashctx *flash, uint8_t *buf, int start, int len); void print_status_82802ab(uint8_t status); -int unlock_82802ab(struct flashchip *flash); -int unlock_28f004s5(struct flashchip *flash); -int unlock_lh28f008bjt(struct flashchip *flash); +int unlock_82802ab(struct flashctx *flash); +int unlock_28f004s5(struct flashctx *flash); +int unlock_lh28f008bjt(struct flashctx *flash); /* jedec.c */ uint8_t oddparity(uint8_t val); @@ -99,58 +99,58 @@ void data_polling_jedec(chipaddr dst, uint8_t data); int write_byte_program_jedec(chipaddr bios, uint8_t *src, chipaddr dst); -int probe_jedec(struct flashchip *flash); -int write_jedec(struct flashchip *flash, uint8_t *buf, int start, int len); -int write_jedec_1(struct flashchip *flash, uint8_t *buf, int start, int len); -int erase_sector_jedec(struct flashchip *flash, unsigned int page, unsigned int pagesize); -int erase_block_jedec(struct flashchip *flash, unsigned int page, unsigned int blocksize); -int erase_chip_block_jedec(struct flashchip *flash, unsigned int page, unsigned int blocksize); +int probe_jedec(struct flashctx *flash); +int write_jedec(struct flashctx *flash, uint8_t *buf, int start, int len); +int write_jedec_1(struct flashctx *flash, uint8_t *buf, int start, int len); +int erase_sector_jedec(struct flashctx *flash, unsigned int page, unsigned int pagesize); +int erase_block_jedec(struct flashctx *flash, unsigned int page, unsigned int blocksize); +int erase_chip_block_jedec(struct flashctx *flash, unsigned int page, unsigned int blocksize); /* m29f400bt.c */ -int probe_m29f400bt(struct flashchip *flash); -int block_erase_m29f400bt(struct flashchip *flash, unsigned int start, unsigned int len); -int block_erase_chip_m29f400bt(struct flashchip *flash, unsigned int start, unsigned int len); -int write_m29f400bt(struct flashchip *flash, uint8_t *buf, int start, int len); +int probe_m29f400bt(struct flashctx *flash); +int block_erase_m29f400bt(struct flashctx *flash, unsigned int start, unsigned int len); +int block_erase_chip_m29f400bt(struct flashctx *flash, unsigned int start, unsigned int len); +int write_m29f400bt(struct flashctx *flash, uint8_t *buf, int start, int len); void protect_m29f400bt(chipaddr bios); /* pm49fl00x.c */ -int unlock_49fl00x(struct flashchip *flash); -int lock_49fl00x(struct flashchip *flash); +int unlock_49fl00x(struct flashctx *flash); +int lock_49fl00x(struct flashctx *flash); /* sst28sf040.c */ -int erase_chip_28sf040(struct flashchip *flash, unsigned int addr, unsigned int blocklen); -int erase_sector_28sf040(struct flashchip *flash, unsigned int address, unsigned int sector_size); -int write_28sf040(struct flashchip *flash, uint8_t *buf, int start, int len); -int unprotect_28sf040(struct flashchip *flash); -int protect_28sf040(struct flashchip *flash); +int erase_chip_28sf040(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int erase_sector_28sf040(struct flashctx *flash, unsigned int address, unsigned int sector_size); +int write_28sf040(struct flashctx *flash, uint8_t *buf, int start, int len); +int unprotect_28sf040(struct flashctx *flash); +int protect_28sf040(struct flashctx *flash); /* sst49lfxxxc.c */ -int erase_sector_49lfxxxc(struct flashchip *flash, unsigned int address, unsigned int sector_size); -int unlock_49lfxxxc(struct flashchip *flash); +int erase_sector_49lfxxxc(struct flashctx *flash, unsigned int address, unsigned int sector_size); +int unlock_49lfxxxc(struct flashctx *flash); /* sst_fwhub.c */ -int printlock_sst_fwhub(struct flashchip *flash); -int unlock_sst_fwhub(struct flashchip *flash); +int printlock_sst_fwhub(struct flashctx *flash); +int unlock_sst_fwhub(struct flashctx *flash); /* w39.c */ -int printlock_w39l040(struct flashchip * flash); -int printlock_w39v040a(struct flashchip *flash); -int printlock_w39v040b(struct flashchip *flash); -int printlock_w39v040c(struct flashchip *flash); -int printlock_w39v040fa(struct flashchip *flash); -int printlock_w39v040fb(struct flashchip *flash); -int printlock_w39v040fc(struct flashchip *flash); -int printlock_w39v080a(struct flashchip *flash); -int printlock_w39v080fa(struct flashchip *flash); -int printlock_w39v080fa_dual(struct flashchip *flash); -int unlock_w39v040fb(struct flashchip *flash); -int unlock_w39v080fa(struct flashchip *flash); +int printlock_w39l040(struct flashctx * flash); +int printlock_w39v040a(struct flashctx *flash); +int printlock_w39v040b(struct flashctx *flash); +int printlock_w39v040c(struct flashctx *flash); +int printlock_w39v040fa(struct flashctx *flash); +int printlock_w39v040fb(struct flashctx *flash); +int printlock_w39v040fc(struct flashctx *flash); +int printlock_w39v080a(struct flashctx *flash); +int printlock_w39v080fa(struct flashctx *flash); +int printlock_w39v080fa_dual(struct flashctx *flash); +int unlock_w39v040fb(struct flashctx *flash); +int unlock_w39v080fa(struct flashctx *flash); /* w29ee011.c */ -int probe_w29ee011(struct flashchip *flash); +int probe_w29ee011(struct flashctx *flash); /* stm50flw0x0x.c */ -int erase_sector_stm50flw0x0x(struct flashchip *flash, unsigned int block, unsigned int blocksize); -int unlock_stm50flw0x0x(struct flashchip *flash); +int erase_sector_stm50flw0x0x(struct flashctx *flash, unsigned int block, unsigned int blocksize); +int unlock_stm50flw0x0x(struct flashctx *flash); #endif /* !__CHIPDRIVERS_H__ */ Index: flashrom-struct_flashctx/m29f400bt.c =================================================================== --- flashrom-struct_flashctx/m29f400bt.c (Revision 1462) +++ flashrom-struct_flashctx/m29f400bt.c (Arbeitskopie) @@ -28,7 +28,7 @@ functions. */ /* chunksize is 1 */ -int write_m29f400bt(struct flashchip *flash, uint8_t *src, int start, int len) +int write_m29f400bt(struct flashctx *flash, uint8_t *src, int start, int len) { int i; chipaddr bios = flash->virtual_memory; @@ -55,7 +55,7 @@ return 0; } -int probe_m29f400bt(struct flashchip *flash) +int probe_m29f400bt(struct flashctx *flash) { chipaddr bios = flash->virtual_memory; uint8_t id1, id2; @@ -86,7 +86,7 @@ return 0; } -int erase_m29f400bt(struct flashchip *flash) +int erase_m29f400bt(struct flashctx *flash) { chipaddr bios = flash->virtual_memory; @@ -105,7 +105,7 @@ return 0; } -int block_erase_m29f400bt(struct flashchip *flash, unsigned int start, unsigned int len) +int block_erase_m29f400bt(struct flashctx *flash, unsigned int start, unsigned int len) { chipaddr bios = flash->virtual_memory; chipaddr dst = bios + start; @@ -125,7 +125,7 @@ return 0; } -int block_erase_chip_m29f400bt(struct flashchip *flash, unsigned int address, unsigned int blocklen) +int block_erase_chip_m29f400bt(struct flashctx *flash, unsigned int address, unsigned int blocklen) { if ((address != 0) || (blocklen != flash->total_size * 1024)) { msg_cerr("%s called with incorrect arguments\n", -- http://www.hailfinger.org/ From tanila at tanila.org Wed Nov 9 15:04:35 2011 From: tanila at tanila.org (Alexander Kaupp) Date: Wed, 09 Nov 2011 15:04:35 +0100 Subject: [flashrom] unsupported chip Message-ID: <1320847475.2721.15.camel@debian.fritz.box> flashrom v0.9.2-r1141 on Linux 2.6.32-5-amd64 (x86_64), built with libpci 3.1.7, GCC 4.4.5 20100728 (prerelease), little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 974M loops per second, 10 myus = 10 us, 100 myus = 99 us, 1000 myus = 978 us, 10000 myus = 10287 us, 4 myus = 4 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "ECS" DMI string system-product-name: "GeForce7050M-M" DMI string system-version: "1.0 " DMI string baseboard-manufacturer: "ECS" DMI string baseboard-product-name: "GeForce7050M-M" DMI string baseboard-version: "1.0 " DMI string chassis-type: "Desktop" Found ITE Super I/O, id 8726 Found chipset "NVIDIA MCP67", enabling flash write... chipset PCI ID is 10de:0548, This chipset is not really supported yet. Guesswork... ISA/LPC bridge reg 0x8a contents: 0x40, bit 6 is 1, bit 5 is 0 Flash bus type is SPI Found SMBus device 10de:0542 at 00:01:1 MCP SPI BAR is at 0xfec80000 SPI control is 0xc012, req=0, gnt=0 Please send the output of "flashrom -V" to flashrom at flashrom.org to help us finish support for your chipset. Thanks. OK. This chipset supports the following protocols: SPI. Super I/O ID 0x8726 is not on the list of flash capable controllers. Probing for AMD Am29F010A/B, 128 KB: skipped. Probing for AMD Am29F002(N)BB, 256 KB: skipped. Probing for AMD Am29F002(N)BT, 256 KB: skipped. Probing for AMD Am29F016D, 2048 KB: skipped. Probing for AMD Am29F040B, 512 KB: skipped. Probing for AMD Am29F080B, 1024 KB: skipped. Probing for AMD Am29LV040B, 512 KB: skipped. Probing for AMD Am29LV081B, 1024 KB: skipped. Probing for AMIC A25L05PT, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L05PU, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L10PT, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L10PU, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L20PT, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L20PU, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L40PT, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L40PU, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L80P, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L16PT, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L16PU, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L512, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L010, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L020, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L040, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L080, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L016, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L032, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25LQ032, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A29002B, 256 KB: skipped. Probing for AMIC A29002T, 256 KB: skipped. Probing for AMIC A29040B, 512 KB: skipped. Probing for AMIC A49LF040A, 512 KB: skipped. Probing for ASD AE49F2008, 256 KB: skipped. Probing for Atmel AT25DF021, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF041A, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF081, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF081A, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF161, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF321, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF321A, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF641, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DQ161, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25F512B, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25FS010, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25FS040, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT26DF041, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT26DF081A, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT26DF161, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT26DF161A, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT26F004, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT29C512, 64 KB: skipped. Probing for Atmel AT29C010A, 128 KB: skipped. Probing for Atmel AT29C020, 256 KB: skipped. Probing for Atmel AT29C040A, 512 KB: skipped. Probing for Atmel AT45CS1282, 16896 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB011D, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB021D, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB041D, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB081D, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB161D, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB321C, 4224 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB321D, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB642D, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT49BV512, 64 KB: skipped. Probing for Atmel AT49F020, 256 KB: skipped. Probing for Atmel AT49F002(N), 256 KB: skipped. Probing for Atmel AT49F002(N)T, 256 KB: skipped. Probing for EMST F49B002UA, 256 KB: skipped. Probing for EMST F25L008A, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B05, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B05T, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B10, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B10T, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B20, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B20T, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B40, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B40T, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B80, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B80T, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B16, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B16T, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B32, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B32T, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B64, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B64T, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25D16, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F05, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F10, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F20, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F40, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F80, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F16, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F32, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN29F010, 128 KB: skipped. Probing for Eon EN29F002(A)(N)B, 256 KB: skipped. Probing for Eon EN29F002(A)(N)T, 256 KB: skipped. Probing for Fujitsu MBM29F004BC, 512 KB: skipped. Probing for Fujitsu MBM29F004TC, 512 KB: skipped. Probing for Fujitsu MBM29F400BC, 512 KB: skipped. Probing for Fujitsu MBM29F400TC, 512 KB: skipped. Probing for Hyundai HY29F002T, 256 KB: skipped. Probing for Hyundai HY29F002B, 256 KB: skipped. Probing for Intel 28F001BX-B, 128 KB: skipped. Probing for Intel 28F001BX-T, 128 KB: skipped. Probing for Intel 28F002BC-T, 256 KB: skipped. Probing for Intel 28F004S5, 512 KB: skipped. Probing for Intel 28F004BV/BE-B, 512 KB: skipped. Probing for Intel 28F004BV/BE-T, 512 KB: skipped. Probing for Intel 28F400BV/CV/CE-B, 512 KB: skipped. Probing for Intel 28F400BV/CV/CE-T, 512 KB: skipped. Probing for Intel 82802AB, 512 KB: skipped. Probing for Intel 82802AC, 1024 KB: skipped. Probing for Macronix MX25L512, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L1005, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L2005, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L4005, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L8005, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Chip status register is 00 Chip status register: Status Register Write Disable (SRWD) is not set Chip status register: Bit 6 is not set Chip status register: Bit 5 / Block Protect 3 (BP3) is not set Chip status register: Bit 4 / Block Protect 2 (BP2) is not set Chip status register: Bit 3 / Block Protect 1 (BP1) is not set Chip status register: Bit 2 / Block Protect 0 (BP0) is not set Chip status register: Write Enable Latch (WEL) is not set Chip status register: Write In Progress (WIP/BUSY) is not set Found chip "Macronix MX25L8005" (1024 KB, SPI) at physical address 0xfff00000. Probing for Macronix MX25L1605, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L1635D, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L3205, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L3235D, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L6405, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L12805, 16384 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX29F001B, 128 KB: skipped. Probing for Macronix MX29F001T, 128 KB: skipped. Probing for Macronix MX29F002B, 256 KB: skipped. Probing for Macronix MX29F002T, 256 KB: skipped. Probing for Macronix MX29LV040, 512 KB: skipped. Probing for MoselVitelic V29C51000B, 64 KB: skipped. Probing for MoselVitelic V29C51000T, 64 KB: skipped. Probing for MoselVitelic V29C51400B, 512 KB: skipped. Probing for MoselVitelic V29C51400T, 512 KB: skipped. Probing for MoselVitelic V29LC51000, 64 KB: skipped. Probing for MoselVitelic V29LC51001, 128 KB: skipped. Probing for MoselVitelic V29LC51002, 256 KB: skipped. Probing for Numonyx M25PE10, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Numonyx M25PE20, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Numonyx M25PE40, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Numonyx M25PE80, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Numonyx M25PE16, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV010, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV016B, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV020, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV040, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV080B, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV512, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm29F002T, 256 KB: skipped. Probing for PMC Pm29F002B, 256 KB: skipped. Probing for PMC Pm39LV010, 128 KB: skipped. Probing for PMC Pm39LV020, 256 KB: skipped. Probing for PMC Pm39LV040, 512 KB: skipped. Probing for PMC Pm49FL002, 256 KB: skipped. Probing for PMC Pm49FL004, 512 KB: skipped. Probing for Sanyo LF25FW203A, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Sharp LHF00L04, 1024 KB: skipped. Probing for Spansion S25FL008A, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Spansion S25FL016A, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25VF016B, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25VF032B, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25VF064C, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25VF040.REMS, 512 KB: probe_spi_rems: id1 0xc2, id2 0x13 Probing for SST SST25VF040B, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25LF040A.RES, 512 KB: probe_spi_res2: id1 0x13, id2 0x13 Probing for SST SST25VF040B.REMS, 512 KB: probe_spi_rems: id1 0xc2, id2 0x13 Probing for SST SST25VF080B, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST28SF040A, 512 KB: skipped. Probing for SST SST29EE010, 128 KB: skipped. Probing for SST SST29LE010, 128 KB: skipped. Probing for SST SST29EE020A, 256 KB: skipped. Probing for SST SST29LE020, 256 KB: skipped. Probing for SST SST39SF512, 64 KB: skipped. Probing for SST SST39SF010A, 128 KB: skipped. Probing for SST SST39SF020A, 256 KB: skipped. Probing for SST SST39SF040, 512 KB: skipped. Probing for SST SST39VF512, 64 KB: skipped. Probing for SST SST39VF010, 128 KB: skipped. Probing for SST SST39VF020, 256 KB: skipped. Probing for SST SST39VF040, 512 KB: skipped. Probing for SST SST39VF080, 1024 KB: skipped. Probing for SST SST49LF002A/B, 256 KB: skipped. Probing for SST SST49LF003A/B, 384 KB: skipped. Probing for SST SST49LF004A/B, 512 KB: skipped. Probing for SST SST49LF004C, 512 KB: skipped. Probing for SST SST49LF008A, 1024 KB: skipped. Probing for SST SST49LF008C, 1024 KB: skipped. Probing for SST SST49LF016C, 2048 KB: skipped. Probing for SST SST49LF020, 256 KB: skipped. Probing for SST SST49LF020A, 256 KB: skipped. Probing for SST SST49LF040, 512 KB: skipped. Probing for SST SST49LF040B, 512 KB: skipped. Probing for SST SST49LF080A, 1024 KB: skipped. Probing for SST SST49LF160C, 2048 KB: skipped. Probing for ST M25P05-A, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P05.RES, 64 KB: Ignoring RES in favour of RDID. Probing for ST M25P10-A, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P10.RES, 128 KB: Ignoring RES in favour of RDID. Probing for ST M25P20, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P40, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P40-old, 512 KB: Ignoring RES in favour of RDID. Probing for ST M25P80, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P16, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P32, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P64, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P128, 16384 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M29F002B, 256 KB: skipped. Probing for ST M29F002T/NT, 256 KB: skipped. Probing for ST M29F040B, 512 KB: skipped. Probing for ST M29F400BB, 512 KB: skipped. Probing for ST M29F400BT, 512 KB: skipped. Probing for ST M29W010B, 128 KB: skipped. Probing for ST M29W040B, 512 KB: skipped. Probing for ST M29W512B, 64 KB: skipped. Probing for ST M50FLW040A, 512 KB: skipped. Probing for ST M50FLW040B, 512 KB: skipped. Probing for ST M50FLW080A, 1024 KB: skipped. Probing for ST M50FLW080B, 1024 KB: skipped. Probing for ST M50FW002, 256 KB: skipped. Probing for ST M50FW016, 2048 KB: skipped. Probing for ST M50FW040, 512 KB: skipped. Probing for ST M50FW080, 1024 KB: skipped. Probing for ST M50LPW116, 2048 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51001B, 128 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51001T, 128 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51002B, 256 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51002T, 256 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51004B, 512 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51004T, 512 KB: skipped. Probing for SyncMOS/MoselVitelic {S,V}29C31004B, 512 KB: skipped. Probing for SyncMOS/MoselVitelic {S,V}29C31004T, 512 KB: skipped. Probing for TI TMS29F002RB, 256 KB: skipped. Probing for TI TMS29F002RT, 256 KB: skipped. Probing for Winbond W25Q80, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25Q16, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25Q32, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25Q64, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25x10, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25x20, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25x40, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25x80, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25x16, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25x32, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25x64, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W29C011, 128 KB: skipped. Probing for Winbond W29C020C, 256 KB: skipped. Probing for Winbond W29C040P, 512 KB: skipped. Probing for Winbond W29EE011, 128 KB: skipped. Probing for Winbond W39V040A, 512 KB: skipped. Probing for Winbond W39V040B, 512 KB: skipped. Probing for Winbond W39V040C, 512 KB: skipped. Probing for Winbond W39V040FA, 512 KB: skipped. Probing for Winbond W39V080A, 1024 KB: skipped. Probing for Winbond W49F002U, 256 KB: skipped. Probing for Winbond W49F020, 256 KB: skipped. Probing for Winbond W49V002A, 256 KB: skipped. Probing for Winbond W49V002FA, 256 KB: skipped. Probing for Winbond W39V080FA, 1024 KB: skipped. Probing for Winbond W39V080FA (dual mode), 512 KB: skipped. Probing for AMIC unknown AMIC SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel unknown Atmel SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon unknown Eon SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix unknown Macronix SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC unknown PMC SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST unknown SST SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST unknown ST SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Sanyo unknown Sanyo SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Generic unknown SPI chip (RDID), 0 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Generic unknown SPI chip (REMS), 0 KB: probe_spi_rems: id1 0xc2, id2 0x13 No operations were specified. From Michael.Karcher at fu-berlin.de Wed Nov 9 23:19:42 2011 From: Michael.Karcher at fu-berlin.de (Michael Karcher) Date: Wed, 09 Nov 2011 23:19:42 +0100 Subject: [flashrom] [PATCH] Register Parallel/LPC/FWH programmers In-Reply-To: <4EB7E17E.6070001@gmx.net> References: <4DEDCE84.8020400@gmx.net> <4E6808CE.7010906@gmx.net> <201109082137.p88Lb3DF014751@mail2.student.tuwien.ac.at> <4E6A5322.8070003@gmx.net> <4EB7E17E.6070001@gmx.net> Message-ID: <1320877182.12407.45.camel@localhost> Am Montag, den 07.11.2011, 14:47 +0100 schrieb Carl-Daniel Hailfinger: > >>> - Should register_par_programmer(...) be called before or after setting > >>> max_rom_decode.*? > >> why is that not a field in the different programmer structs (yet?)? > > Supply it as > > register_par_programmer() parameter and extend register_spi_programmer > > to accept that parameter as well? > I'm now setting max_rom_decode before calling register_par_programmer. > Given that such restrictions may exist for any programmer, I'll postpone > handling max_rom_decode to the universal programmer registration patch > where we get the infrastructure to deal with such programmer > limitations. If you have any objections, please tell me. As we are heading strongly towards having a dynamic list of programmers, and there might even be two SPI programmers with different max decode size, storing it with the programmer structure seems like the only sane option. Having the registeration function fill a field in the dynamic programmer structure using a parameter is one sensible choice to get that field populated. > >>> - Is there a better name for register_par_programmer? > >>> > >> register_parallel_programmer ofc, and imho it is not too long, because > >> it is seldom used, but i don't care that much (due to the same reason). > >> > > 80 column limit... I think that was one of the reasons we used a shorter > > name. I am not really convinced "parallel" is to the point. While even LPC/FWH is still using 4 bits in parallel, the real distinction between parallel/LPC/FWH and SPI is that parallel/LPC/FWH is pushing commands through a memory read/write interface, while SPI pushes memory read/writes through a command interface. (At least if you look at the layer of abstraction applying to flashrom) But "register_memcycle_programmer" is most likely something people are not going to understand, although, looking at the contents of your par_programmer structure, all the functions really are about memory cylces. > max_rom_decode is conceptually different from buses_supported although > that was not obvious when I wrote the paragraph above. It will be > handled in the universal programmer registration patch. In the end, I don't even think we need buses_supported outside of the classic/memcycle/parallel programmer (however you call it), because SPI interface chips just support spi flash chips, and for opaque programmers we even had to introduce a fake bus type. Maximum supported chip size on the other hand is a concept that likely applies sensibly apply to every type of programmer. > >>> - Should map_flash_region/unmap_flash_region be part of the registration? > >> no idea what that does exactly :P > > It makes the flash chip accessible. This is essentially physmap for > > programmers with memory mapped flash and a no-op for everything else. If the idea of a future flashrom (or libflashrom) is that you scan the system for programmers and build a table from the registrations, then I don't think you really want to initialize the hardware/map the memory at the time of registration further than needed for detection, but you need a hardware startup callback in the programmer. > And moving it into the parallel programmer struct may not have been the > best idea. Sure, that gets it out of the way conveniently, but once the > universal programmer registration patch is in, we will not have any > dummy parallel programmer struct for such fallbacks anymore. [drkaiser] > + > + max_rom_decode.parallel = 131072; "128 * 1024" to comply with the flashrom style? > + register_par_programmer(&par_programmer_drkaiser, BUS_PARALLEL); > + > return 0; > } > + /* FIXME: This assumes that serprog device bustypes are always > + * identical with flashrom bustype enums and that they all fit > + * in a single byte. > + */ I guess that is how the serprog protocol is "specified" ;) > Index: flashrom-register_par_programmer/it85spi.c > =================================================================== > --- flashrom-register_par_programmer/it85spi.c (Revision 1460) > +++ flashrom-register_par_programmer/it85spi.c (Arbeitskopie) > @@ -257,8 +257,10 @@ > INDIRECT_A3(shm_io_base, (base >> 24)); > #endif > #ifdef LPC_MEMORY > - base = (chipaddr)programmer_map_flash_region("it85 communication", > - 0xFFFFF000, 0x1000); > + /* FIXME: We should block accessing that region for anything else. > + * Major TODO here, and it will be a lot of work. > + */ "blocking it for anything else" just means disabling the "classic/parallel" interface of the internal programmer, if I understand it correctly, so... > + /* FIXME: Really leave FWH enabled? We can't use this region > + * anymore since accessing it would mess up IT85 communication. > + * If we decide to disable FWH for this region, we should print > + * a debug message about it. > + */ ... of course FWH/LPC/Parallel needs to be turned off here. I hope this code verifies that the IT85 SPI flash translator is really enabled, before concluding this. Looks fine so far. So go ahead and commit. Acked-By: Michael Karcher Regards, Michael Karcher -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 198 bytes Desc: This is a digitally signed message part URL: From svn at flashrom.org Thu Nov 10 00:40:00 2011 From: svn at flashrom.org (repository service) Date: Thu, 10 Nov 2011 00:40:00 +0100 Subject: [flashrom] [commit] r1463 - trunk Message-ID: Author: hailfinger Date: Thu Nov 10 00:40:00 2011 New Revision: 1463 URL: http://flashrom.org/trac/flashrom/changeset/1463 Log: Register Parallel/LPC/FWH programmers the same way SPI programmers are registered. All programmers are now calling programmer registration functions and direct manipulations of buses_supported are not needed/possible anymore. Note: Programmers without parallel/LPC/FWH chip support should not call register_par_programmer(). Additional fixes: Set max_rom_decode.parallel for drkaiser. Remove abuse of programmer_map_flash_region in it85spi. Annotate several FIXMEs in it85spi. Signed-off-by: Carl-Daniel Hailfinger Acked-By: Michael Karcher Modified: trunk/atahpt.c trunk/board_enable.c trunk/chipset_enable.c trunk/cli_classic.c trunk/drkaiser.c trunk/dummyflasher.c trunk/flashrom.c trunk/gfxnvidia.c trunk/ichspi.c trunk/internal.c trunk/it85spi.c trunk/it87spi.c trunk/nic3com.c trunk/nicintel.c trunk/nicnatsemi.c trunk/nicrealtek.c trunk/programmer.c trunk/programmer.h trunk/satamv.c trunk/satasii.c trunk/serprog.c trunk/wbsio_spi.c Modified: trunk/atahpt.c ============================================================================== --- trunk/atahpt.c Tue Nov 8 12:55:24 2011 (r1462) +++ trunk/atahpt.c Thu Nov 10 00:40:00 2011 (r1463) @@ -40,6 +40,17 @@ {}, }; +static const struct par_programmer par_programmer_atahpt = { + .chip_readb = atahpt_chip_readb, + .chip_readw = fallback_chip_readw, + .chip_readl = fallback_chip_readl, + .chip_readn = fallback_chip_readn, + .chip_writeb = atahpt_chip_writeb, + .chip_writew = fallback_chip_writew, + .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, +}; + static int atahpt_shutdown(void *data) { /* Flash access is disabled automatically by PCI restore. */ @@ -61,10 +72,11 @@ reg32 |= (1 << 24); rpci_write_long(pcidev_dev, REG_FLASH_ACCESS, reg32); - buses_supported = BUS_PARALLEL; - if (register_shutdown(atahpt_shutdown, NULL)) return 1; + + register_par_programmer(&par_programmer_atahpt, BUS_PARALLEL); + return 0; } Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Tue Nov 8 12:55:24 2011 (r1462) +++ trunk/board_enable.c Thu Nov 10 00:40:00 2011 (r1463) @@ -425,7 +425,7 @@ /* Check if at least one flash segment is enabled. */ if (tmp & 0xf0) { /* The IT8705F will respond to LPC cycles and translate them. */ - buses_supported = BUS_PARALLEL; + internal_buses_supported = BUS_PARALLEL; /* Flash ROM I/F Writes Enable */ tmp |= 0x04; msg_pdbg("Enabling IT8705F flash ROM interface write.\n"); Modified: trunk/chipset_enable.c ============================================================================== --- trunk/chipset_enable.c Tue Nov 8 12:55:24 2011 (r1462) +++ trunk/chipset_enable.c Thu Nov 10 00:40:00 2011 (r1463) @@ -213,7 +213,7 @@ uint16_t old, new; uint16_t xbcs = 0x4e; /* X-Bus Chip Select register. */ - buses_supported = BUS_PARALLEL; + internal_buses_supported = BUS_PARALLEL; old = pci_read_word(dev, xbcs); @@ -303,7 +303,7 @@ * FWH_DEC_EN1, but they are called FB_SEL1, FB_SEL2, FB_DEC_EN1 and * FB_DEC_EN2. */ - buses_supported = BUS_FWH; + internal_buses_supported = BUS_FWH; return enable_flash_ich(dev, name, 0x4e); } @@ -412,9 +412,9 @@ msg_pdbg("\nMaximum FWH chip size: 0x%x bytes", max_rom_decode.fwh); /* If we're called by enable_flash_ich_dc_spi, it will override - * buses_supported anyway. + * internal_buses_supported anyway. */ - buses_supported = BUS_FWH; + internal_buses_supported = BUS_FWH; return enable_flash_ich(dev, name, 0xdc); } @@ -434,7 +434,7 @@ if (new != old) rpci_write_byte(dev, 0xd9, new); - buses_supported = BUS_FWH; + internal_buses_supported = BUS_FWH; return 0; } @@ -468,12 +468,11 @@ bnt = mmio_readl(rcrb + 0x3410); if (bnt & 0x02) { /* If strapped to LPC, no SPI initialization is required */ - buses_supported = BUS_FWH; + internal_buses_supported = BUS_FWH; return 0; } /* This adds BUS_SPI */ - buses_supported = BUS_SPI; if (ich_init_spi(dev, tmp, rcrb, 7) != 0) { if (!ret) ret = ERROR_NONFATAL; @@ -556,7 +555,7 @@ * time. At least not with our current code. So we prevent searching * on ICH7 when the southbridge is strapped to LPC */ - buses_supported = BUS_FWH; + internal_buses_supported = BUS_FWH; if (ich_generation == CHIPSET_ICH7) { if (bbs == 0x03) { /* If strapped to LPC, no further SPI initialization is @@ -564,7 +563,7 @@ return ret; } else { /* Disable LPC/FWH if strapped to PCI or SPI */ - buses_supported = 0; + internal_buses_supported = BUS_NONE; } } @@ -669,7 +668,7 @@ #define CS5530_ENABLE_SA2320 (1 << 2) #define CS5530_ENABLE_SA20 (1 << 6) - buses_supported = BUS_PARALLEL; + internal_buses_supported = BUS_PARALLEL; /* Decode 0x000E0000-0x000FFFFF (128 kB), not just 64 kB, and * decode 0xFF000000-0xFFFFFFFF (16 MB), not just 256 kB. * FIXME: Should we really touch the low mapping below 1 MB? Flashrom @@ -822,7 +821,7 @@ (prot & 0xfffff800) + (((prot & 0x7fc) << 8) | 0x3ff)); } - buses_supported = BUS_LPC | BUS_FWH; + internal_buses_supported = BUS_LPC | BUS_FWH; ret = sb600_probe_spi(dev); @@ -916,7 +915,7 @@ { uint8_t tmp; - buses_supported = BUS_PARALLEL; + internal_buses_supported = BUS_PARALLEL; tmp = INB(0xc06); tmp |= 0x1; @@ -1016,7 +1015,7 @@ switch ((val >> 5) & 0x3) { case 0x0: ret = enable_flash_mcp55(dev, name); - buses_supported = BUS_LPC; + internal_buses_supported = BUS_LPC; msg_pdbg("Flash bus type is LPC\n"); break; case 0x2: @@ -1024,7 +1023,7 @@ /* SPI is added in mcp6x_spi_init if it works. * Do we really want to disable LPC in this case? */ - buses_supported = BUS_NONE; + internal_buses_supported = BUS_NONE; msg_pdbg("Flash bus type is SPI\n"); msg_pinfo("SPI on this chipset is WIP. Please report any " "success or failure by mailing us the verbose " @@ -1032,7 +1031,7 @@ break; default: /* Should not happen. */ - buses_supported = BUS_NONE; + internal_buses_supported = BUS_NONE; msg_pdbg("Flash bus type is unknown (none)\n"); msg_pinfo("Something went wrong with bus type detection.\n"); goto out_msg; @@ -1325,7 +1324,6 @@ struct pci_dev *dev = NULL; int ret = -2; /* Nothing! */ int i; - char *s; /* Now let's try to find the chipset we have... */ for (i = 0; chipset_enables[i].vendor_name != NULL; i++) { @@ -1377,9 +1375,5 @@ } } - s = flashbuses_to_text(buses_supported); - msg_pinfo("This chipset supports the following protocols: %s.\n", s); - free(s); - return ret; } Modified: trunk/cli_classic.c ============================================================================== --- trunk/cli_classic.c Tue Nov 8 12:55:24 2011 (r1462) +++ trunk/cli_classic.c Thu Nov 10 00:40:00 2011 (r1463) @@ -443,6 +443,10 @@ ret = 1; goto out_shutdown; } + tempstr = flashbuses_to_text(buses_supported); + msg_pdbg("This programmer supports the following protocols: %s.\n", + tempstr); + free(tempstr); for (i = 0; i < ARRAY_SIZE(flashes); i++) { startchip = probe_flash(startchip, &flashes[i], 0); Modified: trunk/drkaiser.c ============================================================================== --- trunk/drkaiser.c Tue Nov 8 12:55:24 2011 (r1462) +++ trunk/drkaiser.c Thu Nov 10 00:40:00 2011 (r1463) @@ -39,6 +39,17 @@ static uint8_t *drkaiser_bar; +static const struct par_programmer par_programmer_drkaiser = { + .chip_readb = drkaiser_chip_readb, + .chip_readw = fallback_chip_readw, + .chip_readl = fallback_chip_readl, + .chip_readn = fallback_chip_readn, + .chip_writeb = drkaiser_chip_writeb, + .chip_writew = fallback_chip_writew, + .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, +}; + static int drkaiser_shutdown(void *data) { physunmap(drkaiser_bar, DRKAISER_MEMMAP_SIZE); @@ -64,10 +75,12 @@ drkaiser_bar = physmap("Dr. Kaiser PC-Waechter flash memory", addr, DRKAISER_MEMMAP_SIZE); - buses_supported = BUS_PARALLEL; - if (register_shutdown(drkaiser_shutdown, NULL)) return 1; + + max_rom_decode.parallel = 128 * 1024; + register_par_programmer(&par_programmer_drkaiser, BUS_PARALLEL); + return 0; } Modified: trunk/dummyflasher.c ============================================================================== --- trunk/dummyflasher.c Tue Nov 8 12:55:24 2011 (r1462) +++ trunk/dummyflasher.c Thu Nov 10 00:40:00 2011 (r1463) @@ -75,6 +75,19 @@ .write_256 = dummy_spi_write_256, }; +static const struct par_programmer par_programmer_dummy = { + .chip_readb = dummy_chip_readb, + .chip_readw = dummy_chip_readw, + .chip_readl = dummy_chip_readl, + .chip_readn = dummy_chip_readn, + .chip_writeb = dummy_chip_writeb, + .chip_writew = dummy_chip_writew, + .chip_writel = dummy_chip_writel, + .chip_writen = dummy_chip_writen, +}; + +enum chipbustype dummy_buses_supported = BUS_NONE; + static int dummy_shutdown(void *data) { msg_pspew("%s\n", __func__); @@ -108,24 +121,24 @@ /* Convert the parameters to lowercase. */ tolower_string(bustext); - buses_supported = BUS_NONE; + dummy_buses_supported = BUS_NONE; if (strstr(bustext, "parallel")) { - buses_supported |= BUS_PARALLEL; + dummy_buses_supported |= BUS_PARALLEL; msg_pdbg("Enabling support for %s flash.\n", "parallel"); } if (strstr(bustext, "lpc")) { - buses_supported |= BUS_LPC; + dummy_buses_supported |= BUS_LPC; msg_pdbg("Enabling support for %s flash.\n", "LPC"); } if (strstr(bustext, "fwh")) { - buses_supported |= BUS_FWH; + dummy_buses_supported |= BUS_FWH; msg_pdbg("Enabling support for %s flash.\n", "FWH"); } if (strstr(bustext, "spi")) { - register_spi_programmer(&spi_programmer_dummyflasher); + dummy_buses_supported |= BUS_SPI; msg_pdbg("Enabling support for %s flash.\n", "SPI"); } - if (buses_supported == BUS_NONE) + if (dummy_buses_supported == BUS_NONE) msg_pdbg("Support for all flash bus types disabled.\n"); free(bustext); @@ -226,6 +239,14 @@ free(flashchip_contents); return 1; } + if (dummy_buses_supported & (BUS_PARALLEL | BUS_LPC | BUS_FWH)) + register_par_programmer(&par_programmer_dummy, + dummy_buses_supported & + (BUS_PARALLEL | BUS_LPC | + BUS_FWH)); + if (dummy_buses_supported & BUS_SPI) + register_spi_programmer(&spi_programmer_dummyflasher); + return 0; } Modified: trunk/flashrom.c ============================================================================== --- trunk/flashrom.c Tue Nov 8 12:55:24 2011 (r1462) +++ trunk/flashrom.c Thu Nov 10 00:40:00 2011 (r1463) @@ -68,14 +68,6 @@ .init = internal_init, .map_flash_region = physmap, .unmap_flash_region = physunmap, - .chip_readb = internal_chip_readb, - .chip_readw = internal_chip_readw, - .chip_readl = internal_chip_readl, - .chip_readn = internal_chip_readn, - .chip_writeb = internal_chip_writeb, - .chip_writew = internal_chip_writew, - .chip_writel = internal_chip_writel, - .chip_writen = fallback_chip_writen, .delay = internal_delay, }, #endif @@ -86,14 +78,6 @@ .init = dummy_init, .map_flash_region = dummy_map, .unmap_flash_region = dummy_unmap, - .chip_readb = dummy_chip_readb, - .chip_readw = dummy_chip_readw, - .chip_readl = dummy_chip_readl, - .chip_readn = dummy_chip_readn, - .chip_writeb = dummy_chip_writeb, - .chip_writew = dummy_chip_writew, - .chip_writel = dummy_chip_writel, - .chip_writen = dummy_chip_writen, .delay = internal_delay, }, #endif @@ -104,14 +88,6 @@ .init = nic3com_init, .map_flash_region = fallback_map, .unmap_flash_region = fallback_unmap, - .chip_readb = nic3com_chip_readb, - .chip_readw = fallback_chip_readw, - .chip_readl = fallback_chip_readl, - .chip_readn = fallback_chip_readn, - .chip_writeb = nic3com_chip_writeb, - .chip_writew = fallback_chip_writew, - .chip_writel = fallback_chip_writel, - .chip_writen = fallback_chip_writen, .delay = internal_delay, }, #endif @@ -124,14 +100,6 @@ .init = nicrealtek_init, .map_flash_region = fallback_map, .unmap_flash_region = fallback_unmap, - .chip_readb = nicrealtek_chip_readb, - .chip_readw = fallback_chip_readw, - .chip_readl = fallback_chip_readl, - .chip_readn = fallback_chip_readn, - .chip_writeb = nicrealtek_chip_writeb, - .chip_writew = fallback_chip_writew, - .chip_writel = fallback_chip_writel, - .chip_writen = fallback_chip_writen, .delay = internal_delay, }, #endif @@ -142,14 +110,6 @@ .init = nicnatsemi_init, .map_flash_region = fallback_map, .unmap_flash_region = fallback_unmap, - .chip_readb = nicnatsemi_chip_readb, - .chip_readw = fallback_chip_readw, - .chip_readl = fallback_chip_readl, - .chip_readn = fallback_chip_readn, - .chip_writeb = nicnatsemi_chip_writeb, - .chip_writew = fallback_chip_writew, - .chip_writel = fallback_chip_writel, - .chip_writen = fallback_chip_writen, .delay = internal_delay, }, #endif @@ -160,14 +120,6 @@ .init = gfxnvidia_init, .map_flash_region = fallback_map, .unmap_flash_region = fallback_unmap, - .chip_readb = gfxnvidia_chip_readb, - .chip_readw = fallback_chip_readw, - .chip_readl = fallback_chip_readl, - .chip_readn = fallback_chip_readn, - .chip_writeb = gfxnvidia_chip_writeb, - .chip_writew = fallback_chip_writew, - .chip_writel = fallback_chip_writel, - .chip_writen = fallback_chip_writen, .delay = internal_delay, }, #endif @@ -178,14 +130,6 @@ .init = drkaiser_init, .map_flash_region = fallback_map, .unmap_flash_region = fallback_unmap, - .chip_readb = drkaiser_chip_readb, - .chip_readw = fallback_chip_readw, - .chip_readl = fallback_chip_readl, - .chip_readn = fallback_chip_readn, - .chip_writeb = drkaiser_chip_writeb, - .chip_writew = fallback_chip_writew, - .chip_writel = fallback_chip_writel, - .chip_writen = fallback_chip_writen, .delay = internal_delay, }, #endif @@ -196,14 +140,6 @@ .init = satasii_init, .map_flash_region = fallback_map, .unmap_flash_region = fallback_unmap, - .chip_readb = satasii_chip_readb, - .chip_readw = fallback_chip_readw, - .chip_readl = fallback_chip_readl, - .chip_readn = fallback_chip_readn, - .chip_writeb = satasii_chip_writeb, - .chip_writew = fallback_chip_writew, - .chip_writel = fallback_chip_writel, - .chip_writen = fallback_chip_writen, .delay = internal_delay, }, #endif @@ -214,14 +150,6 @@ .init = atahpt_init, .map_flash_region = fallback_map, .unmap_flash_region = fallback_unmap, - .chip_readb = atahpt_chip_readb, - .chip_readw = fallback_chip_readw, - .chip_readl = fallback_chip_readl, - .chip_readn = fallback_chip_readn, - .chip_writeb = atahpt_chip_writeb, - .chip_writew = fallback_chip_writew, - .chip_writel = fallback_chip_writel, - .chip_writen = fallback_chip_writen, .delay = internal_delay, }, #endif @@ -232,14 +160,6 @@ .init = ft2232_spi_init, .map_flash_region = fallback_map, .unmap_flash_region = fallback_unmap, - .chip_readb = noop_chip_readb, - .chip_readw = fallback_chip_readw, - .chip_readl = fallback_chip_readl, - .chip_readn = fallback_chip_readn, - .chip_writeb = noop_chip_writeb, - .chip_writew = fallback_chip_writew, - .chip_writel = fallback_chip_writel, - .chip_writen = fallback_chip_writen, .delay = internal_delay, }, #endif @@ -250,14 +170,6 @@ .init = serprog_init, .map_flash_region = fallback_map, .unmap_flash_region = fallback_unmap, - .chip_readb = serprog_chip_readb, - .chip_readw = fallback_chip_readw, - .chip_readl = fallback_chip_readl, - .chip_readn = serprog_chip_readn, - .chip_writeb = serprog_chip_writeb, - .chip_writew = fallback_chip_writew, - .chip_writel = fallback_chip_writel, - .chip_writen = fallback_chip_writen, .delay = serprog_delay, }, #endif @@ -268,14 +180,6 @@ .init = buspirate_spi_init, .map_flash_region = fallback_map, .unmap_flash_region = fallback_unmap, - .chip_readb = noop_chip_readb, - .chip_readw = fallback_chip_readw, - .chip_readl = fallback_chip_readl, - .chip_readn = fallback_chip_readn, - .chip_writeb = noop_chip_writeb, - .chip_writew = fallback_chip_writew, - .chip_writel = fallback_chip_writel, - .chip_writen = fallback_chip_writen, .delay = internal_delay, }, #endif @@ -286,14 +190,6 @@ .init = dediprog_init, .map_flash_region = fallback_map, .unmap_flash_region = fallback_unmap, - .chip_readb = noop_chip_readb, - .chip_readw = fallback_chip_readw, - .chip_readl = fallback_chip_readl, - .chip_readn = fallback_chip_readn, - .chip_writeb = noop_chip_writeb, - .chip_writew = fallback_chip_writew, - .chip_writel = fallback_chip_writel, - .chip_writen = fallback_chip_writen, .delay = internal_delay, }, #endif @@ -304,14 +200,6 @@ .init = rayer_spi_init, .map_flash_region = fallback_map, .unmap_flash_region = fallback_unmap, - .chip_readb = noop_chip_readb, - .chip_readw = fallback_chip_readw, - .chip_readl = fallback_chip_readl, - .chip_readn = fallback_chip_readn, - .chip_writeb = noop_chip_writeb, - .chip_writew = fallback_chip_writew, - .chip_writel = fallback_chip_writel, - .chip_writen = fallback_chip_writen, .delay = internal_delay, }, #endif @@ -322,14 +210,6 @@ .init = nicintel_init, .map_flash_region = fallback_map, .unmap_flash_region = fallback_unmap, - .chip_readb = nicintel_chip_readb, - .chip_readw = fallback_chip_readw, - .chip_readl = fallback_chip_readl, - .chip_readn = fallback_chip_readn, - .chip_writeb = nicintel_chip_writeb, - .chip_writew = fallback_chip_writew, - .chip_writel = fallback_chip_writel, - .chip_writen = fallback_chip_writen, .delay = internal_delay, }, #endif @@ -340,14 +220,6 @@ .init = nicintel_spi_init, .map_flash_region = fallback_map, .unmap_flash_region = fallback_unmap, - .chip_readb = noop_chip_readb, - .chip_readw = fallback_chip_readw, - .chip_readl = fallback_chip_readl, - .chip_readn = fallback_chip_readn, - .chip_writeb = noop_chip_writeb, - .chip_writew = fallback_chip_writew, - .chip_writel = fallback_chip_writel, - .chip_writen = fallback_chip_writen, .delay = internal_delay, }, #endif @@ -358,14 +230,6 @@ .init = ogp_spi_init, .map_flash_region = fallback_map, .unmap_flash_region = fallback_unmap, - .chip_readb = noop_chip_readb, - .chip_readw = fallback_chip_readw, - .chip_readl = fallback_chip_readl, - .chip_readn = fallback_chip_readn, - .chip_writeb = noop_chip_writeb, - .chip_writew = fallback_chip_writew, - .chip_writel = fallback_chip_writel, - .chip_writen = fallback_chip_writen, .delay = internal_delay, }, #endif @@ -376,14 +240,6 @@ .init = satamv_init, .map_flash_region = fallback_map, .unmap_flash_region = fallback_unmap, - .chip_readb = satamv_chip_readb, - .chip_readw = fallback_chip_readw, - .chip_readl = fallback_chip_readl, - .chip_readn = fallback_chip_readn, - .chip_writeb = satamv_chip_writeb, - .chip_writew = fallback_chip_writew, - .chip_writel = fallback_chip_writel, - .chip_writen = fallback_chip_writen, .delay = internal_delay, }, #endif @@ -394,14 +250,6 @@ .init = linux_spi_init, .map_flash_region = fallback_map, .unmap_flash_region = fallback_unmap, - .chip_readb = noop_chip_readb, - .chip_readw = fallback_chip_readw, - .chip_readl = fallback_chip_readl, - .chip_readn = fallback_chip_readn, - .chip_writeb = noop_chip_writeb, - .chip_writew = fallback_chip_writew, - .chip_writel = fallback_chip_writel, - .chip_writen = fallback_chip_writen, .delay = internal_delay, }, #endif @@ -513,42 +361,42 @@ void chip_writeb(uint8_t val, chipaddr addr) { - programmer_table[programmer].chip_writeb(val, addr); + par_programmer->chip_writeb(val, addr); } void chip_writew(uint16_t val, chipaddr addr) { - programmer_table[programmer].chip_writew(val, addr); + par_programmer->chip_writew(val, addr); } void chip_writel(uint32_t val, chipaddr addr) { - programmer_table[programmer].chip_writel(val, addr); + par_programmer->chip_writel(val, addr); } void chip_writen(uint8_t *buf, chipaddr addr, size_t len) { - programmer_table[programmer].chip_writen(buf, addr, len); + par_programmer->chip_writen(buf, addr, len); } uint8_t chip_readb(const chipaddr addr) { - return programmer_table[programmer].chip_readb(addr); + return par_programmer->chip_readb(addr); } uint16_t chip_readw(const chipaddr addr) { - return programmer_table[programmer].chip_readw(addr); + return par_programmer->chip_readw(addr); } uint32_t chip_readl(const chipaddr addr) { - return programmer_table[programmer].chip_readl(addr); + return par_programmer->chip_readl(addr); } void chip_readn(uint8_t *buf, chipaddr addr, size_t len) { - programmer_table[programmer].chip_readn(buf, addr, len); + par_programmer->chip_readn(buf, addr, len); } void programmer_delay(int usecs) Modified: trunk/gfxnvidia.c ============================================================================== --- trunk/gfxnvidia.c Tue Nov 8 12:55:24 2011 (r1462) +++ trunk/gfxnvidia.c Thu Nov 10 00:40:00 2011 (r1463) @@ -61,6 +61,17 @@ {}, }; +static const struct par_programmer par_programmer_gfxnvidia = { + .chip_readb = gfxnvidia_chip_readb, + .chip_readw = fallback_chip_readw, + .chip_readl = fallback_chip_readl, + .chip_readn = fallback_chip_readn, + .chip_writeb = gfxnvidia_chip_writeb, + .chip_writew = fallback_chip_writew, + .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, +}; + static int gfxnvidia_shutdown(void *data) { physunmap(nvidia_bar, GFXNVIDIA_MEMMAP_SIZE); @@ -94,10 +105,9 @@ reg32 &= ~(1 << 0); rpci_write_long(pcidev_dev, 0x50, reg32); - buses_supported = BUS_PARALLEL; - /* Write/erase doesn't work. */ programmer_may_write = 0; + register_par_programmer(&par_programmer_gfxnvidia, BUS_PARALLEL); return 0; } Modified: trunk/ichspi.c ============================================================================== --- trunk/ichspi.c Tue Nov 8 12:55:24 2011 (r1462) +++ trunk/ichspi.c Thu Nov 10 00:40:00 2011 (r1463) @@ -1796,7 +1796,7 @@ ich_spibar = physmap("VT8237S MMIO registers", mmio_base, 0x70); /* Not sure if it speaks all these bus protocols. */ - buses_supported = BUS_LPC | BUS_FWH; + internal_buses_supported = BUS_LPC | BUS_FWH; ich_generation = CHIPSET_ICH7; register_spi_programmer(&spi_programmer_via); Modified: trunk/internal.c ============================================================================== --- trunk/internal.c Tue Nov 8 12:55:24 2011 (r1462) +++ trunk/internal.c Thu Nov 10 00:40:00 2011 (r1463) @@ -127,6 +127,19 @@ int is_laptop = 0; int laptop_ok = 0; +static const struct par_programmer par_programmer_internal = { + .chip_readb = internal_chip_readb, + .chip_readw = internal_chip_readw, + .chip_readl = internal_chip_readl, + .chip_readn = internal_chip_readn, + .chip_writeb = internal_chip_writeb, + .chip_writew = internal_chip_writew, + .chip_writel = internal_chip_writel, + .chip_writen = fallback_chip_writen, +}; + +enum chipbustype internal_buses_supported = BUS_NONE; + static int internal_shutdown(void *data) { release_io_perms(); @@ -191,9 +204,10 @@ return 1; /* Default to Parallel/LPC/FWH flash devices. If a known host controller - * is found, the init routine sets the buses_supported bitfield. + * is found, the host controller init routine sets the + * internal_buses_supported bitfield. */ - buses_supported = BUS_NONSPI; + internal_buses_supported = BUS_NONSPI; /* Initialize PCI access for flash enables */ pacc = pci_alloc(); /* Get the pci_access structure */ @@ -287,6 +301,7 @@ * Besides that, we don't check the board enable return code either. */ #if defined(__i386__) || defined(__x86_64__) || defined (__mips) + register_par_programmer(&par_programmer_internal, internal_buses_supported); return 0; #else msg_perr("Your platform is not supported yet for the internal " Modified: trunk/it85spi.c ============================================================================== --- trunk/it85spi.c Tue Nov 8 12:55:24 2011 (r1462) +++ trunk/it85spi.c Thu Nov 10 00:40:00 2011 (r1463) @@ -257,8 +257,10 @@ INDIRECT_A3(shm_io_base, (base >> 24)); #endif #ifdef LPC_MEMORY - base = (chipaddr)programmer_map_flash_region("it85 communication", - 0xFFFFF000, 0x1000); + /* FIXME: We should block accessing that region for anything else. + * Major TODO here, and it will be a lot of work. + */ + base = (chipaddr)physmap("it85 communication", 0xFFFFF000, 0x1000); msg_pdbg("%s():%d base=0x%08x\n", __func__, __LINE__, (unsigned int)base); ce_high = (unsigned char *)(base + 0xE00); /* 0xFFFFFE00 */ @@ -285,18 +287,26 @@ { int ret; - if (!(buses_supported & BUS_FWH)) { + if (!(internal_buses_supported & BUS_FWH)) { msg_pdbg("%s():%d buses not support FWH\n", __func__, __LINE__); return 1; } ret = it85xx_spi_common_init(s); msg_pdbg("FWH: %s():%d ret=%d\n", __func__, __LINE__, ret); if (!ret) { - msg_pdbg("%s():%d buses_supported=0x%x\n", __func__, __LINE__, - buses_supported); - if (buses_supported & BUS_FWH) - msg_pdbg("Overriding chipset SPI with IT85 FWH|SPI.\n"); - /* Really leave FWH enabled? */ + msg_pdbg("%s: internal_buses_supported=0x%x\n", __func__, + internal_buses_supported); + /* Check for FWH because IT85 listens to FWH cycles. + * FIXME: The big question is whether FWH cycles are necessary + * for communication even if LPC_IO is defined. + */ + if (internal_buses_supported & BUS_FWH) + msg_pdbg("Registering IT85 SPI.\n"); + /* FIXME: Really leave FWH enabled? We can't use this region + * anymore since accessing it would mess up IT85 communication. + * If we decide to disable FWH for this region, we should print + * a debug message about it. + */ /* Set this as SPI controller. */ register_spi_programmer(&spi_programmer_it85xx); } Modified: trunk/it87spi.c ============================================================================== --- trunk/it87spi.c Tue Nov 8 12:55:24 2011 (r1462) +++ trunk/it87spi.c Thu Nov 10 00:40:00 2011 (r1463) @@ -192,7 +192,7 @@ free(portpos); exit_conf_mode_ite(port); it8716f_flashport = flashport; - if (buses_supported & BUS_SPI) + if (internal_buses_supported & BUS_SPI) msg_pdbg("Overriding chipset SPI with IT87 SPI.\n"); /* FIXME: Add the SPI bus or replace the other buses with it? */ register_spi_programmer(&spi_programmer_it87xx); Modified: trunk/nic3com.c ============================================================================== --- trunk/nic3com.c Tue Nov 8 12:55:24 2011 (r1462) +++ trunk/nic3com.c Thu Nov 10 00:40:00 2011 (r1463) @@ -55,6 +55,17 @@ {}, }; +static const struct par_programmer par_programmer_nic3com = { + .chip_readb = nic3com_chip_readb, + .chip_readw = fallback_chip_readw, + .chip_readl = fallback_chip_readl, + .chip_readn = fallback_chip_readn, + .chip_writeb = nic3com_chip_writeb, + .chip_writew = fallback_chip_writew, + .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, +}; + static int nic3com_shutdown(void *data) { /* 3COM 3C90xB cards need a special fixup. */ @@ -96,11 +107,12 @@ */ OUTW(SELECT_REG_WINDOW + 0, io_base_addr + INT_STATUS); - buses_supported = BUS_PARALLEL; - max_rom_decode.parallel = 128 * 1024; - if (register_shutdown(nic3com_shutdown, NULL)) return 1; + + max_rom_decode.parallel = 128 * 1024; + register_par_programmer(&par_programmer_nic3com, BUS_PARALLEL); + return 0; } Modified: trunk/nicintel.c ============================================================================== --- trunk/nicintel.c Tue Nov 8 12:55:24 2011 (r1462) +++ trunk/nicintel.c Thu Nov 10 00:40:00 2011 (r1463) @@ -43,6 +43,17 @@ #define CSR_FCR 0x0c +static const struct par_programmer par_programmer_nicintel = { + .chip_readb = nicintel_chip_readb, + .chip_readw = fallback_chip_readw, + .chip_readl = fallback_chip_readl, + .chip_readn = fallback_chip_readn, + .chip_writeb = nicintel_chip_writeb, + .chip_writew = fallback_chip_writew, + .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, +}; + static int nicintel_shutdown(void *data) { physunmap(nicintel_control_bar, NICINTEL_CONTROL_MEMMAP_SIZE); @@ -93,9 +104,8 @@ */ pci_rmmio_writew(0x0001, nicintel_control_bar + CSR_FCR); - buses_supported = BUS_PARALLEL; - max_rom_decode.parallel = NICINTEL_MEMMAP_SIZE; + register_par_programmer(&par_programmer_nicintel, BUS_PARALLEL); return 0; Modified: trunk/nicnatsemi.c ============================================================================== --- trunk/nicnatsemi.c Tue Nov 8 12:55:24 2011 (r1462) +++ trunk/nicnatsemi.c Thu Nov 10 00:40:00 2011 (r1463) @@ -35,6 +35,17 @@ {}, }; +static const struct par_programmer par_programmer_nicnatsemi = { + .chip_readb = nicnatsemi_chip_readb, + .chip_readw = fallback_chip_readw, + .chip_readl = fallback_chip_readl, + .chip_readn = fallback_chip_readn, + .chip_writeb = nicnatsemi_chip_writeb, + .chip_writew = fallback_chip_writew, + .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, +}; + static int nicnatsemi_shutdown(void *data) { pci_cleanup(pacc); @@ -48,7 +59,8 @@ io_base_addr = pcidev_init(PCI_BASE_ADDRESS_0, nics_natsemi); - buses_supported = BUS_PARALLEL; + if (register_shutdown(nicnatsemi_shutdown, NULL)) + return 1; /* The datasheet shows address lines MA0-MA16 in one place and MA0-MA15 * in another. My NIC has MA16 connected to A16 on the boot ROM socket @@ -57,9 +69,8 @@ * functions below wants to be 0x0000FFFF. */ max_rom_decode.parallel = 131072; + register_par_programmer(&par_programmer_nicnatsemi, BUS_PARALLEL); - if (register_shutdown(nicnatsemi_shutdown, NULL)) - return 1; return 0; } Modified: trunk/nicrealtek.c ============================================================================== --- trunk/nicrealtek.c Tue Nov 8 12:55:24 2011 (r1462) +++ trunk/nicrealtek.c Thu Nov 10 00:40:00 2011 (r1463) @@ -36,6 +36,17 @@ {}, }; +static const struct par_programmer par_programmer_nicrealtek = { + .chip_readb = nicrealtek_chip_readb, + .chip_readw = fallback_chip_readw, + .chip_readl = fallback_chip_readl, + .chip_readn = fallback_chip_readn, + .chip_writeb = nicrealtek_chip_writeb, + .chip_writew = fallback_chip_writew, + .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, +}; + static int nicrealtek_shutdown(void *data) { /* FIXME: We forgot to disable software access again. */ @@ -50,10 +61,11 @@ io_base_addr = pcidev_init(PCI_BASE_ADDRESS_0, nics_realtek); - buses_supported = BUS_PARALLEL; - if (register_shutdown(nicrealtek_shutdown, NULL)) return 1; + + register_par_programmer(&par_programmer_nicrealtek, BUS_PARALLEL); + return 0; } Modified: trunk/programmer.c ============================================================================== --- trunk/programmer.c Tue Nov 8 12:55:24 2011 (r1462) +++ trunk/programmer.c Thu Nov 10 00:40:00 2011 (r1463) @@ -19,6 +19,20 @@ */ #include "flash.h" +#include "programmer.h" + +static const struct par_programmer par_programmer_none = { + .chip_readb = noop_chip_readb, + .chip_readw = fallback_chip_readw, + .chip_readl = fallback_chip_readl, + .chip_readn = fallback_chip_readn, + .chip_writeb = noop_chip_writeb, + .chip_writew = fallback_chip_writew, + .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, +}; + +const struct par_programmer *par_programmer = &par_programmer_none; /* No-op shutdown() for programmers which don't need special handling */ int noop_shutdown(void) @@ -96,3 +110,9 @@ buf[i] = chip_readb(addr + i); return; } + +void register_par_programmer(const struct par_programmer *pgm, const enum chipbustype buses) +{ + par_programmer = pgm; + buses_supported |= buses; +} Modified: trunk/programmer.h ============================================================================== --- trunk/programmer.h Tue Nov 8 12:55:24 2011 (r1462) +++ trunk/programmer.h Thu Nov 10 00:40:00 2011 (r1463) @@ -97,14 +97,6 @@ size_t len); void (*unmap_flash_region) (void *virt_addr, size_t len); - void (*chip_writeb) (uint8_t val, chipaddr addr); - void (*chip_writew) (uint16_t val, chipaddr addr); - void (*chip_writel) (uint32_t val, chipaddr addr); - void (*chip_writen) (uint8_t *buf, chipaddr addr, size_t len); - uint8_t (*chip_readb) (const chipaddr addr); - uint16_t (*chip_readw) (const chipaddr addr); - uint32_t (*chip_readl) (const chipaddr addr); - void (*chip_readn) (uint8_t *buf, const chipaddr addr, size_t len); void (*delay) (int usecs); }; @@ -306,6 +298,7 @@ extern int force_boardmismatch; void probe_superio(void); int register_superio(struct superio s); +extern enum chipbustype internal_buses_supported; int internal_init(void); void internal_chip_writeb(uint8_t val, chipaddr addr); void internal_chip_writew(uint16_t val, chipaddr addr); @@ -360,6 +353,18 @@ uint16_t fallback_chip_readw(const chipaddr addr); uint32_t fallback_chip_readl(const chipaddr addr); void fallback_chip_readn(uint8_t *buf, const chipaddr addr, size_t len); +struct par_programmer { + void (*chip_writeb) (uint8_t val, chipaddr addr); + void (*chip_writew) (uint16_t val, chipaddr addr); + void (*chip_writel) (uint32_t val, chipaddr addr); + void (*chip_writen) (uint8_t *buf, chipaddr addr, size_t len); + uint8_t (*chip_readb) (const chipaddr addr); + uint16_t (*chip_readw) (const chipaddr addr); + uint32_t (*chip_readl) (const chipaddr addr); + void (*chip_readn) (uint8_t *buf, const chipaddr addr, size_t len); +}; +extern const struct par_programmer *par_programmer; +void register_par_programmer(const struct par_programmer *pgm, const enum chipbustype buses); /* dummyflasher.c */ #if CONFIG_DUMMY == 1 @@ -634,10 +639,6 @@ uint8_t serprog_chip_readb(const chipaddr addr); void serprog_chip_readn(uint8_t *buf, const chipaddr addr, size_t len); void serprog_delay(int usecs); -int serprog_spi_send_command(unsigned int writecnt, unsigned int readcnt, - const unsigned char *writearr, - unsigned char *readarr); -int serprog_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); #endif /* serial.c */ Modified: trunk/satamv.c ============================================================================== --- trunk/satamv.c Tue Nov 8 12:55:24 2011 (r1462) +++ trunk/satamv.c Thu Nov 10 00:40:00 2011 (r1463) @@ -41,6 +41,17 @@ #define PCI_BAR2_CONTROL 0x00c08 #define GPIO_PORT_CONTROL 0x104f0 +static const struct par_programmer par_programmer_satamv = { + .chip_readb = satamv_chip_readb, + .chip_readw = fallback_chip_readw, + .chip_readl = fallback_chip_readl, + .chip_readn = fallback_chip_readn, + .chip_writeb = satamv_chip_writeb, + .chip_writew = fallback_chip_writew, + .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, +}; + static int satamv_shutdown(void *data) { physunmap(mv_bar, 0x20000); @@ -137,11 +148,10 @@ mv_iobar = tmp & 0xffff; msg_pspew("Activating I/O BAR at 0x%04x\n", mv_iobar); - buses_supported = BUS_PARALLEL; - /* 512 kByte with two 8-bit latches, and * 4 MByte with additional 3-bit latch. */ max_rom_decode.parallel = 4 * 1024 * 1024; + register_par_programmer(&par_programmer_satamv, BUS_PARALLEL); return 0; Modified: trunk/satasii.c ============================================================================== --- trunk/satasii.c Tue Nov 8 12:55:24 2011 (r1462) +++ trunk/satasii.c Thu Nov 10 00:40:00 2011 (r1463) @@ -42,6 +42,17 @@ {}, }; +static const struct par_programmer par_programmer_satasii = { + .chip_readb = satasii_chip_readb, + .chip_readw = fallback_chip_readw, + .chip_readl = fallback_chip_readl, + .chip_readn = fallback_chip_readn, + .chip_writeb = satasii_chip_writeb, + .chip_writew = fallback_chip_writew, + .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, +}; + static int satasii_shutdown(void *data) { physunmap(sii_bar, SATASII_MEMMAP_SIZE); @@ -76,10 +87,11 @@ if ((id != 0x0680) && (!(pci_mmio_readl(sii_bar) & (1 << 26)))) msg_pinfo("Warning: Flash seems unconnected.\n"); - buses_supported = BUS_PARALLEL; - if (register_shutdown(satasii_shutdown, NULL)) return 1; + + register_par_programmer(&par_programmer_satasii, BUS_PARALLEL); + return 0; } Modified: trunk/serprog.c ============================================================================== --- trunk/serprog.c Tue Nov 8 12:55:24 2011 (r1462) +++ trunk/serprog.c Thu Nov 10 00:40:00 2011 (r1463) @@ -299,6 +299,11 @@ return 0; } +static int serprog_spi_send_command(unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr, + unsigned char *readarr); +static int serprog_spi_read(struct flashchip *flash, uint8_t *buf, int start, + int len); static struct spi_programmer spi_programmer_serprog = { .type = SPI_CONTROLLER_SERPROG, .max_data_read = MAX_DATA_READ_UNLIMITED, @@ -309,6 +314,19 @@ .write_256 = default_spi_write_256, }; +static const struct par_programmer par_programmer_serprog = { + .chip_readb = serprog_chip_readb, + .chip_readw = fallback_chip_readw, + .chip_readl = fallback_chip_readl, + .chip_readn = serprog_chip_readn, + .chip_writeb = serprog_chip_writeb, + .chip_writew = fallback_chip_writew, + .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, +}; + +static enum chipbustype serprog_buses_supported = BUS_NONE; + int serprog_init(void) { uint16_t iface; @@ -400,41 +418,45 @@ if (sp_docommand(S_CMD_Q_IFACE, 0, NULL, 2, &iface)) { msg_perr("Error: NAK to query interface version\n"); - exit(1); + return 1; } if (iface != 1) { msg_perr("Error: Unknown interface version: %d\n", iface); - exit(1); + return 1; } msg_pdbg(MSGHEADER "Interface version ok.\n"); if (sp_docommand(S_CMD_Q_CMDMAP, 0, NULL, 32, sp_cmdmap)) { msg_perr("Error: query command map not supported\n"); - exit(1); + return 1; } sp_check_avail_automatic = 1; - + /* FIXME: This assumes that serprog device bustypes are always + * identical with flashrom bustype enums and that they all fit + * in a single byte. + */ if (sp_docommand(S_CMD_Q_BUSTYPE, 0, NULL, 1, &c)) { msg_perr("Warning: NAK to query supported buses\n"); c = BUS_NONSPI; /* A reasonable default for now. */ } - buses_supported = c; + serprog_buses_supported = c; + msg_pdbg(MSGHEADER "Bus support: parallel=%s, LPC=%s, FWH=%s, SPI=%s\n", (c & BUS_PARALLEL) ? "on" : "off", (c & BUS_LPC) ? "on" : "off", (c & BUS_FWH) ? "on" : "off", (c & BUS_SPI) ? "on" : "off"); /* Check for the minimum operational set of commands. */ - if (buses_supported & BUS_SPI) { + if (serprog_buses_supported & BUS_SPI) { uint8_t bt = BUS_SPI; if (sp_check_commandavail(S_CMD_O_SPIOP) == 0) { msg_perr("Error: SPI operation not supported while the " "bustype is SPI\n"); - exit(1); + return 1; } /* Success of any of these commands is optional. We don't need the programmer to tell us its limits, but if it doesn't, we @@ -461,40 +483,39 @@ spi_programmer_serprog.max_data_read = v; msg_pdbg(MSGHEADER "Maximum read-n length is %d\n", v); } - bt = buses_supported; + bt = serprog_buses_supported; sp_docommand(S_CMD_S_BUSTYPE, 1, &bt, 0, NULL); - register_spi_programmer(&spi_programmer_serprog); } - if (buses_supported & BUS_NONSPI) { + if (serprog_buses_supported & BUS_NONSPI) { if (sp_check_commandavail(S_CMD_O_INIT) == 0) { msg_perr("Error: Initialize operation buffer " "not supported\n"); - exit(1); + return 1; } if (sp_check_commandavail(S_CMD_O_DELAY) == 0) { msg_perr("Error: Write to opbuf: " "delay not supported\n"); - exit(1); + return 1; } /* S_CMD_O_EXEC availability checked later. */ if (sp_check_commandavail(S_CMD_R_BYTE) == 0) { msg_perr("Error: Single byte read not supported\n"); - exit(1); + return 1; } /* This could be translated to single byte reads (if missing), * but now we don't support that. */ if (sp_check_commandavail(S_CMD_R_NBYTES) == 0) { msg_perr("Error: Read n bytes not supported\n"); - exit(1); + return 1; } if (sp_check_commandavail(S_CMD_O_WRITEB) == 0) { msg_perr("Error: Write to opbuf: " "write byte not supported\n"); - exit(1); + return 1; } if (sp_docommand(S_CMD_Q_WRNMAXLEN, 0, NULL, 3, rbuf)) { @@ -513,7 +534,7 @@ if (!sp_write_n_buf) { msg_perr("Error: cannot allocate memory for " "Write-n buffer\n"); - exit(1); + return 1; } sp_write_n_bytes = 0; } @@ -551,12 +572,12 @@ if (sp_check_commandavail(S_CMD_O_EXEC) == 0) { msg_perr("Error: Execute operation buffer not " "supported\n"); - exit(1); + return 1; } if (sp_docommand(S_CMD_O_INIT, 0, NULL, 0, NULL)) { msg_perr("Error: NAK to initialize operation buffer\n"); - exit(1); + return 1; } if (sp_docommand(S_CMD_Q_OPBUF, 0, NULL, 2, @@ -572,6 +593,11 @@ sp_streamed_transmit_ops = 0; sp_streamed_transmit_bytes = 0; sp_opbuf_usage = 0; + if (serprog_buses_supported & BUS_SPI) + register_spi_programmer(&spi_programmer_serprog); + if (serprog_buses_supported & BUS_NONSPI) + register_par_programmer(&par_programmer_serprog, + serprog_buses_supported & BUS_NONSPI); return 0; } @@ -766,7 +792,7 @@ sp_prev_was_write = 0; } -int serprog_spi_send_command(unsigned int writecnt, unsigned int readcnt, +static int serprog_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { @@ -796,7 +822,7 @@ * the advantage that it is much faster for most chips, but breaks those with * non-contiguous address space (like AT45DB161D). When spi_read_chunked is * fixed this method can be removed. */ -int serprog_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) +static int serprog_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) { int i; int cur_len; Modified: trunk/wbsio_spi.c ============================================================================== --- trunk/wbsio_spi.c Tue Nov 8 12:55:24 2011 (r1462) +++ trunk/wbsio_spi.c Thu Nov 10 00:40:00 2011 (r1463) @@ -82,10 +82,10 @@ msg_pspew("\nwbsio_spibase = 0x%x\n", wbsio_spibase); - register_spi_programmer(&spi_programmer_wbsio); msg_pdbg("%s: Winbond saved on 4 register bits so max chip size is " "1024 kB!\n", __func__); max_rom_decode.spi = 1024 * 1024; + register_spi_programmer(&spi_programmer_wbsio); return 0; } From c-d.hailfinger.devel.2006 at gmx.net Thu Nov 10 00:47:36 2011 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Thu, 10 Nov 2011 00:47:36 +0100 Subject: [flashrom] [PATCH] Register Parallel/LPC/FWH programmers In-Reply-To: <1320877182.12407.45.camel@localhost> References: <4DEDCE84.8020400@gmx.net> <4E6808CE.7010906@gmx.net> <201109082137.p88Lb3DF014751@mail2.student.tuwien.ac.at> <4E6A5322.8070003@gmx.net> <4EB7E17E.6070001@gmx.net> <1320877182.12407.45.camel@localhost> Message-ID: <4EBB1118.8020606@gmx.net> Am 09.11.2011 23:19 schrieb Michael Karcher: > Am Montag, den 07.11.2011, 14:47 +0100 schrieb Carl-Daniel Hailfinger: >>>>> - Should register_par_programmer(...) be called before or after setting >>>>> max_rom_decode.*? >>>> why is that not a field in the different programmer structs (yet?)? >>> Supply it as >>> register_par_programmer() parameter and extend register_spi_programmer >>> to accept that parameter as well? >> I'm now setting max_rom_decode before calling register_par_programmer. >> Given that such restrictions may exist for any programmer, I'll postpone >> handling max_rom_decode to the universal programmer registration patch >> where we get the infrastructure to deal with such programmer >> limitations. If you have any objections, please tell me. > As we are heading strongly towards having a dynamic list of programmers, > and there might even be two SPI programmers with different max decode > size, storing it with the programmer structure seems like the only sane > option. Having the registeration function fill a field in the dynamic > programmer structure using a parameter is one sensible choice to get > that field populated. Indeed, that's the plan. I'll post a followup patch for this. >>>>> - Is there a better name for register_par_programmer? >>>>> >>>> register_parallel_programmer ofc, and imho it is not too long, because >>>> it is seldom used, but i don't care that much (due to the same reason). >>>> >>> 80 column limit... I think that was one of the reasons we used a shorter >>> name. > I am not really convinced "parallel" is to the point. While even LPC/FWH > is still using 4 bits in parallel, the real distinction between > parallel/LPC/FWH and SPI is that parallel/LPC/FWH is pushing commands > through a memory read/write interface, while SPI pushes memory > read/writes through a command interface. (At least if you look at the > layer of abstraction applying to flashrom) > > But "register_memcycle_programmer" is most likely something people are > not going to understand, although, looking at the contents of your > par_programmer structure, all the functions really are about memory > cylces. There are three types of programmers: In-band commands (Parallel/LPC/FWH) Out-of-band commands (SPI/I2C) Opaque programmers (ICH HWSeq) All in-band programmers have a common way to interface with the flash chip. Sharing a common registration function makes sense, and I'm not too happy with the name "par" either. Admittedly people outside the x86 world usually know only Parallel flash and SPI flash, so for them a name referencing parallel flash is easiest to understand. OTOH, we could use "ib" or "inband" instead of "par", but I'm not sure if that is understood more easily. Out-of-band programmers all share a command submission mechanism which is used for all accesses, but the mechanism differs between SPI and I2C (and even between classic single-IO SPI and the new dual-/quad-IO SPI). Thus a common registration function for SPI and I2C would be difficult. Fortunately we don't support I2C yet. >> max_rom_decode is conceptually different from buses_supported although >> that was not obvious when I wrote the paragraph above. It will be >> handled in the universal programmer registration patch. > In the end, I don't even think we need buses_supported outside of the > classic/memcycle/parallel programmer (however you call it), because SPI > interface chips just support spi flash chips, and for opaque programmers > we even had to introduce a fake bus type. In the future, probing will be registered-programmer-centric (i.e. walk the registered-programmer list, and for each registered programmer walk the flash chip list) and buses_supported will be a per-registered-programmer field used to match chips with compatible buses during probing. Probing doesn't care about the bus type except for determining compatible chips. > Maximum supported chip size on the other hand is a concept that likely > applies sensibly apply to every type of programmer. Indeed. >>>>> - Should map_flash_region/unmap_flash_region be part of the registration? >>>> no idea what that does exactly :P >>> It makes the flash chip accessible. This is essentially physmap for >>> programmers with memory mapped flash and a no-op for everything else. > If the idea of a future flashrom (or libflashrom) is that you scan the > system for programmers and build a table from the registrations, then I > don't think you really want to initialize the hardware/map the memory at > the time of registration further than needed for detection, but you need > a hardware startup callback in the programmer. That's the idea. map_flash_region is only called during flash chip probing and not during programmer probing/registration. > [drkaiser] >> + >> + max_rom_decode.parallel = 131072; > "128 * 1024" to comply with the flashrom style? Fixed. >> + /* FIXME: This assumes that serprog device bustypes are always >> + * identical with flashrom bustype enums and that they all fit >> + * in a single byte. >> + */ > I guess that is how the serprog protocol is "specified" ;) Heh, yes. >> Index: flashrom-register_par_programmer/it85spi.c >> =================================================================== >> --- flashrom-register_par_programmer/it85spi.c (Revision 1460) >> +++ flashrom-register_par_programmer/it85spi.c (Arbeitskopie) >> @@ -257,8 +257,10 @@ >> INDIRECT_A3(shm_io_base, (base >> 24)); >> #endif >> #ifdef LPC_MEMORY >> - base = (chipaddr)programmer_map_flash_region("it85 communication", >> - 0xFFFFF000, 0x1000); >> + /* FIXME: We should block accessing that region for anything else. >> + * Major TODO here, and it will be a lot of work. >> + */ > "blocking it for anything else" just means disabling the > "classic/parallel" interface of the internal programmer, if I understand > it correctly, so... Not necessarily. If there are multiple flash chips on a board, e.g. a 512 kByte SPI chip behind IT85 SPI translation and a 512 kByte FWH chip attached to the southbridge and if the SPI chip is mapped at 4G-512k to 4G and the FWH chip is mapped in the region 4G-1M to 4G-512k, no conflict arises as long as FWH probing does not touch the top 512 kB. A possible solution would be replacing physmap in programmer_map_flash_region and in IT85 with a variant exclusive_physmap which refuses mapping if another exclusive mapping exists in the same region. >> + /* FIXME: Really leave FWH enabled? We can't use this region >> + * anymore since accessing it would mess up IT85 communication. >> + * If we decide to disable FWH for this region, we should print >> + * a debug message about it. >> + */ > ... of course FWH/LPC/Parallel needs to be turned off here. I hope this > code verifies that the IT85 SPI flash translator is really enabled, > before concluding this. I'll try to get Google to merge their current IT85 SPI code into mainline flashrom and then fix any issues which still arise. To be honest, picking LPC_IO instead of LPC_MEMORY would solve the whole problem without introducing any conflicts, but that would also need cooperation from the IT85 chip to disable listening to LPC memory cycles for its command interface. > Looks fine so far. So go ahead and commit. > > Acked-By: Michael Karcher Thanks a lot. Committed in r1463. Regards, Carl-Daniel -- http://www.hailfinger.org/ From paulepanter at users.sourceforge.net Thu Nov 10 16:24:23 2011 From: paulepanter at users.sourceforge.net (Paul Menzel) Date: Thu, 10 Nov 2011 16:24:23 +0100 Subject: [flashrom] GeForce7050M-M: unsupported chip with flashrom v0.9.2-r1141 In-Reply-To: <1320847475.2721.15.camel@debian.fritz.box> References: <1320847475.2721.15.camel@debian.fritz.box> Message-ID: <1320938663.28328.2.camel@mattotaupa> Dear Alexander, thank you for your report. Am Mittwoch, den 09.11.2011, 15:04 +0100 schrieb Alexander Kaupp: > flashrom v0.9.2-r1141 on Linux 2.6.32-5-amd64 (x86_64), built with > libpci 3.1.7, GCC 4.4.5 20100728 (prerelease), little endian > flashrom is free software, get the source code at > http://www.flashrom.org > > Calibrating delay loop... OS timer resolution is 1 usecs, 974M loops per > second, 10 myus = 10 us, 100 myus = 99 us, 1000 myus = 978 us, 10000 > myus = 10287 us, 4 myus = 4 us, OK. > Initializing internal programmer > No coreboot table found. > DMI string system-manufacturer: "ECS" > DMI string system-product-name: "GeForce7050M-M" > DMI string system-version: "1.0 " > DMI string baseboard-manufacturer: "ECS" > DMI string baseboard-product-name: "GeForce7050M-M" > DMI string baseboard-version: "1.0 " > DMI string chassis-type: "Desktop" > Found ITE Super I/O, id 8726 > Found chipset "NVIDIA MCP67", enabling flash write... chipset PCI ID is > 10de:0548, This chipset is not really supported yet. Guesswork... > ISA/LPC bridge reg 0x8a contents: 0x40, bit 6 is 1, bit 5 is 0 > Flash bus type is SPI > Found SMBus device 10de:0542 at 00:01:1 > MCP SPI BAR is at 0xfec80000 > SPI control is 0xc012, req=0, gnt=0 > Please send the output of "flashrom -V" to flashrom at flashrom.org to help > us finish support for your chipset. Thanks. The version you are using is quite old. Please use version 0.9.4 or the latest stuff from the repository. Installation is quite easy [1]. [?] Thanks, Paul [1] http://flashrom.org/Downloads -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 198 bytes Desc: This is a digitally signed message part URL: From c-d.hailfinger.devel.2006 at gmx.net Fri Nov 11 07:42:44 2011 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Fri, 11 Nov 2011 07:42:44 +0100 Subject: [flashrom] [PATCH] generic programmer registration Message-ID: <4EBCC3E4.9060501@gmx.net> Please note that this patch breaks every programmer except hwseq because we're not passing struct flashchip around yet. To get this working, the following changes have to be made: - Pass struct flashchip * everywhere (or struct flashctx *), see my other patch for that - Change parallel-style and SPI programmers to use flash->pgm... instead of par_programmer->... and spi_programmer->... This compiles and should help you review it, but it is not for merge until the "struct flashchip * everywhere" patch is in. Some code has been removed with #if 0 because I wanted to discuss removing it. The final patch will have no #if 0 at all. Signed-off-by: Carl-Daniel Hailfinger Index: flashrom-register_all_programmers_register_generic/flash.h =================================================================== --- flashrom-register_all_programmers_register_generic/flash.h (Revision 1463) +++ flashrom-register_all_programmers_register_generic/flash.h (Arbeitskopie) @@ -153,6 +153,7 @@ /* Some flash devices have an additional register space. */ chipaddr virtual_memory; chipaddr virtual_registers; + struct registered_programmer *pgm; }; #define TEST_UNTESTED 0 @@ -197,14 +198,13 @@ write_gran_1byte, write_gran_256bytes, }; -extern enum chipbustype buses_supported; extern int verbose; extern const char flashrom_version[]; extern char *chip_to_probe; void map_flash_registers(struct flashchip *flash); int read_memmapped(struct flashchip *flash, uint8_t *buf, int start, int len); int erase_flash(struct flashchip *flash); -int probe_flash(int startchip, struct flashchip *fill_flash, int force); +int probe_flash(struct registered_programmer *pgm, int startchip, struct flashchip *fill_flash, int force); int read_flash_to_file(struct flashchip *flash, const char *filename); int min(int a, int b); int max(int a, int b); @@ -271,4 +271,5 @@ int spi_send_multicommand(struct spi_command *cmds); uint32_t spi_get_valid_read_addr(void); +enum chipbustype get_buses_supported(void); #endif /* !__FLASH_H__ */ Index: flashrom-register_all_programmers_register_generic/cli_classic.c =================================================================== --- flashrom-register_all_programmers_register_generic/cli_classic.c (Revision 1463) +++ flashrom-register_all_programmers_register_generic/cli_classic.c (Arbeitskopie) @@ -172,7 +172,7 @@ struct flashchip flashes[3]; struct flashchip *fill_flash; const char *name; - int namelen, opt, i; + int namelen, opt, i, j; int startchip = 0, chipcount = 0, option_index = 0, force = 0; #if CONFIG_PRINT_WIKI == 1 int list_supported_wiki = 0; @@ -443,17 +443,21 @@ ret = 1; goto out_shutdown; } - tempstr = flashbuses_to_text(buses_supported); + tempstr = flashbuses_to_text(get_buses_supported()); msg_pdbg("This programmer supports the following protocols: %s.\n", tempstr); free(tempstr); - for (i = 0; i < ARRAY_SIZE(flashes); i++) { - startchip = probe_flash(startchip, &flashes[i], 0); - if (startchip == -1) - break; - chipcount++; - startchip++; + for (j = 0; j < registered_programmer_count; j++) { + startchip = 0; + for (i = 0; i < ARRAY_SIZE(flashes); i++) { + startchip = probe_flash(®istered_programmers[j], + startchip, &flashes[i], 0); + if (startchip == -1) + break; + chipcount++; + startchip++; + } } if (chipcount > 1) { @@ -471,6 +475,7 @@ printf("Note: flashrom can never write if the flash " "chip isn't found automatically.\n"); } +#if 0 // FIXME: What happens for a forced chip read if multiple compatible programmers are registered? if (force && read_it && chip_to_probe) { printf("Force read (-f -r -c) requested, pretending " "the chip is there:\n"); @@ -485,6 +490,7 @@ "contain garbage.\n"); return read_flash_to_file(&flashes[0], filename); } +#endif ret = 1; goto out_shutdown; } else if (!chip_to_probe) { @@ -501,7 +507,7 @@ check_chip_supported(fill_flash); size = fill_flash->total_size * 1024; - if (check_max_decode((buses_supported & fill_flash->bustype), size) && + if (check_max_decode((get_buses_supported() & fill_flash->bustype), size) && (!force)) { fprintf(stderr, "Chip is too big for this programmer " "(-V gives details). Use --force to override.\n"); Index: flashrom-register_all_programmers_register_generic/ichspi.c =================================================================== --- flashrom-register_all_programmers_register_generic/ichspi.c (Revision 1463) +++ flashrom-register_all_programmers_register_generic/ichspi.c (Arbeitskopie) @@ -1295,7 +1295,7 @@ REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS)); while (len > 0) { - block_len = min(len, opaque_programmer->max_data_read); + block_len = min(len, flash->pgm->opaque.max_data_read); ich_hwseq_set_addr(addr); hsfc = REGREAD16(ICH9_REG_HSFC); hsfc &= ~HSFC_FCYCLE; /* set read operation */ @@ -1333,7 +1333,7 @@ while (len > 0) { ich_hwseq_set_addr(addr); - block_len = min(len, opaque_programmer->max_data_write); + block_len = min(len, flash->pgm->opaque.max_data_write); ich_fill_data(buf, block_len, ICH9_REG_FDATA0); hsfc = REGREAD16(ICH9_REG_HSFC); hsfc &= ~HSFC_FCYCLE; /* clear operation */ Index: flashrom-register_all_programmers_register_generic/opaque.c =================================================================== --- flashrom-register_all_programmers_register_generic/opaque.c (Revision 1463) +++ flashrom-register_all_programmers_register_generic/opaque.c (Arbeitskopie) @@ -30,70 +30,62 @@ #include "chipdrivers.h" #include "programmer.h" -const struct opaque_programmer opaque_programmer_none = { - .max_data_read = MAX_DATA_UNSPECIFIED, - .max_data_write = MAX_DATA_UNSPECIFIED, - .probe = NULL, - .read = NULL, - .write = NULL, - .erase = NULL, -}; - -const struct opaque_programmer *opaque_programmer = &opaque_programmer_none; - int probe_opaque(struct flashchip *flash) { - if (!opaque_programmer->probe) { + if (!flash->pgm->opaque.probe) { msg_perr("%s called before register_opaque_programmer. " "Please report a bug at flashrom at flashrom.org\n", __func__); return 0; } - return opaque_programmer->probe(flash); + return flash->pgm->opaque.probe(flash); } int read_opaque(struct flashchip *flash, uint8_t *buf, int start, int len) { - if (!opaque_programmer->read) { + if (!flash->pgm->opaque.read) { msg_perr("%s called before register_opaque_programmer. " "Please report a bug at flashrom at flashrom.org\n", __func__); return 1; } - return opaque_programmer->read(flash, buf, start, len); + return flash->pgm->opaque.read(flash, buf, start, len); } int write_opaque(struct flashchip *flash, uint8_t *buf, int start, int len) { - if (!opaque_programmer->write) { + if (!flash->pgm->opaque.write) { msg_perr("%s called before register_opaque_programmer. " "Please report a bug at flashrom at flashrom.org\n", __func__); return 1; } - return opaque_programmer->write(flash, buf, start, len); + return flash->pgm->opaque.write(flash, buf, start, len); } int erase_opaque(struct flashchip *flash, unsigned int blockaddr, unsigned int blocklen) { - if (!opaque_programmer->erase) { + if (!flash->pgm->opaque.erase) { msg_perr("%s called before register_opaque_programmer. " "Please report a bug at flashrom at flashrom.org\n", __func__); return 1; } - return opaque_programmer->erase(flash, blockaddr, blocklen); + return flash->pgm->opaque.erase(flash, blockaddr, blocklen); } void register_opaque_programmer(const struct opaque_programmer *pgm) { + struct registered_programmer rpgm; + if (!pgm->probe || !pgm->read || !pgm->write || !pgm->erase) { msg_perr("%s called with one of probe/read/write/erase being " "NULL. Please report a bug at flashrom at flashrom.org\n", __func__); return; } - opaque_programmer = pgm; - buses_supported |= BUS_PROG; + rpgm.buses_supported = BUS_PROG; + rpgm.opaque = *pgm; + register_programmer(&rpgm); } Index: flashrom-register_all_programmers_register_generic/spi.c =================================================================== --- flashrom-register_all_programmers_register_generic/spi.c (Revision 1463) +++ flashrom-register_all_programmers_register_generic/spi.c (Arbeitskopie) @@ -194,6 +194,9 @@ void register_spi_programmer(const struct spi_programmer *pgm) { - spi_programmer = pgm; - buses_supported |= BUS_SPI; + struct registered_programmer rpgm; + + rpgm.buses_supported = BUS_SPI; + rpgm.spi = *pgm; + register_programmer(&rpgm); } Index: flashrom-register_all_programmers_register_generic/programmer.c =================================================================== --- flashrom-register_all_programmers_register_generic/programmer.c (Revision 1463) +++ flashrom-register_all_programmers_register_generic/programmer.c (Arbeitskopie) @@ -1,7 +1,7 @@ /* * This file is part of the flashrom project. * - * Copyright (C) 2009,2010 Carl-Daniel Hailfinger + * Copyright (C) 2009,2010,2011 Carl-Daniel Hailfinger * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -113,6 +113,38 @@ void register_par_programmer(const struct par_programmer *pgm, const enum chipbustype buses) { - par_programmer = pgm; - buses_supported |= buses; + struct registered_programmer rpgm; + + rpgm.buses_supported = buses; + rpgm.par = *pgm; + register_programmer(&rpgm); } + +/* The limit of 4 is totally arbitrary. */ +#define PROGRAMMERS_MAX 4 +struct registered_programmer registered_programmers[PROGRAMMERS_MAX]; +int registered_programmer_count = 0; + +int register_programmer(struct registered_programmer *pgm) +{ + if (registered_programmer_count >= PROGRAMMERS_MAX) { + msg_perr("Tried to register more than %i programmer " + "interfaces.\n", PROGRAMMERS_MAX); + return 1; + } + registered_programmers[registered_programmer_count] = *pgm; + registered_programmer_count++; + + return 0; +} + +enum chipbustype get_buses_supported(void) +{ + int i; + enum chipbustype ret = BUS_NONE; + + for (i = 0; i < registered_programmer_count; i++) + ret |= registered_programmers[i].buses_supported; + + return ret; +} Index: flashrom-register_all_programmers_register_generic/flashrom.c =================================================================== --- flashrom-register_all_programmers_register_generic/flashrom.c (Revision 1463) +++ flashrom-register_all_programmers_register_generic/flashrom.c (Arbeitskopie) @@ -46,9 +46,6 @@ static char *programmer_param = NULL; -/* Supported buses for the current programmer. */ -enum chipbustype buses_supported; - /* * Programmers supporting multiple buses can have differing size limits on * each bus. Store the limits for each bus in a common struct. @@ -314,7 +311,6 @@ .fwh = 0xffffffff, .spi = 0xffffffff, }; - buses_supported = BUS_NONE; /* Default to top aligned flash at 4 GB. */ flashbase = 0; /* Registering shutdown functions is now allowed. */ @@ -936,7 +932,8 @@ return 1; } -int probe_flash(int startchip, struct flashchip *fill_flash, int force) +int probe_flash(struct registered_programmer *pgm, int startchip, + struct flashchip *fill_flash, int force) { const struct flashchip *flash; unsigned long base = 0; @@ -948,11 +945,12 @@ for (flash = flashchips + startchip; flash && flash->name; flash++) { if (chip_to_probe && strcmp(flash->name, chip_to_probe) != 0) continue; - buses_common = buses_supported & flash->bustype; + buses_common = pgm->buses_supported & flash->bustype; if (!buses_common) { +#if 0 // Does not really make sense anymore if we use a programmer-centric walk. msg_gspew("Probing for %s %s, %d kB: skipped. ", flash->vendor, flash->name, flash->total_size); - tmp = flashbuses_to_text(buses_supported); + tmp = flashbuses_to_text(get_buses_supported()); msg_gspew("Host bus type %s ", tmp); free(tmp); tmp = flashbuses_to_text(flash->bustype); @@ -960,6 +958,7 @@ tmp); free(tmp); msg_gspew("\n"); +#endif continue; } msg_gdbg("Probing for %s %s, %d kB: ", @@ -975,6 +974,7 @@ /* Start filling in the dynamic data. */ *fill_flash = *flash; + fill_flash->pgm = pgm; base = flashbase ? flashbase : (0xffffffff - size + 1); fill_flash->virtual_memory = (chipaddr)programmer_map_flash_region("flash chip", base, size); Index: flashrom-register_all_programmers_register_generic/programmer.h =================================================================== --- flashrom-register_all_programmers_register_generic/programmer.h (Revision 1463) +++ flashrom-register_all_programmers_register_generic/programmer.h (Arbeitskopie) @@ -93,8 +93,8 @@ int (*init) (void); - void * (*map_flash_region) (const char *descr, unsigned long phys_addr, - size_t len); + void *(*map_flash_region) (const char *descr, unsigned long phys_addr, + size_t len); void (*unmap_flash_region) (void *virt_addr, size_t len); void (*delay) (int usecs); @@ -341,31 +341,6 @@ void rmmio_valw(void *addr); void rmmio_vall(void *addr); -/* programmer.c */ -int noop_shutdown(void); -void *fallback_map(const char *descr, unsigned long phys_addr, size_t len); -void fallback_unmap(void *virt_addr, size_t len); -uint8_t noop_chip_readb(const chipaddr addr); -void noop_chip_writeb(uint8_t val, chipaddr addr); -void fallback_chip_writew(uint16_t val, chipaddr addr); -void fallback_chip_writel(uint32_t val, chipaddr addr); -void fallback_chip_writen(uint8_t *buf, chipaddr addr, size_t len); -uint16_t fallback_chip_readw(const chipaddr addr); -uint32_t fallback_chip_readl(const chipaddr addr); -void fallback_chip_readn(uint8_t *buf, const chipaddr addr, size_t len); -struct par_programmer { - void (*chip_writeb) (uint8_t val, chipaddr addr); - void (*chip_writew) (uint16_t val, chipaddr addr); - void (*chip_writel) (uint32_t val, chipaddr addr); - void (*chip_writen) (uint8_t *buf, chipaddr addr, size_t len); - uint8_t (*chip_readb) (const chipaddr addr); - uint16_t (*chip_readw) (const chipaddr addr); - uint32_t (*chip_readl) (const chipaddr addr); - void (*chip_readn) (uint8_t *buf, const chipaddr addr, size_t len); -}; -extern const struct par_programmer *par_programmer; -void register_par_programmer(const struct par_programmer *pgm, const enum chipbustype buses); - /* dummyflasher.c */ #if CONFIG_DUMMY == 1 int dummy_init(void); @@ -632,6 +607,42 @@ extern const struct opaque_programmer *opaque_programmer; void register_opaque_programmer(const struct opaque_programmer *pgm); +/* programmer.c */ +int noop_shutdown(void); +void *fallback_map(const char *descr, unsigned long phys_addr, size_t len); +void fallback_unmap(void *virt_addr, size_t len); +uint8_t noop_chip_readb(const chipaddr addr); +void noop_chip_writeb(uint8_t val, chipaddr addr); +void fallback_chip_writew(uint16_t val, chipaddr addr); +void fallback_chip_writel(uint32_t val, chipaddr addr); +void fallback_chip_writen(uint8_t *buf, chipaddr addr, size_t len); +uint16_t fallback_chip_readw(const chipaddr addr); +uint32_t fallback_chip_readl(const chipaddr addr); +void fallback_chip_readn(uint8_t *buf, const chipaddr addr, size_t len); +struct par_programmer { + void (*chip_writeb) (uint8_t val, chipaddr addr); + void (*chip_writew) (uint16_t val, chipaddr addr); + void (*chip_writel) (uint32_t val, chipaddr addr); + void (*chip_writen) (uint8_t *buf, chipaddr addr, size_t len); + uint8_t (*chip_readb) (const chipaddr addr); + uint16_t (*chip_readw) (const chipaddr addr); + uint32_t (*chip_readl) (const chipaddr addr); + void (*chip_readn) (uint8_t *buf, const chipaddr addr, size_t len); +}; +extern const struct par_programmer *par_programmer; +void register_par_programmer(const struct par_programmer *pgm, const enum chipbustype buses); +struct registered_programmer { + enum chipbustype buses_supported; + union { + struct par_programmer par; + struct spi_programmer spi; + struct opaque_programmer opaque; + }; +}; +extern struct registered_programmer registered_programmers[]; +extern int registered_programmer_count; +int register_programmer(struct registered_programmer *pgm); + /* serprog.c */ #if CONFIG_SERPROG == 1 int serprog_init(void); -- http://www.hailfinger.org/ From c-d.hailfinger.devel.2006 at gmx.net Fri Nov 11 18:48:23 2011 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Fri, 11 Nov 2011 18:48:23 +0100 Subject: [flashrom] FOSDEM 2012 Message-ID: <4EBD5FE7.3050609@gmx.net> Hey, it seems we forgot to apply for a devroom (well, at least I didn't see anything on the mailing list). Should we submit talks to the individual devrooms? Should we ask for a coreboot/flashrom booth/table? Regards, Carl-Daniel From c-d.hailfinger.devel.2006 at gmx.net Sat Nov 12 16:05:50 2011 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Sat, 12 Nov 2011 16:05:50 +0100 Subject: [flashrom] [PATCH] generic programmer registration In-Reply-To: <4EBCC3E4.9060501@gmx.net> References: <4EBCC3E4.9060501@gmx.net> Message-ID: <4EBE8B4E.9030303@gmx.net> Am 11.11.2011 07:42 schrieb Carl-Daniel Hailfinger: > Please note that this patch breaks every programmer except hwseq because > we're not passing struct flashchip around yet. To get this working, the > following changes have to be made: > - Pass struct flashchip * everywhere (or struct flashctx *), see my > other patch for that > - Change parallel-style and SPI programmers to use flash->pgm... instead > of par_programmer->... and spi_programmer->... > > This compiles and should help you review it, but it is not for merge > until the "struct flashchip * everywhere" patch is in. > Some code has been removed with #if 0 because I wanted to discuss > removing it. The final patch will have no #if 0 at all. This is the complete (hopefully working) patch... the #if 0 is still there, and the "add struct flashchip * everywhere" patch is mixed in to get it working. Once the "struct flashctx *" patch at http://patchwork.coreboot.org/patch/3452/ is merged, I can repost this patch on top of it. NOT FOR MERGE, just for testing. Signed-off-by: Carl-Daniel Hailfinger Index: flashrom-register_all_programmers_register_generic_structflashchip/flash.h =================================================================== --- flashrom-register_all_programmers_register_generic_structflashchip/flash.h (Revision 1463) +++ flashrom-register_all_programmers_register_generic_structflashchip/flash.h (Arbeitskopie) @@ -44,14 +44,6 @@ void *programmer_map_flash_region(const char *descr, unsigned long phys_addr, size_t len); void programmer_unmap_flash_region(void *virt_addr, size_t len); -void chip_writeb(uint8_t val, chipaddr addr); -void chip_writew(uint16_t val, chipaddr addr); -void chip_writel(uint32_t val, chipaddr addr); -void chip_writen(uint8_t *buf, chipaddr addr, size_t len); -uint8_t chip_readb(const chipaddr addr); -uint16_t chip_readw(const chipaddr addr); -uint32_t chip_readl(const chipaddr addr); -void chip_readn(uint8_t *buf, const chipaddr addr, size_t len); void programmer_delay(int usecs); #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) @@ -153,6 +145,7 @@ /* Some flash devices have an additional register space. */ chipaddr virtual_memory; chipaddr virtual_registers; + struct registered_programmer *pgm; }; #define TEST_UNTESTED 0 @@ -186,6 +179,15 @@ extern const struct flashchip flashchips[]; +void chip_writeb(const struct flashchip *flash, uint8_t val, chipaddr addr); +void chip_writew(const struct flashchip *flash, uint16_t val, chipaddr addr); +void chip_writel(const struct flashchip *flash, uint32_t val, chipaddr addr); +void chip_writen(const struct flashchip *flash, uint8_t *buf, chipaddr addr, size_t len); +uint8_t chip_readb(const struct flashchip *flash, const chipaddr addr); +uint16_t chip_readw(const struct flashchip *flash, const chipaddr addr); +uint32_t chip_readl(const struct flashchip *flash, const chipaddr addr); +void chip_readn(const struct flashchip *flash, uint8_t *buf, const chipaddr addr, size_t len); + /* print.c */ char *flashbuses_to_text(enum chipbustype bustype); void print_supported(void); @@ -197,14 +199,13 @@ write_gran_1byte, write_gran_256bytes, }; -extern enum chipbustype buses_supported; extern int verbose; extern const char flashrom_version[]; extern char *chip_to_probe; void map_flash_registers(struct flashchip *flash); int read_memmapped(struct flashchip *flash, uint8_t *buf, int start, int len); int erase_flash(struct flashchip *flash); -int probe_flash(int startchip, struct flashchip *fill_flash, int force); +int probe_flash(struct registered_programmer *pgm, int startchip, struct flashchip *fill_flash, int force); int read_flash_to_file(struct flashchip *flash, const char *filename); int min(int a, int b); int max(int a, int b); @@ -266,9 +267,10 @@ const unsigned char *writearr; unsigned char *readarr; }; -int spi_send_command(unsigned int writecnt, unsigned int readcnt, +int spi_send_command(struct flashchip *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); -int spi_send_multicommand(struct spi_command *cmds); -uint32_t spi_get_valid_read_addr(void); +int spi_send_multicommand(struct flashchip *flash, struct spi_command *cmds); +uint32_t spi_get_valid_read_addr(struct flashchip *flash); +enum chipbustype get_buses_supported(void); #endif /* !__FLASH_H__ */ Index: flashrom-register_all_programmers_register_generic_structflashchip/drkaiser.c =================================================================== --- flashrom-register_all_programmers_register_generic_structflashchip/drkaiser.c (Revision 1463) +++ flashrom-register_all_programmers_register_generic_structflashchip/drkaiser.c (Arbeitskopie) @@ -39,6 +39,8 @@ static uint8_t *drkaiser_bar; +static void drkaiser_chip_writeb(const struct flashchip *flash, uint8_t val, chipaddr addr); +static uint8_t drkaiser_chip_readb(const struct flashchip *flash, const chipaddr addr); static const struct par_programmer par_programmer_drkaiser = { .chip_readb = drkaiser_chip_readb, .chip_readw = fallback_chip_readw, @@ -84,12 +86,12 @@ return 0; } -void drkaiser_chip_writeb(uint8_t val, chipaddr addr) +static void drkaiser_chip_writeb(const struct flashchip *flash, uint8_t val, chipaddr addr) { pci_mmio_writeb(val, drkaiser_bar + (addr & DRKAISER_MEMMAP_MASK)); } -uint8_t drkaiser_chip_readb(const chipaddr addr) +static uint8_t drkaiser_chip_readb(const struct flashchip *flash, const chipaddr addr) { return pci_mmio_readb(drkaiser_bar + (addr & DRKAISER_MEMMAP_MASK)); } Index: flashrom-register_all_programmers_register_generic_structflashchip/it87spi.c =================================================================== --- flashrom-register_all_programmers_register_generic_structflashchip/it87spi.c (Revision 1463) +++ flashrom-register_all_programmers_register_generic_structflashchip/it87spi.c (Arbeitskopie) @@ -103,7 +103,7 @@ return; } -static int it8716f_spi_send_command(unsigned int writecnt, unsigned int readcnt, +static int it8716f_spi_send_command(struct flashchip *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); static int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len); @@ -247,7 +247,7 @@ * commands with the address in inverse wire order. That's why the register * ordering in case 4 and 5 may seem strange. */ -static int it8716f_spi_send_command(unsigned int writecnt, unsigned int readcnt, +static int it8716f_spi_send_command(struct flashchip *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { uint8_t busy, writeenc; @@ -318,19 +318,19 @@ int i, result; chipaddr bios = flash->virtual_memory; - result = spi_write_enable(); + result = spi_write_enable(flash); if (result) return result; /* FIXME: The command below seems to be redundant or wrong. */ OUTB(0x06, it8716f_flashport + 1); OUTB(((2 + (fast_spi ? 1 : 0)) << 4), it8716f_flashport); for (i = 0; i < flash->page_size; i++) - chip_writeb(buf[i], bios + start + i); + chip_writeb(flash, buf[i], bios + start + i); OUTB(0, it8716f_flashport); /* Wait until the Write-In-Progress bit is cleared. * This usually takes 1-10 ms, so wait in 1 ms steps. */ - while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) + while (spi_read_status_register(flash) & JEDEC_RDSR_BIT_WIP) programmer_delay(1000); return 0; } Index: flashrom-register_all_programmers_register_generic_structflashchip/jedec.c =================================================================== --- flashrom-register_all_programmers_register_generic_structflashchip/jedec.c (Revision 1463) +++ flashrom-register_all_programmers_register_generic_structflashchip/jedec.c (Arbeitskopie) @@ -37,17 +37,17 @@ return (val ^ (val >> 1)) & 0x1; } -static void toggle_ready_jedec_common(chipaddr dst, int delay) +static void toggle_ready_jedec_common(const struct flashchip *flash, chipaddr dst, int delay) { unsigned int i = 0; uint8_t tmp1, tmp2; - tmp1 = chip_readb(dst) & 0x40; + tmp1 = chip_readb(flash, dst) & 0x40; while (i++ < 0xFFFFFFF) { if (delay) programmer_delay(delay); - tmp2 = chip_readb(dst) & 0x40; + tmp2 = chip_readb(flash, dst) & 0x40; if (tmp1 == tmp2) { break; } @@ -57,9 +57,9 @@ msg_cdbg("%s: excessive loops, i=0x%x\n", __func__, i); } -void toggle_ready_jedec(chipaddr dst) +void toggle_ready_jedec(const struct flashchip *flash, chipaddr dst) { - toggle_ready_jedec_common(dst, 0); + toggle_ready_jedec_common(flash, dst, 0); } /* Some chips require a minimum delay between toggle bit reads. @@ -69,12 +69,12 @@ * Given that erase is slow on all chips, it is recommended to use * toggle_ready_jedec_slow in erase functions. */ -static void toggle_ready_jedec_slow(chipaddr dst) +static void toggle_ready_jedec_slow(const struct flashchip *flash, chipaddr dst) { - toggle_ready_jedec_common(dst, 8 * 1000); + toggle_ready_jedec_common(flash, dst, 8 * 1000); } -void data_polling_jedec(chipaddr dst, uint8_t data) +void data_polling_jedec(const struct flashchip *flash, chipaddr dst, uint8_t data) { unsigned int i = 0; uint8_t tmp; @@ -82,7 +82,7 @@ data &= 0x80; while (i++ < 0xFFFFFFF) { - tmp = chip_readb(dst) & 0x80; + tmp = chip_readb(flash, dst) & 0x80; if (tmp == data) { break; } @@ -113,9 +113,9 @@ static void start_program_jedec_common(struct flashchip *flash, unsigned int mask) { chipaddr bios = flash->virtual_memory; - chip_writeb(0xAA, bios + (0x5555 & mask)); - chip_writeb(0x55, bios + (0x2AAA & mask)); - chip_writeb(0xA0, bios + (0x5555 & mask)); + chip_writeb(flash, 0xAA, bios + (0x5555 & mask)); + chip_writeb(flash, 0x55, bios + (0x2AAA & mask)); + chip_writeb(flash, 0xA0, bios + (0x5555 & mask)); } static int probe_jedec_common(struct flashchip *flash, unsigned int mask) @@ -150,57 +150,57 @@ /* Reset chip to a clean slate */ if ((flash->feature_bits & FEATURE_RESET_MASK) == FEATURE_LONG_RESET) { - chip_writeb(0xAA, bios + (0x5555 & mask)); + chip_writeb(flash, 0xAA, bios + (0x5555 & mask)); if (probe_timing_exit) programmer_delay(10); - chip_writeb(0x55, bios + (0x2AAA & mask)); + chip_writeb(flash, 0x55, bios + (0x2AAA & mask)); if (probe_timing_exit) programmer_delay(10); } - chip_writeb(0xF0, bios + (0x5555 & mask)); + chip_writeb(flash, 0xF0, bios + (0x5555 & mask)); if (probe_timing_exit) programmer_delay(probe_timing_exit); /* Issue JEDEC Product ID Entry command */ - chip_writeb(0xAA, bios + (0x5555 & mask)); + chip_writeb(flash, 0xAA, bios + (0x5555 & mask)); if (probe_timing_enter) programmer_delay(10); - chip_writeb(0x55, bios + (0x2AAA & mask)); + chip_writeb(flash, 0x55, bios + (0x2AAA & mask)); if (probe_timing_enter) programmer_delay(10); - chip_writeb(0x90, bios + (0x5555 & mask)); + chip_writeb(flash, 0x90, bios + (0x5555 & mask)); if (probe_timing_enter) programmer_delay(probe_timing_enter); /* Read product ID */ - id1 = chip_readb(bios); - id2 = chip_readb(bios + 0x01); + id1 = chip_readb(flash, bios); + id2 = chip_readb(flash, bios + 0x01); largeid1 = id1; largeid2 = id2; /* Check if it is a continuation ID, this should be a while loop. */ if (id1 == 0x7F) { largeid1 <<= 8; - id1 = chip_readb(bios + 0x100); + id1 = chip_readb(flash, bios + 0x100); largeid1 |= id1; } if (id2 == 0x7F) { largeid2 <<= 8; - id2 = chip_readb(bios + 0x101); + id2 = chip_readb(flash, bios + 0x101); largeid2 |= id2; } /* Issue JEDEC Product ID Exit command */ if ((flash->feature_bits & FEATURE_RESET_MASK) == FEATURE_LONG_RESET) { - chip_writeb(0xAA, bios + (0x5555 & mask)); + chip_writeb(flash, 0xAA, bios + (0x5555 & mask)); if (probe_timing_exit) programmer_delay(10); - chip_writeb(0x55, bios + (0x2AAA & mask)); + chip_writeb(flash, 0x55, bios + (0x2AAA & mask)); if (probe_timing_exit) programmer_delay(10); } - chip_writeb(0xF0, bios + (0x5555 & mask)); + chip_writeb(flash, 0xF0, bios + (0x5555 & mask)); if (probe_timing_exit) programmer_delay(probe_timing_exit); @@ -209,17 +209,17 @@ msg_cdbg(", id1 parity violation"); /* Read the product ID location again. We should now see normal flash contents. */ - flashcontent1 = chip_readb(bios); - flashcontent2 = chip_readb(bios + 0x01); + flashcontent1 = chip_readb(flash, bios); + flashcontent2 = chip_readb(flash, bios + 0x01); /* Check if it is a continuation ID, this should be a while loop. */ if (flashcontent1 == 0x7F) { flashcontent1 <<= 8; - flashcontent1 |= chip_readb(bios + 0x100); + flashcontent1 |= chip_readb(flash, bios + 0x100); } if (flashcontent2 == 0x7F) { flashcontent2 <<= 8; - flashcontent2 |= chip_readb(bios + 0x101); + flashcontent2 |= chip_readb(flash, bios + 0x101); } if (largeid1 == flashcontent1) @@ -246,22 +246,22 @@ delay_us = 10; /* Issue the Sector Erase command */ - chip_writeb(0xAA, bios + (0x5555 & mask)); + chip_writeb(flash, 0xAA, bios + (0x5555 & mask)); programmer_delay(delay_us); - chip_writeb(0x55, bios + (0x2AAA & mask)); + chip_writeb(flash, 0x55, bios + (0x2AAA & mask)); programmer_delay(delay_us); - chip_writeb(0x80, bios + (0x5555 & mask)); + chip_writeb(flash, 0x80, bios + (0x5555 & mask)); programmer_delay(delay_us); - chip_writeb(0xAA, bios + (0x5555 & mask)); + chip_writeb(flash, 0xAA, bios + (0x5555 & mask)); programmer_delay(delay_us); - chip_writeb(0x55, bios + (0x2AAA & mask)); + chip_writeb(flash, 0x55, bios + (0x2AAA & mask)); programmer_delay(delay_us); - chip_writeb(0x30, bios + page); + chip_writeb(flash, 0x30, bios + page); programmer_delay(delay_us); /* wait for Toggle bit ready */ - toggle_ready_jedec_slow(bios); + toggle_ready_jedec_slow(flash, bios); /* FIXME: Check the status register for errors. */ return 0; @@ -276,22 +276,22 @@ delay_us = 10; /* Issue the Sector Erase command */ - chip_writeb(0xAA, bios + (0x5555 & mask)); + chip_writeb(flash, 0xAA, bios + (0x5555 & mask)); programmer_delay(delay_us); - chip_writeb(0x55, bios + (0x2AAA & mask)); + chip_writeb(flash, 0x55, bios + (0x2AAA & mask)); programmer_delay(delay_us); - chip_writeb(0x80, bios + (0x5555 & mask)); + chip_writeb(flash, 0x80, bios + (0x5555 & mask)); programmer_delay(delay_us); - chip_writeb(0xAA, bios + (0x5555 & mask)); + chip_writeb(flash, 0xAA, bios + (0x5555 & mask)); programmer_delay(delay_us); - chip_writeb(0x55, bios + (0x2AAA & mask)); + chip_writeb(flash, 0x55, bios + (0x2AAA & mask)); programmer_delay(delay_us); - chip_writeb(0x50, bios + block); + chip_writeb(flash, 0x50, bios + block); programmer_delay(delay_us); /* wait for Toggle bit ready */ - toggle_ready_jedec_slow(bios); + toggle_ready_jedec_slow(flash, bios); /* FIXME: Check the status register for errors. */ return 0; @@ -305,21 +305,21 @@ delay_us = 10; /* Issue the JEDEC Chip Erase command */ - chip_writeb(0xAA, bios + (0x5555 & mask)); + chip_writeb(flash, 0xAA, bios + (0x5555 & mask)); programmer_delay(delay_us); - chip_writeb(0x55, bios + (0x2AAA & mask)); + chip_writeb(flash, 0x55, bios + (0x2AAA & mask)); programmer_delay(delay_us); - chip_writeb(0x80, bios + (0x5555 & mask)); + chip_writeb(flash, 0x80, bios + (0x5555 & mask)); programmer_delay(delay_us); - chip_writeb(0xAA, bios + (0x5555 & mask)); + chip_writeb(flash, 0xAA, bios + (0x5555 & mask)); programmer_delay(delay_us); - chip_writeb(0x55, bios + (0x2AAA & mask)); + chip_writeb(flash, 0x55, bios + (0x2AAA & mask)); programmer_delay(delay_us); - chip_writeb(0x10, bios + (0x5555 & mask)); + chip_writeb(flash, 0x10, bios + (0x5555 & mask)); programmer_delay(delay_us); - toggle_ready_jedec_slow(bios); + toggle_ready_jedec_slow(flash, bios); /* FIXME: Check the status register for errors. */ return 0; @@ -341,10 +341,10 @@ start_program_jedec_common(flash, mask); /* transfer data from source to destination */ - chip_writeb(*src, dst); - toggle_ready_jedec(bios); + chip_writeb(flash, *src, dst); + toggle_ready_jedec(flash, bios); - if (chip_readb(dst) != *src && tried++ < MAX_REFLASH_TRIES) { + if (chip_readb(flash, dst) != *src && tried++ < MAX_REFLASH_TRIES) { goto retry; } @@ -395,12 +395,12 @@ for (i = 0; i < page_size; i++) { /* If the data is 0xFF, don't program it */ if (*src != 0xFF) - chip_writeb(*src, dst); + chip_writeb(flash, *src, dst); dst++; src++; } - toggle_ready_jedec(dst - 1); + toggle_ready_jedec(flash, dst - 1); dst = d; src = s; Index: flashrom-register_all_programmers_register_generic_structflashchip/gfxnvidia.c =================================================================== --- flashrom-register_all_programmers_register_generic_structflashchip/gfxnvidia.c (Revision 1463) +++ flashrom-register_all_programmers_register_generic_structflashchip/gfxnvidia.c (Arbeitskopie) @@ -61,6 +61,8 @@ {}, }; +static void gfxnvidia_chip_writeb(const struct flashchip *flash, uint8_t val, chipaddr addr); +static uint8_t gfxnvidia_chip_readb(const struct flashchip *flash, const chipaddr addr); static const struct par_programmer par_programmer_gfxnvidia = { .chip_readb = gfxnvidia_chip_readb, .chip_readw = fallback_chip_readw, @@ -112,12 +114,12 @@ return 0; } -void gfxnvidia_chip_writeb(uint8_t val, chipaddr addr) +static void gfxnvidia_chip_writeb(const struct flashchip *flash, uint8_t val, chipaddr addr) { pci_mmio_writeb(val, nvidia_bar + (addr & GFXNVIDIA_MEMMAP_MASK)); } -uint8_t gfxnvidia_chip_readb(const chipaddr addr) +static uint8_t gfxnvidia_chip_readb(const struct flashchip *flash, const chipaddr addr) { return pci_mmio_readb(nvidia_bar + (addr & GFXNVIDIA_MEMMAP_MASK)); } Index: flashrom-register_all_programmers_register_generic_structflashchip/nicrealtek.c =================================================================== --- flashrom-register_all_programmers_register_generic_structflashchip/nicrealtek.c (Revision 1463) +++ flashrom-register_all_programmers_register_generic_structflashchip/nicrealtek.c (Arbeitskopie) @@ -36,6 +36,8 @@ {}, }; +static void nicrealtek_chip_writeb(const struct flashchip *flash, uint8_t val, chipaddr addr); +static uint8_t nicrealtek_chip_readb(const struct flashchip *flash, const chipaddr addr); static const struct par_programmer par_programmer_nicrealtek = { .chip_readb = nicrealtek_chip_readb, .chip_readw = fallback_chip_readw, @@ -69,7 +71,7 @@ return 0; } -void nicrealtek_chip_writeb(uint8_t val, chipaddr addr) +static void nicrealtek_chip_writeb(const struct flashchip *flash, uint8_t val, chipaddr addr) { /* Output addr and data, set WE to 0, set OE to 1, set CS to 0, * enable software access. @@ -83,7 +85,7 @@ io_base_addr + BIOS_ROM_ADDR); } -uint8_t nicrealtek_chip_readb(const chipaddr addr) +static uint8_t nicrealtek_chip_readb(const struct flashchip *flash, const chipaddr addr) { uint8_t val; Index: flashrom-register_all_programmers_register_generic_structflashchip/bitbang_spi.c =================================================================== --- flashrom-register_all_programmers_register_generic_structflashchip/bitbang_spi.c (Revision 1463) +++ flashrom-register_all_programmers_register_generic_structflashchip/bitbang_spi.c (Arbeitskopie) @@ -63,7 +63,7 @@ bitbang_spi_master->release_bus(); } -static int bitbang_spi_send_command(unsigned int writecnt, unsigned int readcnt, +static int bitbang_spi_send_command(struct flashchip *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); static const struct spi_programmer spi_programmer_bitbang = { @@ -141,7 +141,7 @@ return ret; } -static int bitbang_spi_send_command(unsigned int writecnt, unsigned int readcnt, +static int bitbang_spi_send_command(struct flashchip *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { int i; Index: flashrom-register_all_programmers_register_generic_structflashchip/serprog.c =================================================================== --- flashrom-register_all_programmers_register_generic_structflashchip/serprog.c (Revision 1463) +++ flashrom-register_all_programmers_register_generic_structflashchip/serprog.c (Arbeitskopie) @@ -299,7 +299,8 @@ return 0; } -static int serprog_spi_send_command(unsigned int writecnt, unsigned int readcnt, +static int serprog_spi_send_command(struct flashchip *flash, + unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); static int serprog_spi_read(struct flashchip *flash, uint8_t *buf, int start, @@ -314,6 +315,9 @@ .write_256 = default_spi_write_256, }; +static void serprog_chip_writeb(const struct flashchip *flash, uint8_t val, chipaddr addr); +static uint8_t serprog_chip_readb(const struct flashchip *flash, const chipaddr addr); +static void serprog_chip_readn(const struct flashchip *flash, uint8_t *buf, const chipaddr addr, size_t len); static const struct par_programmer par_programmer_serprog = { .chip_readb = serprog_chip_readb, .chip_readw = fallback_chip_readw, @@ -680,7 +684,7 @@ } } -void serprog_chip_writeb(uint8_t val, chipaddr addr) +static void serprog_chip_writeb(const struct flashchip *flash, uint8_t val, chipaddr addr) { msg_pspew("%s\n", __func__); if (sp_max_write_n) { @@ -711,7 +715,7 @@ } } -uint8_t serprog_chip_readb(const chipaddr addr) +static uint8_t serprog_chip_readb(const struct flashchip *flash, const chipaddr addr) { unsigned char c; unsigned char buf[3]; @@ -757,7 +761,7 @@ } /* The externally called version that makes sure that max_read_n is obeyed. */ -void serprog_chip_readn(uint8_t * buf, const chipaddr addr, size_t len) +static void serprog_chip_readn(const struct flashchip *flash, uint8_t * buf, const chipaddr addr, size_t len) { size_t lenm = len; chipaddr addrm = addr; @@ -792,7 +796,7 @@ sp_prev_was_write = 0; } -static int serprog_spi_send_command(unsigned int writecnt, unsigned int readcnt, +static int serprog_spi_send_command(struct flashchip *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { @@ -830,7 +834,7 @@ for (i = 0; i < len; i += cur_len) { int ret; cur_len = min(max_read, (len - i)); - ret = spi_nbyte_read(start + i, buf + i, cur_len); + ret = spi_nbyte_read(flash, start + i, buf + i, cur_len); if (ret) return ret; } Index: flashrom-register_all_programmers_register_generic_structflashchip/w39.c =================================================================== --- flashrom-register_all_programmers_register_generic_structflashchip/w39.c (Revision 1463) +++ flashrom-register_all_programmers_register_generic_structflashchip/w39.c (Arbeitskopie) @@ -26,7 +26,7 @@ chipaddr wrprotect = flash->virtual_registers + offset + 2; uint8_t locking; - locking = chip_readb(wrprotect); + locking = chip_readb(flash, wrprotect); msg_cdbg("Lock status of block at 0x%08x is ", offset); switch (locking & 0x7) { case 0: @@ -64,7 +64,7 @@ chipaddr wrprotect = flash->virtual_registers + offset + 2; uint8_t locking; - locking = chip_readb(wrprotect); + locking = chip_readb(flash, wrprotect); /* Read or write lock present? */ if (locking & ((1 << 2) | (1 << 0))) { /* Lockdown active? */ @@ -73,7 +73,7 @@ return -1; } else { msg_cdbg("Unlocking block at 0x%08x\n", offset); - chip_writeb(0, wrprotect); + chip_writeb(flash, 0, wrprotect); } } @@ -86,18 +86,18 @@ uint8_t val; /* Product Identification Entry */ - chip_writeb(0xAA, bios + 0x5555); - chip_writeb(0x55, bios + 0x2AAA); - chip_writeb(0x90, bios + 0x5555); + chip_writeb(flash, 0xAA, bios + 0x5555); + chip_writeb(flash, 0x55, bios + 0x2AAA); + chip_writeb(flash, 0x90, bios + 0x5555); programmer_delay(10); /* Read something, maybe hardware lock bits */ - val = chip_readb(bios + offset); + val = chip_readb(flash, bios + offset); /* Product Identification Exit */ - chip_writeb(0xAA, bios + 0x5555); - chip_writeb(0x55, bios + 0x2AAA); - chip_writeb(0xF0, bios + 0x5555); + chip_writeb(flash, 0xAA, bios + 0x5555); + chip_writeb(flash, 0x55, bios + 0x2AAA); + chip_writeb(flash, 0xF0, bios + 0x5555); programmer_delay(10); return val; Index: flashrom-register_all_programmers_register_generic_structflashchip/sst49lfxxxc.c =================================================================== --- flashrom-register_all_programmers_register_generic_structflashchip/sst49lfxxxc.c (Revision 1463) +++ flashrom-register_all_programmers_register_generic_structflashchip/sst49lfxxxc.c (Arbeitskopie) @@ -26,8 +26,8 @@ static int write_lockbits_block_49lfxxxc(struct flashchip *flash, unsigned long address, unsigned char bits) { unsigned long lock = flash->virtual_registers + address + 2; - msg_cdbg("lockbits at address=0x%08lx is 0x%01x\n", lock, chip_readb(lock)); - chip_writeb(bits, lock); + msg_cdbg("lockbits at address=0x%08lx is 0x%01x\n", lock, chip_readb(flash, lock)); + chip_writeb(flash, bits, lock); return 0; } @@ -64,8 +64,8 @@ uint8_t status; chipaddr bios = flash->virtual_memory; - chip_writeb(0x30, bios); - chip_writeb(0xD0, bios + address); + chip_writeb(flash, 0x30, bios); + chip_writeb(flash, 0xD0, bios + address); status = wait_82802ab(flash); print_status_82802ab(status); Index: flashrom-register_all_programmers_register_generic_structflashchip/sharplhf00l04.c =================================================================== --- flashrom-register_all_programmers_register_generic_structflashchip/sharplhf00l04.c (Revision 1463) +++ flashrom-register_all_programmers_register_generic_structflashchip/sharplhf00l04.c (Arbeitskopie) @@ -33,18 +33,18 @@ uint8_t status; // clear status register - chip_writeb(0x50, bios); + chip_writeb(flash, 0x50, bios); status = wait_82802ab(flash); print_status_82802ab(status); // clear write protect msg_cspew("write protect is at 0x%lx\n", (wrprotect)); - msg_cspew("write protect is 0x%x\n", chip_readb(wrprotect)); - chip_writeb(0, wrprotect); - msg_cspew("write protect is 0x%x\n", chip_readb(wrprotect)); + msg_cspew("write protect is 0x%x\n", chip_readb(flash, wrprotect)); + chip_writeb(flash, 0, wrprotect); + msg_cspew("write protect is 0x%x\n", chip_readb(flash, wrprotect)); // now start it - chip_writeb(0x20, bios); - chip_writeb(0xd0, bios); + chip_writeb(flash, 0x20, bios); + chip_writeb(flash, 0xd0, bios); programmer_delay(10); // now let's see what the register is status = wait_82802ab(flash); Index: flashrom-register_all_programmers_register_generic_structflashchip/a25.c =================================================================== --- flashrom-register_all_programmers_register_generic_structflashchip/a25.c (Revision 1463) +++ flashrom-register_all_programmers_register_generic_structflashchip/a25.c (Arbeitskopie) @@ -33,7 +33,7 @@ { uint8_t status; - status = spi_read_status_register(); + status = spi_read_status_register(flash); msg_cdbg("Chip status register is %02x\n", status); spi_prettyprint_status_register_amic_a25_srwd(status); @@ -49,7 +49,7 @@ { uint8_t status; - status = spi_read_status_register(); + status = spi_read_status_register(flash); msg_cdbg("Chip status register is %02x\n", status); spi_prettyprint_status_register_amic_a25_srwd(status); @@ -64,7 +64,7 @@ { uint8_t status; - status = spi_read_status_register(); + status = spi_read_status_register(flash); msg_cdbg("Chip status register is %02x\n", status); spi_prettyprint_status_register_amic_a25_srwd(status); @@ -82,7 +82,7 @@ { uint8_t status; - status = spi_read_status_register(); + status = spi_read_status_register(flash); msg_cdbg("Chip status register is %02x\n", status); spi_prettyprint_status_register_amic_a25_srwd(status); Index: flashrom-register_all_programmers_register_generic_structflashchip/satamv.c =================================================================== --- flashrom-register_all_programmers_register_generic_structflashchip/satamv.c (Revision 1463) +++ flashrom-register_all_programmers_register_generic_structflashchip/satamv.c (Arbeitskopie) @@ -41,6 +41,8 @@ #define PCI_BAR2_CONTROL 0x00c08 #define GPIO_PORT_CONTROL 0x104f0 +static void satamv_chip_writeb(const struct flashchip *flash, uint8_t val, chipaddr addr); +static uint8_t satamv_chip_readb(const struct flashchip *flash, const chipaddr addr); static const struct par_programmer par_programmer_satamv = { .chip_readb = satamv_chip_readb, .chip_readw = fallback_chip_readw, @@ -183,13 +185,13 @@ } /* FIXME: Prefer direct access to BAR2 if BAR2 is active. */ -void satamv_chip_writeb(uint8_t val, chipaddr addr) +static void satamv_chip_writeb(const struct flashchip *flash, uint8_t val, chipaddr addr) { satamv_indirect_chip_writeb(val, addr); } /* FIXME: Prefer direct access to BAR2 if BAR2 is active. */ -uint8_t satamv_chip_readb(const chipaddr addr) +static uint8_t satamv_chip_readb(const struct flashchip *flash, const chipaddr addr) { return satamv_indirect_chip_readb(addr); } Index: flashrom-register_all_programmers_register_generic_structflashchip/dummyflasher.c =================================================================== --- flashrom-register_all_programmers_register_generic_structflashchip/dummyflasher.c (Revision 1463) +++ flashrom-register_all_programmers_register_generic_structflashchip/dummyflasher.c (Arbeitskopie) @@ -60,10 +60,18 @@ static int spi_write_256_chunksize = 256; -static int dummy_spi_send_command(unsigned int writecnt, unsigned int readcnt, +static int dummy_spi_send_command(struct flashchip *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); static int dummy_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); +static void dummy_chip_writeb(const struct flashchip *flash, uint8_t val, chipaddr addr); +static void dummy_chip_writew(const struct flashchip *flash, uint16_t val, chipaddr addr); +static void dummy_chip_writel(const struct flashchip *flash, uint32_t val, chipaddr addr); +static void dummy_chip_writen(const struct flashchip *flash, uint8_t *buf, chipaddr addr, size_t len); +static uint8_t dummy_chip_readb(const struct flashchip *flash, const chipaddr addr); +static uint16_t dummy_chip_readw(const struct flashchip *flash, const chipaddr addr); +static uint32_t dummy_chip_readl(const struct flashchip *flash, const chipaddr addr); +static void dummy_chip_readn(const struct flashchip *flash, uint8_t *buf, const chipaddr addr, size_t len); static const struct spi_programmer spi_programmer_dummyflasher = { .type = SPI_CONTROLLER_DUMMY, @@ -263,22 +271,22 @@ __func__, (unsigned long)len, virt_addr); } -void dummy_chip_writeb(uint8_t val, chipaddr addr) +static void dummy_chip_writeb(const struct flashchip *flash, uint8_t val, chipaddr addr) { msg_pspew("%s: addr=0x%lx, val=0x%02x\n", __func__, addr, val); } -void dummy_chip_writew(uint16_t val, chipaddr addr) +static void dummy_chip_writew(const struct flashchip *flash, uint16_t val, chipaddr addr) { msg_pspew("%s: addr=0x%lx, val=0x%04x\n", __func__, addr, val); } -void dummy_chip_writel(uint32_t val, chipaddr addr) +static void dummy_chip_writel(const struct flashchip *flash, uint32_t val, chipaddr addr) { msg_pspew("%s: addr=0x%lx, val=0x%08x\n", __func__, addr, val); } -void dummy_chip_writen(uint8_t *buf, chipaddr addr, size_t len) +static void dummy_chip_writen(const struct flashchip *flash, uint8_t *buf, chipaddr addr, size_t len) { size_t i; msg_pspew("%s: addr=0x%lx, len=0x%08lx, writing data (hex):", @@ -290,25 +298,25 @@ } } -uint8_t dummy_chip_readb(const chipaddr addr) +static uint8_t dummy_chip_readb(const struct flashchip *flash, const chipaddr addr) { msg_pspew("%s: addr=0x%lx, returning 0xff\n", __func__, addr); return 0xff; } -uint16_t dummy_chip_readw(const chipaddr addr) +static uint16_t dummy_chip_readw(const struct flashchip *flash, const chipaddr addr) { msg_pspew("%s: addr=0x%lx, returning 0xffff\n", __func__, addr); return 0xffff; } -uint32_t dummy_chip_readl(const chipaddr addr) +static uint32_t dummy_chip_readl(const struct flashchip *flash, const chipaddr addr) { msg_pspew("%s: addr=0x%lx, returning 0xffffffff\n", __func__, addr); return 0xffffffff; } -void dummy_chip_readn(uint8_t *buf, const chipaddr addr, size_t len) +static void dummy_chip_readn(const struct flashchip *flash, uint8_t *buf, const chipaddr addr, size_t len) { msg_pspew("%s: addr=0x%lx, len=0x%lx, returning array of 0xff\n", __func__, addr, (unsigned long)len); @@ -513,7 +521,7 @@ } #endif -static int dummy_spi_send_command(unsigned int writecnt, unsigned int readcnt, +static int dummy_spi_send_command(struct flashchip *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { int i; Index: flashrom-register_all_programmers_register_generic_structflashchip/sst_fwhub.c =================================================================== --- flashrom-register_all_programmers_register_generic_structflashchip/sst_fwhub.c (Revision 1463) +++ flashrom-register_all_programmers_register_generic_structflashchip/sst_fwhub.c (Arbeitskopie) @@ -29,7 +29,7 @@ chipaddr registers = flash->virtual_registers; uint8_t blockstatus; - blockstatus = chip_readb(registers + offset + 2); + blockstatus = chip_readb(flash, registers + offset + 2); msg_cdbg("Lock status for 0x%06x (size 0x%06x) is %02x, ", offset, flash->page_size, blockstatus); switch (blockstatus & 0x3) { @@ -59,7 +59,7 @@ if (blockstatus) { msg_cdbg("Trying to clear lock for 0x%06x... ", offset); - chip_writeb(0, registers + offset + 2); + chip_writeb(flash, 0, registers + offset + 2); blockstatus = check_sst_fwhub_block_lock(flash, offset); msg_cdbg("%s\n", (blockstatus) ? "failed" : "OK"); Index: flashrom-register_all_programmers_register_generic_structflashchip/cli_classic.c =================================================================== --- flashrom-register_all_programmers_register_generic_structflashchip/cli_classic.c (Revision 1463) +++ flashrom-register_all_programmers_register_generic_structflashchip/cli_classic.c (Arbeitskopie) @@ -172,7 +172,7 @@ struct flashchip flashes[3]; struct flashchip *fill_flash; const char *name; - int namelen, opt, i; + int namelen, opt, i, j; int startchip = 0, chipcount = 0, option_index = 0, force = 0; #if CONFIG_PRINT_WIKI == 1 int list_supported_wiki = 0; @@ -443,17 +443,21 @@ ret = 1; goto out_shutdown; } - tempstr = flashbuses_to_text(buses_supported); + tempstr = flashbuses_to_text(get_buses_supported()); msg_pdbg("This programmer supports the following protocols: %s.\n", tempstr); free(tempstr); - for (i = 0; i < ARRAY_SIZE(flashes); i++) { - startchip = probe_flash(startchip, &flashes[i], 0); - if (startchip == -1) - break; - chipcount++; - startchip++; + for (j = 0; j < registered_programmer_count; j++) { + startchip = 0; + for (i = 0; i < ARRAY_SIZE(flashes); i++) { + startchip = probe_flash(®istered_programmers[j], + startchip, &flashes[i], 0); + if (startchip == -1) + break; + chipcount++; + startchip++; + } } if (chipcount > 1) { @@ -471,6 +475,7 @@ printf("Note: flashrom can never write if the flash " "chip isn't found automatically.\n"); } +#if 0 // FIXME: What happens for a forced chip read if multiple compatible programmers are registered? if (force && read_it && chip_to_probe) { printf("Force read (-f -r -c) requested, pretending " "the chip is there:\n"); @@ -485,6 +490,7 @@ "contain garbage.\n"); return read_flash_to_file(&flashes[0], filename); } +#endif ret = 1; goto out_shutdown; } else if (!chip_to_probe) { @@ -501,7 +507,7 @@ check_chip_supported(fill_flash); size = fill_flash->total_size * 1024; - if (check_max_decode((buses_supported & fill_flash->bustype), size) && + if (check_max_decode((get_buses_supported() & fill_flash->bustype), size) && (!force)) { fprintf(stderr, "Chip is too big for this programmer " "(-V gives details). Use --force to override.\n"); Index: flashrom-register_all_programmers_register_generic_structflashchip/at25.c =================================================================== --- flashrom-register_all_programmers_register_generic_structflashchip/at25.c (Revision 1463) +++ flashrom-register_all_programmers_register_generic_structflashchip/at25.c (Arbeitskopie) @@ -61,7 +61,7 @@ { uint8_t status; - status = spi_read_status_register(); + status = spi_read_status_register(flash); msg_cdbg("Chip status register is %02x\n", status); spi_prettyprint_status_register_atmel_at25_srpl(status); @@ -84,7 +84,7 @@ { uint8_t status; - status = spi_read_status_register(); + status = spi_read_status_register(flash); msg_cdbg("Chip status register is %02x\n", status); spi_prettyprint_status_register_atmel_at25_srpl(status); @@ -103,7 +103,7 @@ { uint8_t status; - status = spi_read_status_register(); + status = spi_read_status_register(flash); msg_cdbg("Chip status register is %02x\n", status); msg_cdbg("Chip status register: Status Register Write Protect (WPEN) " @@ -127,7 +127,7 @@ { uint8_t status; - status = spi_read_status_register(); + status = spi_read_status_register(flash); msg_cdbg("Chip status register is %02x\n", status); msg_cdbg("Chip status register: Status Register Write Protect (WPEN) " @@ -151,7 +151,7 @@ { uint8_t status; - status = spi_read_status_register(); + status = spi_read_status_register(flash); msg_cdbg("Chip status register is %02x\n", status); spi_prettyprint_status_register_atmel_at25_srpl(status); @@ -168,7 +168,7 @@ uint8_t status; int result; - status = spi_read_status_register(); + status = spi_read_status_register(flash); /* If block protection is disabled, stop here. */ if ((status & (3 << 2)) == 0) return 0; @@ -195,7 +195,7 @@ msg_cerr("spi_write_status_register failed\n"); return result; } - status = spi_read_status_register(); + status = spi_read_status_register(flash); if ((status & (3 << 2)) != 0) { msg_cerr("Block protection could not be disabled!\n"); return 1; @@ -223,7 +223,7 @@ uint8_t status; int result; - status = spi_read_status_register(); + status = spi_read_status_register(flash); /* If block protection is disabled, stop here. */ if ((status & 0x6c) == 0) return 0; @@ -244,7 +244,7 @@ msg_cerr("spi_write_status_register failed\n"); return result; } - status = spi_read_status_register(); + status = spi_read_status_register(flash); if ((status & 0x6c) != 0) { msg_cerr("Block protection could not be disabled!\n"); return 1; @@ -257,7 +257,7 @@ uint8_t status; int result; - status = spi_read_status_register(); + status = spi_read_status_register(flash); /* If block protection is disabled, stop here. */ if ((status & 0x7c) == 0) return 0; @@ -278,7 +278,7 @@ msg_cerr("spi_write_status_register failed\n"); return result; } - status = spi_read_status_register(); + status = spi_read_status_register(flash); if ((status & 0x7c) != 0) { msg_cerr("Block protection could not be disabled!\n"); return 1; Index: flashrom-register_all_programmers_register_generic_structflashchip/internal.c =================================================================== --- flashrom-register_all_programmers_register_generic_structflashchip/internal.c (Revision 1463) +++ flashrom-register_all_programmers_register_generic_structflashchip/internal.c (Arbeitskopie) @@ -127,6 +127,13 @@ int is_laptop = 0; int laptop_ok = 0; +static void internal_chip_writeb(const struct flashchip *flash, uint8_t val, chipaddr addr); +static void internal_chip_writew(const struct flashchip *flash, uint16_t val, chipaddr addr); +static void internal_chip_writel(const struct flashchip *flash, uint32_t val, chipaddr addr); +static uint8_t internal_chip_readb(const struct flashchip *flash, const chipaddr addr); +static uint16_t internal_chip_readw(const struct flashchip *flash, const chipaddr addr); +static uint32_t internal_chip_readl(const struct flashchip *flash, const chipaddr addr); +static void internal_chip_readn(const struct flashchip *flash, uint8_t *buf, const chipaddr addr, size_t len); static const struct par_programmer par_programmer_internal = { .chip_readb = internal_chip_readb, .chip_readw = internal_chip_readw, @@ -324,37 +331,37 @@ } #endif -void internal_chip_writeb(uint8_t val, chipaddr addr) +static void internal_chip_writeb(const struct flashchip *flash, uint8_t val, chipaddr addr) { mmio_writeb(val, (void *) addr); } -void internal_chip_writew(uint16_t val, chipaddr addr) +static void internal_chip_writew(const struct flashchip *flash, uint16_t val, chipaddr addr) { mmio_writew(val, (void *) addr); } -void internal_chip_writel(uint32_t val, chipaddr addr) +static void internal_chip_writel(const struct flashchip *flash, uint32_t val, chipaddr addr) { mmio_writel(val, (void *) addr); } -uint8_t internal_chip_readb(const chipaddr addr) +static uint8_t internal_chip_readb(const struct flashchip *flash, const chipaddr addr) { return mmio_readb((void *) addr); } -uint16_t internal_chip_readw(const chipaddr addr) +static uint16_t internal_chip_readw(const struct flashchip *flash, const chipaddr addr) { return mmio_readw((void *) addr); } -uint32_t internal_chip_readl(const chipaddr addr) +static uint32_t internal_chip_readl(const struct flashchip *flash, const chipaddr addr) { return mmio_readl((void *) addr); } -void internal_chip_readn(uint8_t *buf, const chipaddr addr, size_t len) +static void internal_chip_readn(const struct flashchip *flash, uint8_t *buf, const chipaddr addr, size_t len) { memcpy(buf, (void *)addr, len); return; Index: flashrom-register_all_programmers_register_generic_structflashchip/ichspi.c =================================================================== --- flashrom-register_all_programmers_register_generic_structflashchip/ichspi.c (Revision 1463) +++ flashrom-register_all_programmers_register_generic_structflashchip/ichspi.c (Arbeitskopie) @@ -228,7 +228,7 @@ static int find_preop(OPCODES *op, uint8_t preop); static int generate_opcodes(OPCODES * op); static int program_opcodes(OPCODES *op, int enable_undo); -static int run_opcode(OPCODE op, uint32_t offset, +static int run_opcode(const struct flashchip *flash, OPCODE op, uint32_t offset, uint8_t datalength, uint8_t * data); /* for pairing opcodes with their required preop */ @@ -635,7 +635,7 @@ /* Read len bytes from the fdata/spid register into the data array. * - * Note that using len > spi_programmer->max_data_read will return garbage or + * Note that using len > flash->pgm->spi.max_data_read will return garbage or * may even crash. */ static void ich_read_data(uint8_t *data, int len, int reg0_off) @@ -653,7 +653,7 @@ /* Fill len bytes from the data array into the fdata/spid registers. * - * Note that using len > spi_programmer->max_data_write will trash the registers + * Note that using len > flash->pgm->spi.max_data_write will trash the registers * following the data registers. */ static void ich_fill_data(const uint8_t *data, int len, int reg0_off) @@ -956,13 +956,13 @@ return 0; } -static int run_opcode(OPCODE op, uint32_t offset, +static int run_opcode(const struct flashchip *flash, OPCODE op, uint32_t offset, uint8_t datalength, uint8_t * data) { /* max_data_read == max_data_write for all Intel/VIA SPI masters */ - uint8_t maxlength = spi_programmer->max_data_read; + uint8_t maxlength = flash->pgm->spi.max_data_read; - if (spi_programmer->type == SPI_CONTROLLER_NONE) { + if (ich_generation == CHIPSET_ICH_UNKNOWN) { msg_perr("%s: unsupported chipset\n", __func__); return -1; } @@ -983,7 +983,7 @@ } } -static int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, +static int ich_spi_send_command(struct flashchip *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { int result; @@ -1076,7 +1076,7 @@ count = readcnt; } - result = run_opcode(*opcode, addr, count, data); + result = run_opcode(flash, *opcode, addr, count, data); if (result) { msg_pdbg("Running OPCODE 0x%02x failed ", opcode->opcode); if ((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) || @@ -1295,7 +1295,7 @@ REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS)); while (len > 0) { - block_len = min(len, opaque_programmer->max_data_read); + block_len = min(len, flash->pgm->opaque.max_data_read); ich_hwseq_set_addr(addr); hsfc = REGREAD16(ICH9_REG_HSFC); hsfc &= ~HSFC_FCYCLE; /* set read operation */ @@ -1333,7 +1333,7 @@ while (len > 0) { ich_hwseq_set_addr(addr); - block_len = min(len, opaque_programmer->max_data_write); + block_len = min(len, flash->pgm->opaque.max_data_write); ich_fill_data(buf, block_len, ICH9_REG_FDATA0); hsfc = REGREAD16(ICH9_REG_HSFC); hsfc &= ~HSFC_FCYCLE; /* clear operation */ @@ -1353,7 +1353,7 @@ return 0; } -static int ich_spi_send_multicommand(struct spi_command *cmds) +static int ich_spi_send_multicommand(struct flashchip *flash, struct spi_command *cmds) { int ret = 0; int i; @@ -1403,7 +1403,7 @@ * preoppos matched, this is a normal opcode. */ } - ret = ich_spi_send_command(cmds->writecnt, cmds->readcnt, + ret = ich_spi_send_command(flash, cmds->writecnt, cmds->readcnt, cmds->writearr, cmds->readarr); /* Reset the type of all opcodes to non-atomic. */ for (i = 0; i < 8; i++) Index: flashrom-register_all_programmers_register_generic_structflashchip/82802ab.c =================================================================== --- flashrom-register_all_programmers_register_generic_structflashchip/82802ab.c (Revision 1463) +++ flashrom-register_all_programmers_register_generic_structflashchip/82802ab.c (Arbeitskopie) @@ -47,18 +47,18 @@ int shifted = (flash->feature_bits & FEATURE_ADDR_SHIFTED) != 0; /* Reset to get a clean state */ - chip_writeb(0xFF, bios); + chip_writeb(flash, 0xFF, bios); programmer_delay(10); /* Enter ID mode */ - chip_writeb(0x90, bios); + chip_writeb(flash, 0x90, bios); programmer_delay(10); - id1 = chip_readb(bios + (0x00 << shifted)); - id2 = chip_readb(bios + (0x01 << shifted)); + id1 = chip_readb(flash, bios + (0x00 << shifted)); + id2 = chip_readb(flash, bios + (0x01 << shifted)); /* Leave ID mode */ - chip_writeb(0xFF, bios); + chip_writeb(flash, 0xFF, bios); programmer_delay(10); @@ -71,8 +71,8 @@ * Read the product ID location again. We should now see normal * flash contents. */ - flashcontent1 = chip_readb(bios + (0x00 << shifted)); - flashcontent2 = chip_readb(bios + (0x01 << shifted)); + flashcontent1 = chip_readb(flash, bios + (0x00 << shifted)); + flashcontent2 = chip_readb(flash, bios + (0x01 << shifted)); if (id1 == flashcontent1) msg_cdbg(", id1 is normal flash content"); @@ -94,15 +94,15 @@ uint8_t status; chipaddr bios = flash->virtual_memory; - chip_writeb(0x70, bios); - if ((chip_readb(bios) & 0x80) == 0) { // it's busy - while ((chip_readb(bios) & 0x80) == 0) ; + chip_writeb(flash, 0x70, bios); + if ((chip_readb(flash, bios) & 0x80) == 0) { // it's busy + while ((chip_readb(flash, bios) & 0x80) == 0) ; } - status = chip_readb(bios); + status = chip_readb(flash, bios); /* Reset to get a clean state */ - chip_writeb(0xFF, bios); + chip_writeb(flash, 0xFF, bios); return status; } @@ -113,7 +113,7 @@ //chipaddr wrprotect = flash->virtual_registers + page + 2; for (i = 0; i < flash->total_size * 1024; i+= flash->page_size) - chip_writeb(0, flash->virtual_registers + i + 2); + chip_writeb(flash, 0, flash->virtual_registers + i + 2); return 0; } @@ -125,11 +125,11 @@ uint8_t status; // clear status register - chip_writeb(0x50, bios + page); + chip_writeb(flash, 0x50, bios + page); // now start it - chip_writeb(0x20, bios + page); - chip_writeb(0xd0, bios + page); + chip_writeb(flash, 0x20, bios + page); + chip_writeb(flash, 0xd0, bios + page); programmer_delay(10); // now let's see what the register is @@ -148,8 +148,8 @@ for (i = 0; i < len; i++) { /* transfer data from source to destination */ - chip_writeb(0x40, dst); - chip_writeb(*src++, dst++); + chip_writeb(flash, 0x40, dst); + chip_writeb(flash, *src++, dst++); wait_82802ab(flash); } @@ -164,13 +164,13 @@ int i; /* Clear status register */ - chip_writeb(0x50, bios); + chip_writeb(flash, 0x50, bios); /* Read identifier codes */ - chip_writeb(0x90, bios); + chip_writeb(flash, 0x90, bios); /* Read master lock-bit */ - mcfg = chip_readb(bios + 0x3); + mcfg = chip_readb(flash, bios + 0x3); msg_cdbg("master lock is "); if (mcfg) { msg_cdbg("locked!\n"); @@ -181,7 +181,7 @@ /* Read block lock-bits */ for (i = 0; i < flash->total_size * 1024; i+= (64 * 1024)) { - bcfg = chip_readb(bios + i + 2); // read block lock config + bcfg = chip_readb(flash, bios + i + 2); // read block lock config msg_cdbg("block lock at %06x is %slocked!\n", i, bcfg ? "" : "un"); if (bcfg) { need_unlock = 1; @@ -189,14 +189,14 @@ } /* Reset chip */ - chip_writeb(0xFF, bios); + chip_writeb(flash, 0xFF, bios); /* Unlock: clear block lock-bits, if needed */ if (can_unlock && need_unlock) { msg_cdbg("Unlock: "); - chip_writeb(0x60, bios); - chip_writeb(0xD0, bios); - chip_writeb(0xFF, bios); + chip_writeb(flash, 0x60, bios); + chip_writeb(flash, 0xD0, bios); + chip_writeb(flash, 0xFF, bios); msg_cdbg("Done!\n"); } @@ -220,10 +220,10 @@ wait_82802ab(flash); /* Read identifier codes */ - chip_writeb(0x90, bios); + chip_writeb(flash, 0x90, bios); /* Read master lock-bit */ - mcfg = chip_readb(bios + 0x3); + mcfg = chip_readb(flash, bios + 0x3); msg_cdbg("master lock is "); if (mcfg) { msg_cdbg("locked!\n"); @@ -235,7 +235,7 @@ /* Read block lock-bits, 8 * 8 KB + 15 * 64 KB */ for (i = 0; i < flash->total_size * 1024; i += (i >= (64 * 1024) ? 64 * 1024 : 8 * 1024)) { - bcfg = chip_readb(bios + i + 2); /* read block lock config */ + bcfg = chip_readb(flash, bios + i + 2); /* read block lock config */ msg_cdbg("block lock at %06x is %slocked!\n", i, bcfg ? "" : "un"); if (bcfg) @@ -243,14 +243,14 @@ } /* Reset chip */ - chip_writeb(0xFF, bios); + chip_writeb(flash, 0xFF, bios); /* Unlock: clear block lock-bits, if needed */ if (can_unlock && need_unlock) { msg_cdbg("Unlock: "); - chip_writeb(0x60, bios); - chip_writeb(0xD0, bios); - chip_writeb(0xFF, bios); + chip_writeb(flash, 0x60, bios); + chip_writeb(flash, 0xD0, bios); + chip_writeb(flash, 0xFF, bios); wait_82802ab(flash); msg_cdbg("Done!\n"); } Index: flashrom-register_all_programmers_register_generic_structflashchip/nicnatsemi.c =================================================================== --- flashrom-register_all_programmers_register_generic_structflashchip/nicnatsemi.c (Revision 1463) +++ flashrom-register_all_programmers_register_generic_structflashchip/nicnatsemi.c (Arbeitskopie) @@ -35,6 +35,8 @@ {}, }; +static void nicnatsemi_chip_writeb(const struct flashchip *flash, uint8_t val, chipaddr addr); +static uint8_t nicnatsemi_chip_readb(const struct flashchip *flash, const chipaddr addr); static const struct par_programmer par_programmer_nicnatsemi = { .chip_readb = nicnatsemi_chip_readb, .chip_readw = fallback_chip_readw, @@ -74,7 +76,7 @@ return 0; } -void nicnatsemi_chip_writeb(uint8_t val, chipaddr addr) +static void nicnatsemi_chip_writeb(const struct flashchip *flash, uint8_t val, chipaddr addr) { OUTL((uint32_t)addr & 0x0001FFFF, io_base_addr + BOOT_ROM_ADDR); /* @@ -88,7 +90,7 @@ OUTB(val, io_base_addr + BOOT_ROM_DATA); } -uint8_t nicnatsemi_chip_readb(const chipaddr addr) +static uint8_t nicnatsemi_chip_readb(const struct flashchip *flash, const chipaddr addr) { OUTL(((uint32_t)addr & 0x0001FFFF), io_base_addr + BOOT_ROM_ADDR); /* Index: flashrom-register_all_programmers_register_generic_structflashchip/opaque.c =================================================================== --- flashrom-register_all_programmers_register_generic_structflashchip/opaque.c (Revision 1463) +++ flashrom-register_all_programmers_register_generic_structflashchip/opaque.c (Arbeitskopie) @@ -30,70 +30,62 @@ #include "chipdrivers.h" #include "programmer.h" -const struct opaque_programmer opaque_programmer_none = { - .max_data_read = MAX_DATA_UNSPECIFIED, - .max_data_write = MAX_DATA_UNSPECIFIED, - .probe = NULL, - .read = NULL, - .write = NULL, - .erase = NULL, -}; - -const struct opaque_programmer *opaque_programmer = &opaque_programmer_none; - int probe_opaque(struct flashchip *flash) { - if (!opaque_programmer->probe) { + if (!flash->pgm->opaque.probe) { msg_perr("%s called before register_opaque_programmer. " "Please report a bug at flashrom at flashrom.org\n", __func__); return 0; } - return opaque_programmer->probe(flash); + return flash->pgm->opaque.probe(flash); } int read_opaque(struct flashchip *flash, uint8_t *buf, int start, int len) { - if (!opaque_programmer->read) { + if (!flash->pgm->opaque.read) { msg_perr("%s called before register_opaque_programmer. " "Please report a bug at flashrom at flashrom.org\n", __func__); return 1; } - return opaque_programmer->read(flash, buf, start, len); + return flash->pgm->opaque.read(flash, buf, start, len); } int write_opaque(struct flashchip *flash, uint8_t *buf, int start, int len) { - if (!opaque_programmer->write) { + if (!flash->pgm->opaque.write) { msg_perr("%s called before register_opaque_programmer. " "Please report a bug at flashrom at flashrom.org\n", __func__); return 1; } - return opaque_programmer->write(flash, buf, start, len); + return flash->pgm->opaque.write(flash, buf, start, len); } int erase_opaque(struct flashchip *flash, unsigned int blockaddr, unsigned int blocklen) { - if (!opaque_programmer->erase) { + if (!flash->pgm->opaque.erase) { msg_perr("%s called before register_opaque_programmer. " "Please report a bug at flashrom at flashrom.org\n", __func__); return 1; } - return opaque_programmer->erase(flash, blockaddr, blocklen); + return flash->pgm->opaque.erase(flash, blockaddr, blocklen); } void register_opaque_programmer(const struct opaque_programmer *pgm) { + struct registered_programmer rpgm; + if (!pgm->probe || !pgm->read || !pgm->write || !pgm->erase) { msg_perr("%s called with one of probe/read/write/erase being " "NULL. Please report a bug at flashrom at flashrom.org\n", __func__); return; } - opaque_programmer = pgm; - buses_supported |= BUS_PROG; + rpgm.buses_supported = BUS_PROG; + rpgm.opaque = *pgm; + register_programmer(&rpgm); } Index: flashrom-register_all_programmers_register_generic_structflashchip/dediprog.c =================================================================== --- flashrom-register_all_programmers_register_generic_structflashchip/dediprog.c (Revision 1463) +++ flashrom-register_all_programmers_register_generic_structflashchip/dediprog.c (Arbeitskopie) @@ -317,7 +317,7 @@ return ret; } -static int dediprog_spi_send_command(unsigned int writecnt, unsigned int readcnt, +static int dediprog_spi_send_command(struct flashchip *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { int ret; Index: flashrom-register_all_programmers_register_generic_structflashchip/spi25.c =================================================================== --- flashrom-register_all_programmers_register_generic_structflashchip/spi25.c (Revision 1463) +++ flashrom-register_all_programmers_register_generic_structflashchip/spi25.c (Arbeitskopie) @@ -29,13 +29,13 @@ #include "programmer.h" #include "spi.h" -static int spi_rdid(unsigned char *readarr, int bytes) +static int spi_rdid(struct flashchip *flash, unsigned char *readarr, int bytes) { static const unsigned char cmd[JEDEC_RDID_OUTSIZE] = { JEDEC_RDID }; int ret; int i; - ret = spi_send_command(sizeof(cmd), bytes, cmd, readarr); + ret = spi_send_command(flash, sizeof(cmd), bytes, cmd, readarr); if (ret) return ret; msg_cspew("RDID returned"); @@ -45,20 +45,20 @@ return 0; } -static int spi_rems(unsigned char *readarr) +static int spi_rems(struct flashchip *flash, unsigned char *readarr) { unsigned char cmd[JEDEC_REMS_OUTSIZE] = { JEDEC_REMS, 0, 0, 0 }; uint32_t readaddr; int ret; - ret = spi_send_command(sizeof(cmd), JEDEC_REMS_INSIZE, cmd, readarr); + ret = spi_send_command(flash, sizeof(cmd), JEDEC_REMS_INSIZE, cmd, readarr); if (ret == SPI_INVALID_ADDRESS) { /* Find the lowest even address allowed for reads. */ - readaddr = (spi_get_valid_read_addr() + 1) & ~1; + readaddr = (spi_get_valid_read_addr(flash) + 1) & ~1; cmd[1] = (readaddr >> 16) & 0xff, cmd[2] = (readaddr >> 8) & 0xff, cmd[3] = (readaddr >> 0) & 0xff, - ret = spi_send_command(sizeof(cmd), JEDEC_REMS_INSIZE, cmd, readarr); + ret = spi_send_command(flash, sizeof(cmd), JEDEC_REMS_INSIZE, cmd, readarr); } if (ret) return ret; @@ -66,21 +66,21 @@ return 0; } -static int spi_res(unsigned char *readarr, int bytes) +static int spi_res(struct flashchip *flash, unsigned char *readarr, int bytes) { unsigned char cmd[JEDEC_RES_OUTSIZE] = { JEDEC_RES, 0, 0, 0 }; uint32_t readaddr; int ret; int i; - ret = spi_send_command(sizeof(cmd), bytes, cmd, readarr); + ret = spi_send_command(flash, sizeof(cmd), bytes, cmd, readarr); if (ret == SPI_INVALID_ADDRESS) { /* Find the lowest even address allowed for reads. */ - readaddr = (spi_get_valid_read_addr() + 1) & ~1; + readaddr = (spi_get_valid_read_addr(flash) + 1) & ~1; cmd[1] = (readaddr >> 16) & 0xff, cmd[2] = (readaddr >> 8) & 0xff, cmd[3] = (readaddr >> 0) & 0xff, - ret = spi_send_command(sizeof(cmd), bytes, cmd, readarr); + ret = spi_send_command(flash, sizeof(cmd), bytes, cmd, readarr); } if (ret) return ret; @@ -91,13 +91,13 @@ return 0; } -int spi_write_enable(void) +int spi_write_enable(struct flashchip *flash) { static const unsigned char cmd[JEDEC_WREN_OUTSIZE] = { JEDEC_WREN }; int result; /* Send WREN (Write Enable) */ - result = spi_send_command(sizeof(cmd), 0, cmd, NULL); + result = spi_send_command(flash, sizeof(cmd), 0, cmd, NULL); if (result) msg_cerr("%s failed\n", __func__); @@ -105,12 +105,12 @@ return result; } -int spi_write_disable(void) +int spi_write_disable(struct flashchip *flash) { static const unsigned char cmd[JEDEC_WRDI_OUTSIZE] = { JEDEC_WRDI }; /* Send WRDI (Write Disable) */ - return spi_send_command(sizeof(cmd), 0, cmd, NULL); + return spi_send_command(flash, sizeof(cmd), 0, cmd, NULL); } static int probe_spi_rdid_generic(struct flashchip *flash, int bytes) @@ -119,7 +119,7 @@ uint32_t id1; uint32_t id2; - if (spi_rdid(readarr, bytes)) { + if (spi_rdid(flash, readarr, bytes)) { return 0; } @@ -177,7 +177,7 @@ /* Some SPI controllers do not support commands with writecnt=1 and * readcnt=4. */ - switch (spi_programmer->type) { + switch (flash->pgm->spi.type) { #if CONFIG_INTERNAL == 1 #if defined(__i386__) || defined(__x86_64__) case SPI_CONTROLLER_IT87XX: @@ -199,7 +199,7 @@ unsigned char readarr[JEDEC_REMS_INSIZE]; uint32_t id1, id2; - if (spi_rems(readarr)) { + if (spi_rems(flash, readarr)) { return 0; } @@ -242,7 +242,7 @@ /* Check if RDID is usable and does not return 0xff 0xff 0xff or * 0x00 0x00 0x00. In that case, RES is pointless. */ - if (!spi_rdid(readarr, 3) && memcmp(readarr, allff, 3) && + if (!spi_rdid(flash, readarr, 3) && memcmp(readarr, allff, 3) && memcmp(readarr, all00, 3)) { msg_cdbg("Ignoring RES in favour of RDID.\n"); return 0; @@ -250,13 +250,13 @@ /* Check if REMS is usable and does not return 0xff 0xff or * 0x00 0x00. In that case, RES is pointless. */ - if (!spi_rems(readarr) && memcmp(readarr, allff, JEDEC_REMS_INSIZE) && + if (!spi_rems(flash, readarr) && memcmp(readarr, allff, JEDEC_REMS_INSIZE) && memcmp(readarr, all00, JEDEC_REMS_INSIZE)) { msg_cdbg("Ignoring RES in favour of REMS.\n"); return 0; } - if (spi_res(readarr, 1)) { + if (spi_res(flash, readarr, 1)) { return 0; } @@ -279,7 +279,7 @@ unsigned char readarr[2]; uint32_t id1, id2; - if (spi_res(readarr, 2)) { + if (spi_res(flash, readarr, 2)) { return 0; } @@ -298,7 +298,7 @@ return 1; } -uint8_t spi_read_status_register(void) +uint8_t spi_read_status_register(struct flashchip *flash) { static const unsigned char cmd[JEDEC_RDSR_OUTSIZE] = { JEDEC_RDSR }; /* FIXME: No workarounds for driver/hardware bugs in generic code. */ @@ -306,7 +306,7 @@ int ret; /* Read Status Register */ - ret = spi_send_command(sizeof(cmd), sizeof(readarr), cmd, readarr); + ret = spi_send_command(flash, sizeof(cmd), sizeof(readarr), cmd, readarr); if (ret) msg_cerr("RDSR failed!\n"); @@ -414,7 +414,7 @@ { uint8_t status; - status = spi_read_status_register(); + status = spi_read_status_register(flash); msg_cdbg("Chip status register is %02x\n", status); switch (flash->manufacture_id) { case ST_ID: @@ -465,7 +465,7 @@ .readarr = NULL, }}; - result = spi_send_multicommand(cmds); + result = spi_send_multicommand(flash, cmds); if (result) { msg_cerr("%s failed during command execution\n", __func__); @@ -475,7 +475,7 @@ * This usually takes 1-85 s, so wait in 1 s steps. */ /* FIXME: We assume spi_read_status_register will never fail. */ - while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) + while (spi_read_status_register(flash) & JEDEC_RDSR_BIT_WIP) programmer_delay(1000 * 1000); /* FIXME: Check the status register for errors. */ return 0; @@ -502,7 +502,7 @@ .readarr = NULL, }}; - result = spi_send_multicommand(cmds); + result = spi_send_multicommand(flash, cmds); if (result) { msg_cerr("%s failed during command execution\n", __func__); return result; @@ -511,7 +511,7 @@ * This usually takes 1-85 s, so wait in 1 s steps. */ /* FIXME: We assume spi_read_status_register will never fail. */ - while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) + while (spi_read_status_register(flash) & JEDEC_RDSR_BIT_WIP) programmer_delay(1000 * 1000); /* FIXME: Check the status register for errors. */ return 0; @@ -543,7 +543,7 @@ .readarr = NULL, }}; - result = spi_send_multicommand(cmds); + result = spi_send_multicommand(flash, cmds); if (result) { msg_cerr("%s failed during command execution at address 0x%x\n", __func__, addr); @@ -552,7 +552,7 @@ /* Wait until the Write-In-Progress bit is cleared. * This usually takes 100-4000 ms, so wait in 100 ms steps. */ - while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) + while (spi_read_status_register(flash) & JEDEC_RDSR_BIT_WIP) programmer_delay(100 * 1000); /* FIXME: Check the status register for errors. */ return 0; @@ -589,7 +589,7 @@ .readarr = NULL, }}; - result = spi_send_multicommand(cmds); + result = spi_send_multicommand(flash, cmds); if (result) { msg_cerr("%s failed during command execution at address 0x%x\n", __func__, addr); @@ -598,7 +598,7 @@ /* Wait until the Write-In-Progress bit is cleared. * This usually takes 100-4000 ms, so wait in 100 ms steps. */ - while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) + while (spi_read_status_register(flash) & JEDEC_RDSR_BIT_WIP) programmer_delay(100 * 1000); /* FIXME: Check the status register for errors. */ return 0; @@ -633,7 +633,7 @@ .readarr = NULL, }}; - result = spi_send_multicommand(cmds); + result = spi_send_multicommand(flash, cmds); if (result) { msg_cerr("%s failed during command execution at address 0x%x\n", __func__, addr); @@ -642,7 +642,7 @@ /* Wait until the Write-In-Progress bit is cleared. * This usually takes 100-4000 ms, so wait in 100 ms steps. */ - while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) + while (spi_read_status_register(flash) & JEDEC_RDSR_BIT_WIP) programmer_delay(100 * 1000); /* FIXME: Check the status register for errors. */ return 0; @@ -675,7 +675,7 @@ .readarr = NULL, }}; - result = spi_send_multicommand(cmds); + result = spi_send_multicommand(flash, cmds); if (result) { msg_cerr("%s failed during command execution at address 0x%x\n", __func__, addr); @@ -684,7 +684,7 @@ /* Wait until the Write-In-Progress bit is cleared. * This usually takes 15-800 ms, so wait in 10 ms steps. */ - while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) + while (spi_read_status_register(flash) & JEDEC_RDSR_BIT_WIP) programmer_delay(10 * 1000); /* FIXME: Check the status register for errors. */ return 0; @@ -710,13 +710,13 @@ return spi_chip_erase_c7(flash); } -int spi_write_status_enable(void) +int spi_write_status_enable(struct flashchip *flash) { static const unsigned char cmd[JEDEC_EWSR_OUTSIZE] = { JEDEC_EWSR }; int result; /* Send EWSR (Enable Write Status Register). */ - result = spi_send_command(sizeof(cmd), JEDEC_EWSR_INSIZE, cmd, NULL); + result = spi_send_command(flash, sizeof(cmd), JEDEC_EWSR_INSIZE, cmd, NULL); if (result) msg_cerr("%s failed\n", __func__); @@ -751,7 +751,7 @@ .readarr = NULL, }}; - result = spi_send_multicommand(cmds); + result = spi_send_multicommand(flash, cmds); if (result) { msg_cerr("%s failed during command execution\n", __func__); @@ -766,7 +766,7 @@ * 100 ms, then wait in 10 ms steps until a total of 5 s have elapsed. */ programmer_delay(100 * 1000); - while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) { + while (spi_read_status_register(flash) & JEDEC_RDSR_BIT_WIP) { if (++i > 490) { msg_cerr("Error: WIP bit after WRSR never cleared\n"); return TIMEOUT_ERROR; @@ -799,7 +799,7 @@ .readarr = NULL, }}; - result = spi_send_multicommand(cmds); + result = spi_send_multicommand(flash, cmds); if (result) { msg_cerr("%s failed during command execution\n", __func__); @@ -814,7 +814,7 @@ * 100 ms, then wait in 10 ms steps until a total of 5 s have elapsed. */ programmer_delay(100 * 1000); - while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) { + while (spi_read_status_register(flash) & JEDEC_RDSR_BIT_WIP) { if (++i > 490) { msg_cerr("Error: WIP bit after WRSR never cleared\n"); return TIMEOUT_ERROR; @@ -840,7 +840,7 @@ return ret; } -int spi_byte_program(int addr, uint8_t databyte) +int spi_byte_program(struct flashchip *flash, int addr, uint8_t databyte) { int result; struct spi_command cmds[] = { @@ -867,7 +867,7 @@ .readarr = NULL, }}; - result = spi_send_multicommand(cmds); + result = spi_send_multicommand(flash, cmds); if (result) { msg_cerr("%s failed during command execution at address 0x%x\n", __func__, addr); @@ -875,7 +875,7 @@ return result; } -int spi_nbyte_program(int addr, uint8_t *bytes, int len) +int spi_nbyte_program(struct flashchip *flash, int addr, uint8_t *bytes, int len) { int result; /* FIXME: Switch to malloc based on len unless that kills speed. */ @@ -914,7 +914,7 @@ memcpy(&cmd[4], bytes, len); - result = spi_send_multicommand(cmds); + result = spi_send_multicommand(flash, cmds); if (result) { msg_cerr("%s failed during command execution at address 0x%x\n", __func__, addr); @@ -931,7 +931,7 @@ uint8_t status; int result; - status = spi_read_status_register(); + status = spi_read_status_register(flash); /* If block protection is disabled, stop here. */ if ((status & 0x3c) == 0) return 0; @@ -942,7 +942,7 @@ msg_cerr("spi_write_status_register failed\n"); return result; } - status = spi_read_status_register(); + status = spi_read_status_register(flash); if ((status & 0x3c) != 0) { msg_cerr("Block protection could not be disabled!\n"); return 1; @@ -950,7 +950,7 @@ return 0; } -int spi_nbyte_read(int address, uint8_t *bytes, int len) +int spi_nbyte_read(struct flashchip *flash, int address, uint8_t *bytes, int len) { const unsigned char cmd[JEDEC_READ_OUTSIZE] = { JEDEC_READ, @@ -960,7 +960,7 @@ }; /* Send Read */ - return spi_send_command(sizeof(cmd), len, cmd, bytes); + return spi_send_command(flash, sizeof(cmd), len, cmd, bytes); } /* @@ -992,7 +992,7 @@ lenhere = min(start + len, (i + 1) * page_size) - starthere; for (j = 0; j < lenhere; j += chunksize) { toread = min(chunksize, lenhere - j); - rc = spi_nbyte_read(starthere + j, buf + starthere - start + j, toread); + rc = spi_nbyte_read(flash, starthere + j, buf + starthere - start + j, toread); if (rc) break; } @@ -1037,10 +1037,10 @@ lenhere = min(start + len, (i + 1) * page_size) - starthere; for (j = 0; j < lenhere; j += chunksize) { towrite = min(chunksize, lenhere - j); - rc = spi_nbyte_program(starthere + j, buf + starthere - start + j, towrite); + rc = spi_nbyte_program(flash, starthere + j, buf + starthere - start + j, towrite); if (rc) break; - while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) + while (spi_read_status_register(flash) & JEDEC_RDSR_BIT_WIP) programmer_delay(10); } if (rc) @@ -1062,10 +1062,10 @@ int i, result = 0; for (i = start; i < start + len; i++) { - result = spi_byte_program(i, buf[i - start]); + result = spi_byte_program(flash, i, buf[i - start]); if (result) return 1; - while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) + while (spi_read_status_register(flash) & JEDEC_RDSR_BIT_WIP) programmer_delay(10); } @@ -1104,7 +1104,7 @@ .readarr = NULL, }}; - switch (spi_programmer->type) { + switch (flash->pgm->spi.type) { #if CONFIG_INTERNAL == 1 #if defined(__i386__) || defined(__x86_64__) case SPI_CONTROLLER_IT87XX: @@ -1150,7 +1150,7 @@ } - result = spi_send_multicommand(cmds); + result = spi_send_multicommand(flash, cmds); if (result) { msg_cerr("%s failed during start command execution\n", __func__); @@ -1159,7 +1159,7 @@ */ return result; } - while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) + while (spi_read_status_register(flash) & JEDEC_RDSR_BIT_WIP) programmer_delay(10); /* We already wrote 2 bytes in the multicommand step. */ @@ -1169,15 +1169,15 @@ while (pos < start + len - 1) { cmd[1] = buf[pos++ - start]; cmd[2] = buf[pos++ - start]; - spi_send_command(JEDEC_AAI_WORD_PROGRAM_CONT_OUTSIZE, 0, cmd, NULL); - while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) + spi_send_command(flash, JEDEC_AAI_WORD_PROGRAM_CONT_OUTSIZE, 0, cmd, NULL); + while (spi_read_status_register(flash) & JEDEC_RDSR_BIT_WIP) programmer_delay(10); } /* Use WRDI to exit AAI mode. This needs to be done before issuing any * other non-AAI command. */ - spi_write_disable(); + spi_write_disable(flash); /* Write remaining byte (if any). */ if (pos < start + len) { Index: flashrom-register_all_programmers_register_generic_structflashchip/pm49fl00x.c =================================================================== --- flashrom-register_all_programmers_register_generic_structflashchip/pm49fl00x.c (Revision 1463) +++ flashrom-register_all_programmers_register_generic_structflashchip/pm49fl00x.c (Arbeitskopie) @@ -22,7 +22,7 @@ #include "flash.h" -static void write_lockbits_49fl00x(chipaddr bios, int size, +static void write_lockbits_49fl00x(const struct flashchip *flash, chipaddr bios, int size, unsigned char bits, int block_size) { int i, left = size; @@ -32,18 +32,18 @@ if (block_size == 16384 && i % 2) continue; - chip_writeb(bits, bios + (i * block_size) + 2); + chip_writeb(flash, bits, bios + (i * block_size) + 2); } } int unlock_49fl00x(struct flashchip *flash) { - write_lockbits_49fl00x(flash->virtual_registers, flash->total_size * 1024, 0, flash->page_size); + write_lockbits_49fl00x(flash, flash->virtual_registers, flash->total_size * 1024, 0, flash->page_size); return 0; } int lock_49fl00x(struct flashchip *flash) { - write_lockbits_49fl00x(flash->virtual_registers, flash->total_size * 1024, 1, flash->page_size); + write_lockbits_49fl00x(flash, flash->virtual_registers, flash->total_size * 1024, 1, flash->page_size); return 0; } Index: flashrom-register_all_programmers_register_generic_structflashchip/it85spi.c =================================================================== --- flashrom-register_all_programmers_register_generic_structflashchip/it85spi.c (Revision 1463) +++ flashrom-register_all_programmers_register_generic_structflashchip/it85spi.c (Arbeitskopie) @@ -270,7 +270,7 @@ return 0; } -static int it85xx_spi_send_command(unsigned int writecnt, unsigned int readcnt, +static int it85xx_spi_send_command(struct flashchip *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); static const struct spi_programmer spi_programmer_it85xx = { @@ -320,7 +320,7 @@ * 3. read date from LPC/FWH address 0xffff_fdxxh (drive CE# low and get * data from MISO) */ -static int it85xx_spi_send_command(unsigned int writecnt, unsigned int readcnt, +static int it85xx_spi_send_command(struct flashchip *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { int i; Index: flashrom-register_all_programmers_register_generic_structflashchip/buspirate_spi.c =================================================================== --- flashrom-register_all_programmers_register_generic_structflashchip/buspirate_spi.c (Revision 1463) +++ flashrom-register_all_programmers_register_generic_structflashchip/buspirate_spi.c (Arbeitskopie) @@ -86,7 +86,7 @@ return 0; } -static int buspirate_spi_send_command(unsigned int writecnt, unsigned int readcnt, +static int buspirate_spi_send_command(struct flashchip *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); static const struct spi_programmer spi_programmer_buspirate = { @@ -291,7 +291,7 @@ return 0; } -static int buspirate_spi_send_command(unsigned int writecnt, unsigned int readcnt, +static int buspirate_spi_send_command(struct flashchip *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { static unsigned char *buf = NULL; Index: flashrom-register_all_programmers_register_generic_structflashchip/linux_spi.c =================================================================== --- flashrom-register_all_programmers_register_generic_structflashchip/linux_spi.c (Revision 1463) +++ flashrom-register_all_programmers_register_generic_structflashchip/linux_spi.c (Arbeitskopie) @@ -34,7 +34,7 @@ static int fd = -1; static int linux_spi_shutdown(void *data); -static int linux_spi_send_command(unsigned int writecnt, unsigned int readcnt, +static int linux_spi_send_command(struct flashchip *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *txbuf, unsigned char *rxbuf); static int linux_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); @@ -107,7 +107,7 @@ return 0; } -static int linux_spi_send_command(unsigned int writecnt, unsigned int readcnt, +static int linux_spi_send_command(struct flashchip *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *txbuf, unsigned char *rxbuf) { struct spi_ioc_transfer msg[2] = { Index: flashrom-register_all_programmers_register_generic_structflashchip/w29ee011.c =================================================================== --- flashrom-register_all_programmers_register_generic_structflashchip/w29ee011.c (Revision 1463) +++ flashrom-register_all_programmers_register_generic_structflashchip/w29ee011.c (Arbeitskopie) @@ -38,29 +38,29 @@ } /* Issue JEDEC Product ID Entry command */ - chip_writeb(0xAA, bios + 0x5555); + chip_writeb(flash, 0xAA, bios + 0x5555); programmer_delay(10); - chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(flash, 0x55, bios + 0x2AAA); programmer_delay(10); - chip_writeb(0x80, bios + 0x5555); + chip_writeb(flash, 0x80, bios + 0x5555); programmer_delay(10); - chip_writeb(0xAA, bios + 0x5555); + chip_writeb(flash, 0xAA, bios + 0x5555); programmer_delay(10); - chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(flash, 0x55, bios + 0x2AAA); programmer_delay(10); - chip_writeb(0x60, bios + 0x5555); + chip_writeb(flash, 0x60, bios + 0x5555); programmer_delay(10); /* Read product ID */ - id1 = chip_readb(bios); - id2 = chip_readb(bios + 0x01); + id1 = chip_readb(flash, bios); + id2 = chip_readb(flash, bios + 0x01); /* Issue JEDEC Product ID Exit command */ - chip_writeb(0xAA, bios + 0x5555); + chip_writeb(flash, 0xAA, bios + 0x5555); programmer_delay(10); - chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(flash, 0x55, bios + 0x2AAA); programmer_delay(10); - chip_writeb(0xF0, bios + 0x5555); + chip_writeb(flash, 0xF0, bios + 0x5555); programmer_delay(10); msg_cdbg("%s: id1 0x%02x, id2 0x%02x\n", __func__, id1, id2); Index: flashrom-register_all_programmers_register_generic_structflashchip/atahpt.c =================================================================== --- flashrom-register_all_programmers_register_generic_structflashchip/atahpt.c (Revision 1463) +++ flashrom-register_all_programmers_register_generic_structflashchip/atahpt.c (Arbeitskopie) @@ -40,6 +40,8 @@ {}, }; +static void atahpt_chip_writeb(const struct flashchip *flash, uint8_t val, chipaddr addr); +static uint8_t atahpt_chip_readb(const struct flashchip *flash, const chipaddr addr); static const struct par_programmer par_programmer_atahpt = { .chip_readb = atahpt_chip_readb, .chip_readw = fallback_chip_readw, @@ -80,13 +82,13 @@ return 0; } -void atahpt_chip_writeb(uint8_t val, chipaddr addr) +static void atahpt_chip_writeb(const struct flashchip *flash, uint8_t val, chipaddr addr) { OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR); OUTB(val, io_base_addr + BIOS_ROM_DATA); } -uint8_t atahpt_chip_readb(const chipaddr addr) +static uint8_t atahpt_chip_readb(const struct flashchip *flash, const chipaddr addr) { OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR); return INB(io_base_addr + BIOS_ROM_DATA); Index: flashrom-register_all_programmers_register_generic_structflashchip/nic3com.c =================================================================== --- flashrom-register_all_programmers_register_generic_structflashchip/nic3com.c (Revision 1463) +++ flashrom-register_all_programmers_register_generic_structflashchip/nic3com.c (Arbeitskopie) @@ -55,6 +55,8 @@ {}, }; +static void nic3com_chip_writeb(const struct flashchip *flash, uint8_t val, chipaddr addr); +static uint8_t nic3com_chip_readb(const struct flashchip *flash, const chipaddr addr); static const struct par_programmer par_programmer_nic3com = { .chip_readb = nic3com_chip_readb, .chip_readw = fallback_chip_readw, @@ -116,13 +118,13 @@ return 0; } -void nic3com_chip_writeb(uint8_t val, chipaddr addr) +static void nic3com_chip_writeb(const struct flashchip *flash, uint8_t val, chipaddr addr) { OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR); OUTB(val, io_base_addr + BIOS_ROM_DATA); } -uint8_t nic3com_chip_readb(const chipaddr addr) +static uint8_t nic3com_chip_readb(const struct flashchip *flash, const chipaddr addr) { OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR); return INB(io_base_addr + BIOS_ROM_DATA); Index: flashrom-register_all_programmers_register_generic_structflashchip/spi.c =================================================================== --- flashrom-register_all_programmers_register_generic_structflashchip/spi.c (Revision 1463) +++ flashrom-register_all_programmers_register_generic_structflashchip/spi.c (Arbeitskopie) @@ -30,45 +30,33 @@ #include "programmer.h" #include "spi.h" -const struct spi_programmer spi_programmer_none = { - .type = SPI_CONTROLLER_NONE, - .max_data_read = MAX_DATA_UNSPECIFIED, - .max_data_write = MAX_DATA_UNSPECIFIED, - .command = NULL, - .multicommand = NULL, - .read = NULL, - .write_256 = NULL, -}; - -const struct spi_programmer *spi_programmer = &spi_programmer_none; - -int spi_send_command(unsigned int writecnt, unsigned int readcnt, +int spi_send_command(struct flashchip *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { - if (!spi_programmer->command) { + if (!flash->pgm->spi.command) { msg_perr("%s called, but SPI is unsupported on this " "hardware. Please report a bug at " "flashrom at flashrom.org\n", __func__); return 1; } - return spi_programmer->command(writecnt, readcnt, + return flash->pgm->spi.command(flash, writecnt, readcnt, writearr, readarr); } -int spi_send_multicommand(struct spi_command *cmds) +int spi_send_multicommand(struct flashchip *flash, struct spi_command *cmds) { - if (!spi_programmer->multicommand) { + if (!flash->pgm->spi.multicommand) { msg_perr("%s called, but SPI is unsupported on this " "hardware. Please report a bug at " "flashrom at flashrom.org\n", __func__); return 1; } - return spi_programmer->multicommand(cmds); + return flash->pgm->spi.multicommand(flash, cmds); } -int default_spi_send_command(unsigned int writecnt, unsigned int readcnt, +int default_spi_send_command(struct flashchip *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { struct spi_command cmd[] = { @@ -84,14 +72,14 @@ .readarr = NULL, }}; - return spi_send_multicommand(cmd); + return spi_send_multicommand(flash, cmd); } -int default_spi_send_multicommand(struct spi_command *cmds) +int default_spi_send_multicommand(struct flashchip *flash, struct spi_command *cmds) { int result = 0; for (; (cmds->writecnt || cmds->readcnt) && !result; cmds++) { - result = spi_send_command(cmds->writecnt, cmds->readcnt, + result = spi_send_command(flash, cmds->writecnt, cmds->readcnt, cmds->writearr, cmds->readarr); } return result; @@ -99,7 +87,7 @@ int default_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) { - int max_data = spi_programmer->max_data_read; + int max_data = flash->pgm->spi.max_data_read; if (max_data == MAX_DATA_UNSPECIFIED) { msg_perr("%s called, but SPI read chunk size not defined " "on this hardware. Please report a bug at " @@ -111,7 +99,7 @@ int default_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) { - int max_data = spi_programmer->max_data_write; + int max_data = flash->pgm->spi.max_data_write; if (max_data == MAX_DATA_UNSPECIFIED) { msg_perr("%s called, but SPI write chunk size not defined " "on this hardware. Please report a bug at " @@ -124,7 +112,7 @@ int spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len) { int addrbase = 0; - if (!spi_programmer->read) { + if (!flash->pgm->spi.read) { msg_perr("%s called, but SPI read is unsupported on this " "hardware. Please report a bug at " "flashrom at flashrom.org\n", __func__); @@ -135,7 +123,7 @@ * address. Highest possible address with the current SPI implementation * means 0xffffff, the highest unsigned 24bit number. */ - addrbase = spi_get_valid_read_addr(); + addrbase = spi_get_valid_read_addr(flash); if (addrbase + flash->total_size * 1024 > (1 << 24)) { msg_perr("Flash chip size exceeds the allowed access window. "); msg_perr("Read will probably fail.\n"); @@ -150,7 +138,7 @@ "access window.\n"); msg_perr("Read will probably return garbage.\n"); } - return spi_programmer->read(flash, buf, addrbase + start, len); + return flash->pgm->spi.read(flash, buf, addrbase + start, len); } /* @@ -162,14 +150,14 @@ /* real chunksize is up to 256, logical chunksize is 256 */ int spi_chip_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) { - if (!spi_programmer->write_256) { + if (!flash->pgm->spi.write_256) { msg_perr("%s called, but SPI page write is unsupported on this " "hardware. Please report a bug at " "flashrom at flashrom.org\n", __func__); return 1; } - return spi_programmer->write_256(flash, buf, start, len); + return flash->pgm->spi.write_256(flash, buf, start, len); } /* @@ -177,9 +165,9 @@ * be the lowest allowed address for all commands which take an address. * This is a programmer limitation. */ -uint32_t spi_get_valid_read_addr(void) +uint32_t spi_get_valid_read_addr(struct flashchip *flash) { - switch (spi_programmer->type) { + switch (flash->pgm->spi.type) { #if CONFIG_INTERNAL == 1 #if defined(__i386__) || defined(__x86_64__) case SPI_CONTROLLER_ICH7: @@ -194,6 +182,9 @@ void register_spi_programmer(const struct spi_programmer *pgm) { - spi_programmer = pgm; - buses_supported |= BUS_SPI; + struct registered_programmer rpgm; + + rpgm.buses_supported = BUS_SPI; + rpgm.spi = *pgm; + register_programmer(&rpgm); } Index: flashrom-register_all_programmers_register_generic_structflashchip/ft2232_spi.c =================================================================== --- flashrom-register_all_programmers_register_generic_structflashchip/ft2232_spi.c (Revision 1463) +++ flashrom-register_all_programmers_register_generic_structflashchip/ft2232_spi.c (Arbeitskopie) @@ -144,7 +144,7 @@ return 0; } -static int ft2232_spi_send_command(unsigned int writecnt, unsigned int readcnt, +static int ft2232_spi_send_command(struct flashchip *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); static const struct spi_programmer spi_programmer_ft2232 = { @@ -342,7 +342,7 @@ } /* Returns 0 upon success, a negative number upon errors. */ -static int ft2232_spi_send_command(unsigned int writecnt, unsigned int readcnt, +static int ft2232_spi_send_command(struct flashchip *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { struct ftdi_context *ftdic = &ftdic_context; Index: flashrom-register_all_programmers_register_generic_structflashchip/satasii.c =================================================================== --- flashrom-register_all_programmers_register_generic_structflashchip/satasii.c (Revision 1463) +++ flashrom-register_all_programmers_register_generic_structflashchip/satasii.c (Arbeitskopie) @@ -42,6 +42,8 @@ {}, }; +static void satasii_chip_writeb(const struct flashchip *flash, uint8_t val, chipaddr addr); +static uint8_t satasii_chip_readb(const struct flashchip *flash, const chipaddr addr); static const struct par_programmer par_programmer_satasii = { .chip_readb = satasii_chip_readb, .chip_readw = fallback_chip_readw, @@ -95,7 +97,7 @@ return 0; } -void satasii_chip_writeb(uint8_t val, chipaddr addr) +static void satasii_chip_writeb(const struct flashchip *flash, uint8_t val, chipaddr addr) { uint32_t ctrl_reg, data_reg; @@ -112,7 +114,7 @@ while (pci_mmio_readl(sii_bar) & (1 << 25)) ; } -uint8_t satasii_chip_readb(const chipaddr addr) +static uint8_t satasii_chip_readb(const struct flashchip *flash, const chipaddr addr) { uint32_t ctrl_reg; Index: flashrom-register_all_programmers_register_generic_structflashchip/wbsio_spi.c =================================================================== --- flashrom-register_all_programmers_register_generic_structflashchip/wbsio_spi.c (Revision 1463) +++ flashrom-register_all_programmers_register_generic_structflashchip/wbsio_spi.c (Arbeitskopie) @@ -60,7 +60,7 @@ return flashport; } -static int wbsio_spi_send_command(unsigned int writecnt, unsigned int readcnt, +static int wbsio_spi_send_command(struct flashchip *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); static int wbsio_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); @@ -110,7 +110,7 @@ * Would one more byte of RAM in the chip (to get all 24 bits) really make * such a big difference? */ -static int wbsio_spi_send_command(unsigned int writecnt, unsigned int readcnt, +static int wbsio_spi_send_command(struct flashchip *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { int i; Index: flashrom-register_all_programmers_register_generic_structflashchip/sst28sf040.c =================================================================== --- flashrom-register_all_programmers_register_generic_structflashchip/sst28sf040.c (Revision 1463) +++ flashrom-register_all_programmers_register_generic_structflashchip/sst28sf040.c (Arbeitskopie) @@ -34,13 +34,13 @@ { chipaddr bios = flash->virtual_memory; - chip_readb(bios + 0x1823); - chip_readb(bios + 0x1820); - chip_readb(bios + 0x1822); - chip_readb(bios + 0x0418); - chip_readb(bios + 0x041B); - chip_readb(bios + 0x0419); - chip_readb(bios + 0x040A); + chip_readb(flash, bios + 0x1823); + chip_readb(flash, bios + 0x1820); + chip_readb(flash, bios + 0x1822); + chip_readb(flash, bios + 0x0418); + chip_readb(flash, bios + 0x041B); + chip_readb(flash, bios + 0x0419); + chip_readb(flash, bios + 0x040A); return 0; } @@ -49,13 +49,13 @@ { chipaddr bios = flash->virtual_memory; - chip_readb(bios + 0x1823); - chip_readb(bios + 0x1820); - chip_readb(bios + 0x1822); - chip_readb(bios + 0x0418); - chip_readb(bios + 0x041B); - chip_readb(bios + 0x0419); - chip_readb(bios + 0x041A); + chip_readb(flash, bios + 0x1823); + chip_readb(flash, bios + 0x1820); + chip_readb(flash, bios + 0x1822); + chip_readb(flash, bios + 0x0418); + chip_readb(flash, bios + 0x041B); + chip_readb(flash, bios + 0x0419); + chip_readb(flash, bios + 0x041A); return 0; } @@ -65,11 +65,11 @@ chipaddr bios = flash->virtual_memory; /* This command sequence is very similar to erase_block_82802ab. */ - chip_writeb(AUTO_PG_ERASE1, bios); - chip_writeb(AUTO_PG_ERASE2, bios + address); + chip_writeb(flash, AUTO_PG_ERASE1, bios); + chip_writeb(flash, AUTO_PG_ERASE2, bios + address); /* wait for Toggle bit ready */ - toggle_ready_jedec(bios); + toggle_ready_jedec(flash, bios); /* FIXME: Check the status register for errors. */ return 0; @@ -90,11 +90,11 @@ continue; } /*issue AUTO PROGRAM command */ - chip_writeb(AUTO_PGRM, dst); - chip_writeb(*src++, dst++); + chip_writeb(flash, AUTO_PGRM, dst); + chip_writeb(flash, *src++, dst++); /* wait for Toggle bit ready */ - toggle_ready_jedec(bios); + toggle_ready_jedec(flash, bios); } return 0; @@ -104,11 +104,11 @@ { chipaddr bios = flash->virtual_memory; - chip_writeb(CHIP_ERASE, bios); - chip_writeb(CHIP_ERASE, bios); + chip_writeb(flash, CHIP_ERASE, bios); + chip_writeb(flash, CHIP_ERASE, bios); programmer_delay(10); - toggle_ready_jedec(bios); + toggle_ready_jedec(flash, bios); /* FIXME: Check the status register for errors. */ return 0; Index: flashrom-register_all_programmers_register_generic_structflashchip/stm50flw0x0x.c =================================================================== --- flashrom-register_all_programmers_register_generic_structflashchip/stm50flw0x0x.c (Revision 1463) +++ flashrom-register_all_programmers_register_generic_structflashchip/stm50flw0x0x.c (Arbeitskopie) @@ -60,8 +60,8 @@ // unlock each 4k-sector for (j = 0; j < 0x10000; j += 0x1000) { msg_cdbg("unlocking at 0x%x\n", offset + j); - chip_writeb(unlock_sector, wrprotect + offset + j); - if (chip_readb(wrprotect + offset + j) != unlock_sector) { + chip_writeb(flash, unlock_sector, wrprotect + offset + j); + if (chip_readb(flash, wrprotect + offset + j) != unlock_sector) { msg_cerr("Cannot unlock sector @ 0x%x\n", offset + j); return -1; @@ -69,8 +69,8 @@ } } else { msg_cdbg("unlocking at 0x%x\n", offset); - chip_writeb(unlock_sector, wrprotect + offset); - if (chip_readb(wrprotect + offset) != unlock_sector) { + chip_writeb(flash, unlock_sector, wrprotect + offset); + if (chip_readb(flash, wrprotect + offset) != unlock_sector) { msg_cerr("Cannot unlock sector @ 0x%x\n", offset); return -1; } @@ -99,10 +99,10 @@ chipaddr bios = flash->virtual_memory + sector; // clear status register - chip_writeb(0x50, bios); + chip_writeb(flash, 0x50, bios); // now start it - chip_writeb(0x32, bios); - chip_writeb(0xd0, bios); + chip_writeb(flash, 0x32, bios); + chip_writeb(flash, 0xd0, bios); programmer_delay(10); wait_82802ab(flash); Index: flashrom-register_all_programmers_register_generic_structflashchip/nicintel.c =================================================================== --- flashrom-register_all_programmers_register_generic_structflashchip/nicintel.c (Revision 1463) +++ flashrom-register_all_programmers_register_generic_structflashchip/nicintel.c (Arbeitskopie) @@ -43,6 +43,8 @@ #define CSR_FCR 0x0c +static void nicintel_chip_writeb(const struct flashchip *flash, uint8_t val, chipaddr addr); +static uint8_t nicintel_chip_readb(const struct flashchip *flash, const chipaddr addr); static const struct par_programmer par_programmer_nicintel = { .chip_readb = nicintel_chip_readb, .chip_readw = fallback_chip_readw, @@ -117,12 +119,12 @@ return 1; } -void nicintel_chip_writeb(uint8_t val, chipaddr addr) +static void nicintel_chip_writeb(const struct flashchip *flash, uint8_t val, chipaddr addr) { pci_mmio_writeb(val, nicintel_bar + (addr & NICINTEL_MEMMAP_MASK)); } -uint8_t nicintel_chip_readb(const chipaddr addr) +static uint8_t nicintel_chip_readb(const struct flashchip *flash, const chipaddr addr) { return pci_mmio_readb(nicintel_bar + (addr & NICINTEL_MEMMAP_MASK)); } Index: flashrom-register_all_programmers_register_generic_structflashchip/sb600spi.c =================================================================== --- flashrom-register_all_programmers_register_generic_structflashchip/sb600spi.c (Revision 1463) +++ flashrom-register_all_programmers_register_generic_structflashchip/sb600spi.c (Arbeitskopie) @@ -88,7 +88,7 @@ ; } -static int sb600_spi_send_command(unsigned int writecnt, unsigned int readcnt, +static int sb600_spi_send_command(struct flashchip *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { int count; Index: flashrom-register_all_programmers_register_generic_structflashchip/programmer.c =================================================================== --- flashrom-register_all_programmers_register_generic_structflashchip/programmer.c (Revision 1463) +++ flashrom-register_all_programmers_register_generic_structflashchip/programmer.c (Arbeitskopie) @@ -1,7 +1,7 @@ /* * This file is part of the flashrom project. * - * Copyright (C) 2009,2010 Carl-Daniel Hailfinger + * Copyright (C) 2009,2010,2011 Carl-Daniel Hailfinger * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -21,19 +21,6 @@ #include "flash.h" #include "programmer.h" -static const struct par_programmer par_programmer_none = { - .chip_readb = noop_chip_readb, - .chip_readw = fallback_chip_readw, - .chip_readl = fallback_chip_readl, - .chip_readn = fallback_chip_readn, - .chip_writeb = noop_chip_writeb, - .chip_writew = fallback_chip_writew, - .chip_writel = fallback_chip_writel, - .chip_writen = fallback_chip_writen, -}; - -const struct par_programmer *par_programmer = &par_programmer_none; - /* No-op shutdown() for programmers which don't need special handling */ int noop_shutdown(void) { @@ -53,66 +40,98 @@ } /* No-op chip_writeb() for drivers not supporting addr/data pair accesses */ -uint8_t noop_chip_readb(const chipaddr addr) +uint8_t noop_chip_readb(const struct flashchip *flash, const chipaddr addr) { return 0xff; } /* No-op chip_writeb() for drivers not supporting addr/data pair accesses */ -void noop_chip_writeb(uint8_t val, chipaddr addr) +void noop_chip_writeb(const struct flashchip *flash, uint8_t val, chipaddr addr) { } /* Little-endian fallback for drivers not supporting 16 bit accesses */ -void fallback_chip_writew(uint16_t val, chipaddr addr) +void fallback_chip_writew(const struct flashchip *flash, uint16_t val, chipaddr addr) { - chip_writeb(val & 0xff, addr); - chip_writeb((val >> 8) & 0xff, addr + 1); + chip_writeb(flash, val & 0xff, addr); + chip_writeb(flash, (val >> 8) & 0xff, addr + 1); } /* Little-endian fallback for drivers not supporting 16 bit accesses */ -uint16_t fallback_chip_readw(const chipaddr addr) +uint16_t fallback_chip_readw(const struct flashchip *flash, const chipaddr addr) { uint16_t val; - val = chip_readb(addr); - val |= chip_readb(addr + 1) << 8; + val = chip_readb(flash, addr); + val |= chip_readb(flash, addr + 1) << 8; return val; } /* Little-endian fallback for drivers not supporting 32 bit accesses */ -void fallback_chip_writel(uint32_t val, chipaddr addr) +void fallback_chip_writel(const struct flashchip *flash, uint32_t val, chipaddr addr) { - chip_writew(val & 0xffff, addr); - chip_writew((val >> 16) & 0xffff, addr + 2); + chip_writew(flash, val & 0xffff, addr); + chip_writew(flash, (val >> 16) & 0xffff, addr + 2); } /* Little-endian fallback for drivers not supporting 32 bit accesses */ -uint32_t fallback_chip_readl(const chipaddr addr) +uint32_t fallback_chip_readl(const struct flashchip *flash, const chipaddr addr) { uint32_t val; - val = chip_readw(addr); - val |= chip_readw(addr + 2) << 16; + val = chip_readw(flash, addr); + val |= chip_readw(flash, addr + 2) << 16; return val; } -void fallback_chip_writen(uint8_t *buf, chipaddr addr, size_t len) +void fallback_chip_writen(const struct flashchip *flash, uint8_t *buf, chipaddr addr, size_t len) { size_t i; for (i = 0; i < len; i++) - chip_writeb(buf[i], addr + i); + chip_writeb(flash, buf[i], addr + i); return; } -void fallback_chip_readn(uint8_t *buf, chipaddr addr, size_t len) +void fallback_chip_readn(const struct flashchip *flash, uint8_t *buf, chipaddr addr, size_t len) { size_t i; for (i = 0; i < len; i++) - buf[i] = chip_readb(addr + i); + buf[i] = chip_readb(flash, addr + i); return; } void register_par_programmer(const struct par_programmer *pgm, const enum chipbustype buses) { - par_programmer = pgm; - buses_supported |= buses; + struct registered_programmer rpgm; + + rpgm.buses_supported = buses; + rpgm.par = *pgm; + register_programmer(&rpgm); } + +/* The limit of 4 is totally arbitrary. */ +#define PROGRAMMERS_MAX 4 +struct registered_programmer registered_programmers[PROGRAMMERS_MAX]; +int registered_programmer_count = 0; + +int register_programmer(struct registered_programmer *pgm) +{ + if (registered_programmer_count >= PROGRAMMERS_MAX) { + msg_perr("Tried to register more than %i programmer " + "interfaces.\n", PROGRAMMERS_MAX); + return 1; + } + registered_programmers[registered_programmer_count] = *pgm; + registered_programmer_count++; + + return 0; +} + +enum chipbustype get_buses_supported(void) +{ + int i; + enum chipbustype ret = BUS_NONE; + + for (i = 0; i < registered_programmer_count; i++) + ret |= registered_programmers[i].buses_supported; + + return ret; +} Index: flashrom-register_all_programmers_register_generic_structflashchip/flashrom.c =================================================================== --- flashrom-register_all_programmers_register_generic_structflashchip/flashrom.c (Revision 1463) +++ flashrom-register_all_programmers_register_generic_structflashchip/flashrom.c (Arbeitskopie) @@ -46,9 +46,6 @@ static char *programmer_param = NULL; -/* Supported buses for the current programmer. */ -enum chipbustype buses_supported; - /* * Programmers supporting multiple buses can have differing size limits on * each bus. Store the limits for each bus in a common struct. @@ -314,7 +311,6 @@ .fwh = 0xffffffff, .spi = 0xffffffff, }; - buses_supported = BUS_NONE; /* Default to top aligned flash at 4 GB. */ flashbase = 0; /* Registering shutdown functions is now allowed. */ @@ -359,44 +355,44 @@ programmer_table[programmer].unmap_flash_region(virt_addr, len); } -void chip_writeb(uint8_t val, chipaddr addr) +void chip_writeb(const struct flashchip *flash, uint8_t val, chipaddr addr) { - par_programmer->chip_writeb(val, addr); + flash->pgm->par.chip_writeb(flash, val, addr); } -void chip_writew(uint16_t val, chipaddr addr) +void chip_writew(const struct flashchip *flash, uint16_t val, chipaddr addr) { - par_programmer->chip_writew(val, addr); + flash->pgm->par.chip_writew(flash, val, addr); } -void chip_writel(uint32_t val, chipaddr addr) +void chip_writel(const struct flashchip *flash, uint32_t val, chipaddr addr) { - par_programmer->chip_writel(val, addr); + flash->pgm->par.chip_writel(flash, val, addr); } -void chip_writen(uint8_t *buf, chipaddr addr, size_t len) +void chip_writen(const struct flashchip *flash, uint8_t *buf, chipaddr addr, size_t len) { - par_programmer->chip_writen(buf, addr, len); + flash->pgm->par.chip_writen(flash, buf, addr, len); } -uint8_t chip_readb(const chipaddr addr) +uint8_t chip_readb(const struct flashchip *flash, const chipaddr addr) { - return par_programmer->chip_readb(addr); + return flash->pgm->par.chip_readb(flash, addr); } -uint16_t chip_readw(const chipaddr addr) +uint16_t chip_readw(const struct flashchip *flash, const chipaddr addr) { - return par_programmer->chip_readw(addr); + return flash->pgm->par.chip_readw(flash, addr); } -uint32_t chip_readl(const chipaddr addr) +uint32_t chip_readl(const struct flashchip *flash, const chipaddr addr) { - return par_programmer->chip_readl(addr); + return flash->pgm->par.chip_readl(flash, addr); } -void chip_readn(uint8_t *buf, chipaddr addr, size_t len) +void chip_readn(const struct flashchip *flash, uint8_t *buf, chipaddr addr, size_t len) { - par_programmer->chip_readn(buf, addr, len); + flash->pgm->par.chip_readn(flash, buf, addr, len); } void programmer_delay(int usecs) @@ -414,7 +410,7 @@ int read_memmapped(struct flashchip *flash, uint8_t *buf, int start, int len) { - chip_readn(buf, flash->virtual_memory + start, len); + chip_readn(flash, buf, flash->virtual_memory + start, len); return 0; } @@ -936,7 +932,8 @@ return 1; } -int probe_flash(int startchip, struct flashchip *fill_flash, int force) +int probe_flash(struct registered_programmer *pgm, int startchip, + struct flashchip *fill_flash, int force) { const struct flashchip *flash; unsigned long base = 0; @@ -948,11 +945,12 @@ for (flash = flashchips + startchip; flash && flash->name; flash++) { if (chip_to_probe && strcmp(flash->name, chip_to_probe) != 0) continue; - buses_common = buses_supported & flash->bustype; + buses_common = pgm->buses_supported & flash->bustype; if (!buses_common) { +#if 0 // Does not really make sense anymore if we use a programmer-centric walk. msg_gspew("Probing for %s %s, %d kB: skipped. ", flash->vendor, flash->name, flash->total_size); - tmp = flashbuses_to_text(buses_supported); + tmp = flashbuses_to_text(get_buses_supported()); msg_gspew("Host bus type %s ", tmp); free(tmp); tmp = flashbuses_to_text(flash->bustype); @@ -960,6 +958,7 @@ tmp); free(tmp); msg_gspew("\n"); +#endif continue; } msg_gdbg("Probing for %s %s, %d kB: ", @@ -975,6 +974,7 @@ /* Start filling in the dynamic data. */ *fill_flash = *flash; + fill_flash->pgm = pgm; base = flashbase ? flashbase : (0xffffffff - size + 1); fill_flash->virtual_memory = (chipaddr)programmer_map_flash_region("flash chip", base, size); Index: flashrom-register_all_programmers_register_generic_structflashchip/programmer.h =================================================================== --- flashrom-register_all_programmers_register_generic_structflashchip/programmer.h (Revision 1463) +++ flashrom-register_all_programmers_register_generic_structflashchip/programmer.h (Arbeitskopie) @@ -93,8 +93,8 @@ int (*init) (void); - void * (*map_flash_region) (const char *descr, unsigned long phys_addr, - size_t len); + void *(*map_flash_region) (const char *descr, unsigned long phys_addr, + size_t len); void (*unmap_flash_region) (void *virt_addr, size_t len); void (*delay) (int usecs); @@ -300,13 +300,6 @@ int register_superio(struct superio s); extern enum chipbustype internal_buses_supported; int internal_init(void); -void internal_chip_writeb(uint8_t val, chipaddr addr); -void internal_chip_writew(uint16_t val, chipaddr addr); -void internal_chip_writel(uint32_t val, chipaddr addr); -uint8_t internal_chip_readb(const chipaddr addr); -uint16_t internal_chip_readw(const chipaddr addr); -uint32_t internal_chip_readl(const chipaddr addr); -void internal_chip_readn(uint8_t *buf, const chipaddr addr, size_t len); #endif /* hwaccess.c */ @@ -341,91 +334,46 @@ void rmmio_valw(void *addr); void rmmio_vall(void *addr); -/* programmer.c */ -int noop_shutdown(void); -void *fallback_map(const char *descr, unsigned long phys_addr, size_t len); -void fallback_unmap(void *virt_addr, size_t len); -uint8_t noop_chip_readb(const chipaddr addr); -void noop_chip_writeb(uint8_t val, chipaddr addr); -void fallback_chip_writew(uint16_t val, chipaddr addr); -void fallback_chip_writel(uint32_t val, chipaddr addr); -void fallback_chip_writen(uint8_t *buf, chipaddr addr, size_t len); -uint16_t fallback_chip_readw(const chipaddr addr); -uint32_t fallback_chip_readl(const chipaddr addr); -void fallback_chip_readn(uint8_t *buf, const chipaddr addr, size_t len); -struct par_programmer { - void (*chip_writeb) (uint8_t val, chipaddr addr); - void (*chip_writew) (uint16_t val, chipaddr addr); - void (*chip_writel) (uint32_t val, chipaddr addr); - void (*chip_writen) (uint8_t *buf, chipaddr addr, size_t len); - uint8_t (*chip_readb) (const chipaddr addr); - uint16_t (*chip_readw) (const chipaddr addr); - uint32_t (*chip_readl) (const chipaddr addr); - void (*chip_readn) (uint8_t *buf, const chipaddr addr, size_t len); -}; -extern const struct par_programmer *par_programmer; -void register_par_programmer(const struct par_programmer *pgm, const enum chipbustype buses); - /* dummyflasher.c */ #if CONFIG_DUMMY == 1 int dummy_init(void); void *dummy_map(const char *descr, unsigned long phys_addr, size_t len); void dummy_unmap(void *virt_addr, size_t len); -void dummy_chip_writeb(uint8_t val, chipaddr addr); -void dummy_chip_writew(uint16_t val, chipaddr addr); -void dummy_chip_writel(uint32_t val, chipaddr addr); -void dummy_chip_writen(uint8_t *buf, chipaddr addr, size_t len); -uint8_t dummy_chip_readb(const chipaddr addr); -uint16_t dummy_chip_readw(const chipaddr addr); -uint32_t dummy_chip_readl(const chipaddr addr); -void dummy_chip_readn(uint8_t *buf, const chipaddr addr, size_t len); #endif /* nic3com.c */ #if CONFIG_NIC3COM == 1 int nic3com_init(void); -void nic3com_chip_writeb(uint8_t val, chipaddr addr); -uint8_t nic3com_chip_readb(const chipaddr addr); extern const struct pcidev_status nics_3com[]; #endif /* gfxnvidia.c */ #if CONFIG_GFXNVIDIA == 1 int gfxnvidia_init(void); -void gfxnvidia_chip_writeb(uint8_t val, chipaddr addr); -uint8_t gfxnvidia_chip_readb(const chipaddr addr); extern const struct pcidev_status gfx_nvidia[]; #endif /* drkaiser.c */ #if CONFIG_DRKAISER == 1 int drkaiser_init(void); -void drkaiser_chip_writeb(uint8_t val, chipaddr addr); -uint8_t drkaiser_chip_readb(const chipaddr addr); extern const struct pcidev_status drkaiser_pcidev[]; #endif /* nicrealtek.c */ #if CONFIG_NICREALTEK == 1 int nicrealtek_init(void); -void nicrealtek_chip_writeb(uint8_t val, chipaddr addr); -uint8_t nicrealtek_chip_readb(const chipaddr addr); extern const struct pcidev_status nics_realtek[]; #endif /* nicnatsemi.c */ #if CONFIG_NICNATSEMI == 1 int nicnatsemi_init(void); -void nicnatsemi_chip_writeb(uint8_t val, chipaddr addr); -uint8_t nicnatsemi_chip_readb(const chipaddr addr); extern const struct pcidev_status nics_natsemi[]; #endif /* nicintel.c */ #if CONFIG_NICINTEL == 1 int nicintel_init(void); -void nicintel_chip_writeb(uint8_t val, chipaddr addr); -uint8_t nicintel_chip_readb(const chipaddr addr); extern const struct pcidev_status nics_intel[]; #endif @@ -444,24 +392,18 @@ /* satamv.c */ #if CONFIG_SATAMV == 1 int satamv_init(void); -void satamv_chip_writeb(uint8_t val, chipaddr addr); -uint8_t satamv_chip_readb(const chipaddr addr); extern const struct pcidev_status satas_mv[]; #endif /* satasii.c */ #if CONFIG_SATASII == 1 int satasii_init(void); -void satasii_chip_writeb(uint8_t val, chipaddr addr); -uint8_t satasii_chip_readb(const chipaddr addr); extern const struct pcidev_status satas_sii[]; #endif /* atahpt.c */ #if CONFIG_ATAHPT == 1 int atahpt_init(void); -void atahpt_chip_writeb(uint8_t val, chipaddr addr); -uint8_t atahpt_chip_readb(const chipaddr addr); extern const struct pcidev_status ata_hpt[]; #endif @@ -556,7 +498,6 @@ SPI_CONTROLLER_SERPROG, #endif }; -extern const int spi_programmer_count; #define MAX_DATA_UNSPECIFIED 0 #define MAX_DATA_READ_UNLIMITED 64 * 1024 @@ -565,19 +506,18 @@ enum spi_controller type; int max_data_read; int max_data_write; - int (*command)(unsigned int writecnt, unsigned int readcnt, + int (*command)(struct flashchip *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); - int (*multicommand)(struct spi_command *cmds); + int (*multicommand)(struct flashchip *flash, struct spi_command *cmds); /* Optimized functions for this programmer */ int (*read)(struct flashchip *flash, uint8_t *buf, int start, int len); int (*write_256)(struct flashchip *flash, uint8_t *buf, int start, int len); }; -extern const struct spi_programmer *spi_programmer; -int default_spi_send_command(unsigned int writecnt, unsigned int readcnt, +int default_spi_send_command(struct flashchip *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); -int default_spi_send_multicommand(struct spi_command *cmds); +int default_spi_send_multicommand(struct flashchip *flash, struct spi_command *cmds); int default_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); int default_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); void register_spi_programmer(const struct spi_programmer *programmer); @@ -632,12 +572,44 @@ extern const struct opaque_programmer *opaque_programmer; void register_opaque_programmer(const struct opaque_programmer *pgm); +/* programmer.c */ +int noop_shutdown(void); +void *fallback_map(const char *descr, unsigned long phys_addr, size_t len); +void fallback_unmap(void *virt_addr, size_t len); +uint8_t noop_chip_readb(const struct flashchip *flash, const chipaddr addr); +void noop_chip_writeb(const struct flashchip *flash, uint8_t val, chipaddr addr); +void fallback_chip_writew(const struct flashchip *flash, uint16_t val, chipaddr addr); +void fallback_chip_writel(const struct flashchip *flash, uint32_t val, chipaddr addr); +void fallback_chip_writen(const struct flashchip *flash, uint8_t *buf, chipaddr addr, size_t len); +uint16_t fallback_chip_readw(const struct flashchip *flash, const chipaddr addr); +uint32_t fallback_chip_readl(const struct flashchip *flash, const chipaddr addr); +void fallback_chip_readn(const struct flashchip *flash, uint8_t *buf, const chipaddr addr, size_t len); +struct par_programmer { + void (*chip_writeb) (const struct flashchip *flash, uint8_t val, chipaddr addr); + void (*chip_writew) (const struct flashchip *flash, uint16_t val, chipaddr addr); + void (*chip_writel) (const struct flashchip *flash, uint32_t val, chipaddr addr); + void (*chip_writen) (const struct flashchip *flash, uint8_t *buf, chipaddr addr, size_t len); + uint8_t (*chip_readb) (const struct flashchip *flash, const chipaddr addr); + uint16_t (*chip_readw) (const struct flashchip *flash, const chipaddr addr); + uint32_t (*chip_readl) (const struct flashchip *flash, const chipaddr addr); + void (*chip_readn) (const struct flashchip *flash, uint8_t *buf, const chipaddr addr, size_t len); +}; +void register_par_programmer(const struct par_programmer *pgm, const enum chipbustype buses); +struct registered_programmer { + enum chipbustype buses_supported; + union { + struct par_programmer par; + struct spi_programmer spi; + struct opaque_programmer opaque; + }; +}; +extern struct registered_programmer registered_programmers[]; +extern int registered_programmer_count; +int register_programmer(struct registered_programmer *pgm); + /* serprog.c */ #if CONFIG_SERPROG == 1 int serprog_init(void); -void serprog_chip_writeb(uint8_t val, chipaddr addr); -uint8_t serprog_chip_readb(const chipaddr addr); -void serprog_chip_readn(uint8_t *buf, const chipaddr addr, size_t len); void serprog_delay(int usecs); #endif Index: flashrom-register_all_programmers_register_generic_structflashchip/chipdrivers.h =================================================================== --- flashrom-register_all_programmers_register_generic_structflashchip/chipdrivers.h (Revision 1463) +++ flashrom-register_all_programmers_register_generic_structflashchip/chipdrivers.h (Arbeitskopie) @@ -33,8 +33,8 @@ int probe_spi_rems(struct flashchip *flash); int probe_spi_res1(struct flashchip *flash); int probe_spi_res2(struct flashchip *flash); -int spi_write_enable(void); -int spi_write_disable(void); +int spi_write_enable(struct flashchip *flash); +int spi_write_disable(struct flashchip *flash); int spi_block_erase_20(struct flashchip *flash, unsigned int addr, unsigned int blocklen); int spi_block_erase_52(struct flashchip *flash, unsigned int addr, unsigned int blocklen); int spi_block_erase_d7(struct flashchip *flash, unsigned int addr, unsigned int blocklen); @@ -44,16 +44,16 @@ int spi_chip_write_1(struct flashchip *flash, uint8_t *buf, int start, int len); int spi_chip_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); int spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len); -uint8_t spi_read_status_register(void); +uint8_t spi_read_status_register(struct flashchip *flash); int spi_write_status_register(struct flashchip *flash, int status); void spi_prettyprint_status_register_bit(uint8_t status, int bit); void spi_prettyprint_status_register_bp3210(uint8_t status, int bp); void spi_prettyprint_status_register_welwip(uint8_t status); int spi_prettyprint_status_register(struct flashchip *flash); int spi_disable_blockprotect(struct flashchip *flash); -int spi_byte_program(int addr, uint8_t databyte); -int spi_nbyte_program(int addr, uint8_t *bytes, int len); -int spi_nbyte_read(int addr, uint8_t *bytes, int len); +int spi_byte_program(struct flashchip *flash, int addr, uint8_t databyte); +int spi_nbyte_program(struct flashchip *flash, int addr, uint8_t *bytes, int len); +int spi_nbyte_read(struct flashchip *flash, int addr, uint8_t *bytes, int len); int spi_read_chunked(struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize); int spi_write_chunked(struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize); int spi_aai_write(struct flashchip *flash, uint8_t *buf, int start, int len); @@ -95,9 +95,9 @@ /* jedec.c */ uint8_t oddparity(uint8_t val); -void toggle_ready_jedec(chipaddr dst); -void data_polling_jedec(chipaddr dst, uint8_t data); -int write_byte_program_jedec(chipaddr bios, uint8_t *src, +void toggle_ready_jedec(struct flashchip *flash, chipaddr dst); +void data_polling_jedec(struct flashchip *flash, chipaddr dst, uint8_t data); +int write_byte_program_jedec(struct flashchip *flash, chipaddr bios, uint8_t *src, chipaddr dst); int probe_jedec(struct flashchip *flash); int write_jedec(struct flashchip *flash, uint8_t *buf, int start, int len); @@ -111,7 +111,7 @@ int block_erase_m29f400bt(struct flashchip *flash, unsigned int start, unsigned int len); int block_erase_chip_m29f400bt(struct flashchip *flash, unsigned int start, unsigned int len); int write_m29f400bt(struct flashchip *flash, uint8_t *buf, int start, int len); -void protect_m29f400bt(chipaddr bios); +void protect_m29f400bt(struct flashchip *flash, chipaddr bios); /* pm49fl00x.c */ int unlock_49fl00x(struct flashchip *flash); Index: flashrom-register_all_programmers_register_generic_structflashchip/m29f400bt.c =================================================================== --- flashrom-register_all_programmers_register_generic_structflashchip/m29f400bt.c (Revision 1463) +++ flashrom-register_all_programmers_register_generic_structflashchip/m29f400bt.c (Arbeitskopie) @@ -35,17 +35,17 @@ chipaddr dst = flash->virtual_memory + start; for (i = 0; i < len; i++) { - chip_writeb(0xAA, bios + 0xAAA); - chip_writeb(0x55, bios + 0x555); - chip_writeb(0xA0, bios + 0xAAA); + chip_writeb(flash, 0xAA, bios + 0xAAA); + chip_writeb(flash, 0x55, bios + 0x555); + chip_writeb(flash, 0xA0, bios + 0xAAA); /* transfer data from source to destination */ - chip_writeb(*src, dst); - toggle_ready_jedec(dst); + chip_writeb(flash, *src, dst); + toggle_ready_jedec(flash, dst); #if 0 /* We only want to print something in the error case. */ msg_cerr("Value in the flash at address 0x%lx = %#x, want %#x\n", - (dst - bios), chip_readb(dst), *src); + (dst - bios), chip_readb(flash, dst), *src); #endif dst++; src++; @@ -60,21 +60,21 @@ chipaddr bios = flash->virtual_memory; uint8_t id1, id2; - chip_writeb(0xAA, bios + 0xAAA); - chip_writeb(0x55, bios + 0x555); - chip_writeb(0x90, bios + 0xAAA); + chip_writeb(flash, 0xAA, bios + 0xAAA); + chip_writeb(flash, 0x55, bios + 0x555); + chip_writeb(flash, 0x90, bios + 0xAAA); programmer_delay(10); - id1 = chip_readb(bios); + id1 = chip_readb(flash, bios); /* The data sheet says id2 is at (bios + 0x01) and id2 listed in * flash.h does not match. It should be possible to use JEDEC probe. */ - id2 = chip_readb(bios + 0x02); + id2 = chip_readb(flash, bios + 0x02); - chip_writeb(0xAA, bios + 0xAAA); - chip_writeb(0x55, bios + 0x555); - chip_writeb(0xF0, bios + 0xAAA); + chip_writeb(flash, 0xAA, bios + 0xAAA); + chip_writeb(flash, 0x55, bios + 0x555); + chip_writeb(flash, 0xF0, bios + 0xAAA); programmer_delay(10); @@ -90,16 +90,16 @@ { chipaddr bios = flash->virtual_memory; - chip_writeb(0xAA, bios + 0xAAA); - chip_writeb(0x55, bios + 0x555); - chip_writeb(0x80, bios + 0xAAA); + chip_writeb(flash, 0xAA, bios + 0xAAA); + chip_writeb(flash, 0x55, bios + 0x555); + chip_writeb(flash, 0x80, bios + 0xAAA); - chip_writeb(0xAA, bios + 0xAAA); - chip_writeb(0x55, bios + 0x555); - chip_writeb(0x10, bios + 0xAAA); + chip_writeb(flash, 0xAA, bios + 0xAAA); + chip_writeb(flash, 0x55, bios + 0x555); + chip_writeb(flash, 0x10, bios + 0xAAA); programmer_delay(10); - toggle_ready_jedec(bios); + toggle_ready_jedec(flash, bios); /* FIXME: Check the status register for errors. */ return 0; @@ -110,16 +110,16 @@ chipaddr bios = flash->virtual_memory; chipaddr dst = bios + start; - chip_writeb(0xAA, bios + 0xAAA); - chip_writeb(0x55, bios + 0x555); - chip_writeb(0x80, bios + 0xAAA); + chip_writeb(flash, 0xAA, bios + 0xAAA); + chip_writeb(flash, 0x55, bios + 0x555); + chip_writeb(flash, 0x80, bios + 0xAAA); - chip_writeb(0xAA, bios + 0xAAA); - chip_writeb(0x55, bios + 0x555); - chip_writeb(0x30, dst); + chip_writeb(flash, 0xAA, bios + 0xAAA); + chip_writeb(flash, 0x55, bios + 0x555); + chip_writeb(flash, 0x30, dst); programmer_delay(10); - toggle_ready_jedec(bios); + toggle_ready_jedec(flash, bios); /* FIXME: Check the status register for errors. */ return 0; -- http://www.hailfinger.org/ From jakllsch at kollasch.net Sun Nov 13 00:43:40 2011 From: jakllsch at kollasch.net (Jonathan A. Kollasch) Date: Sat, 12 Nov 2011 23:43:40 +0000 Subject: [flashrom] [patch] move ich_init_opcodes() call back to where it was before r1461 Message-ID: <20111112234339.GA573@tazenda.kollasch.net> ich_init_opcodes() needs to be called after ichspi_lock is set. Signed-off-by: Jonathan A. Kollasch -------------- next part -------------- Index: ichspi.c =================================================================== --- ichspi.c (revision 1463) +++ ichspi.c (working copy) @@ -1562,8 +1562,6 @@ /* Assign Virtual Address */ ich_spibar = rcrb + spibar_offset; - ich_init_opcodes(); - switch (ich_generation) { case CHIPSET_ICH7: msg_pdbg("0x00: 0x%04x (SPIS)\n", @@ -1603,6 +1601,7 @@ } ich_set_bbar(0); register_spi_programmer(&spi_programmer_ich7); + ich_init_opcodes(); break; case CHIPSET_ICH8: default: /* Future version might behave the same */ @@ -1754,6 +1753,7 @@ register_opaque_programmer(&opaque_programmer_ich_hwseq); } else { register_spi_programmer(&spi_programmer_ich9); + ich_init_opcodes(); } break; } From stefan.tauner at student.tuwien.ac.at Sun Nov 13 01:27:45 2011 From: stefan.tauner at student.tuwien.ac.at (Stefan Tauner) Date: Sun, 13 Nov 2011 01:27:45 +0100 Subject: [flashrom] [patch] move ich_init_opcodes() call back to where it was before r1461 In-Reply-To: <20111112234339.GA573@tazenda.kollasch.net> References: <20111112234339.GA573@tazenda.kollasch.net> Message-ID: <201111130027.pAD0Rbik022669@mail2.student.tuwien.ac.at> On Sat, 12 Nov 2011 23:43:40 +0000 "Jonathan A. Kollasch" wrote: > ich_init_opcodes() needs to be called after ichspi_lock is set. > > Signed-off-by: Jonathan A. Kollasch > thanks jonathan for that patch, but this wont work as it should due to ich_missing_opcodes. i have prepared the attached patch already and will commit it as soon as carldani had time to discuss it. it changes the output which might not what we want: [?] SPIBAR = 0xfed1c000 + 0x3800 0x04: 0xe008 (HSFS) HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=1, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=1 WARNING: SPI Configuration Lockdown activated. Reading OPCODES... done 0x06: 0x3f00 (HSFC) HSFC: FGO=0, FCYCLE=0, FDBC=63, SME=0 0x08: 0x00003000 (FADDR) 0x50: 0x00000a0b (FRAP) [?] the problem is "Reading OPCODES... done" which is quite unexpected in the middle of the register outputs...(?) another option would be to make ichspi_lock a function or macro. performance is probably not an issue(?) and we would avoid such ordering problems. -- Kind regards/Mit freundlichen Gr??en, Stefan Tauner -------------- next part -------------- A non-text attachment was scrubbed... Name: 0001-ichspi-fix-ich_init_opcodes-calls-in-ich_init_spi.patch Type: text/x-patch Size: 1745 bytes Desc: not available URL: From c-d.hailfinger.devel.2006 at gmx.net Sun Nov 13 16:12:32 2011 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Sun, 13 Nov 2011 16:12:32 +0100 Subject: [flashrom] [patch] move ich_init_opcodes() call back to where it was before r1461 In-Reply-To: <201111130027.pAD0Rbik022669@mail2.student.tuwien.ac.at> References: <20111112234339.GA573@tazenda.kollasch.net> <201111130027.pAD0Rbik022669@mail2.student.tuwien.ac.at> Message-ID: <4EBFDE60.5090905@gmx.net> Am 13.11.2011 01:27 schrieb Stefan Tauner: > On Sat, 12 Nov 2011 23:43:40 +0000 > "Jonathan A. Kollasch" wrote: > >> > ich_init_opcodes() needs to be called after ichspi_lock is set. >> > >> > Signed-off-by: Jonathan A. Kollasch >> > > thanks jonathan for that patch, but this wont work as it should due to > ich_missing_opcodes. > i have prepared the attached patch already and will commit it as soon as > carldani had time to discuss it. > it changes the output which might not what we want: > [?] > SPIBAR = 0xfed1c000 + 0x3800 > 0x04: 0xe008 (HSFS) > HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=1, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=1 > WARNING: SPI Configuration Lockdown activated. > Reading OPCODES... done > 0x06: 0x3f00 (HSFC) > HSFC: FGO=0, FCYCLE=0, FDBC=63, SME=0 > 0x08: 0x00003000 (FADDR) > 0x50: 0x00000a0b (FRAP) > [?] > > the problem is "Reading OPCODES... done" which is quite unexpected in > the middle of the register outputs...(?) > > another option would be to make ichspi_lock a function or macro. > performance is probably not an issue(?) and we would avoid such ordering > problems. > > > From: Stefan Tauner > Date: Sat, 12 Nov 2011 22:44:26 +0100 > Subject: [PATCH] ichspi: fix ich_init_opcodes() calls in ich_init_spi() > > By calling it early ichspi_lock was not set up correctly in accordance > with the corresponding register, hence ich_init_opcodes() was always > trying to programming the opcodes instead of reading them in from the > opmenu in case of a locked down configuration. > > Thanks to Jonathan Kollasch for reporting this bug. You forgot the A. in his name. > Signed-off-by: Stefan Tauner The cosmetic change in the output is not an issue for me. Acked-by: Carl-Daniel Hailfinger Regards, Carl-Daniel -- http://www.hailfinger.org/ From svn at flashrom.org Sun Nov 13 16:17:11 2011 From: svn at flashrom.org (repository service) Date: Sun, 13 Nov 2011 16:17:11 +0100 Subject: [flashrom] [commit] r1464 - trunk Message-ID: Author: stefanct Date: Sun Nov 13 16:17:10 2011 New Revision: 1464 URL: http://flashrom.org/trac/flashrom/changeset/1464 Log: ichspi: fix ich_init_opcodes() calls in ich_init_spi() By calling it early ichspi_lock was not set up correctly in accordance with the corresponding register, hence ich_init_opcodes() was always trying to programming the opcodes instead of reading them in from the opmenu in case of a locked down configuration. Thanks to Jonathan A. Kollasch for reporting this bug. Signed-off-by: Stefan Tauner Acked-by: Carl-Daniel Hailfinger Modified: trunk/ichspi.c Modified: trunk/ichspi.c ============================================================================== --- trunk/ichspi.c Thu Nov 10 00:40:00 2011 (r1463) +++ trunk/ichspi.c Sun Nov 13 16:17:10 2011 (r1464) @@ -1562,8 +1562,6 @@ /* Assign Virtual Address */ ich_spibar = rcrb + spibar_offset; - ich_init_opcodes(); - switch (ich_generation) { case CHIPSET_ICH7: msg_pdbg("0x00: 0x%04x (SPIS)\n", @@ -1601,6 +1599,7 @@ msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); ichspi_lock = 1; } + ich_init_opcodes(); ich_set_bbar(0); register_spi_programmer(&spi_programmer_ich7); break; @@ -1643,6 +1642,7 @@ "by the FRAP and FREG registers are NOT in " "effect. Please note that Protected\n" "Range (PR) restrictions still apply.\n"); + ich_init_opcodes(); if (desc_valid) { tmp2 = mmio_readw(ich_spibar + ICH9_REG_HSFC); From stefan.tauner at student.tuwien.ac.at Sun Nov 13 16:18:14 2011 From: stefan.tauner at student.tuwien.ac.at (Stefan Tauner) Date: Sun, 13 Nov 2011 16:18:14 +0100 Subject: [flashrom] [patch] move ich_init_opcodes() call back to where it was before r1461 In-Reply-To: <4EBFDE60.5090905@gmx.net> References: <20111112234339.GA573@tazenda.kollasch.net> <201111130027.pAD0Rbik022669@mail2.student.tuwien.ac.at> <4EBFDE60.5090905@gmx.net> Message-ID: <201111131518.pADFI9qB021224@mail2.student.tuwien.ac.at> On Sun, 13 Nov 2011 16:12:32 +0100 Carl-Daniel Hailfinger wrote: > Am 13.11.2011 01:27 schrieb Stefan Tauner: > > Thanks to Jonathan Kollasch for reporting this bug. > > You forgot the A. in his name. fixed :) > The cosmetic change in the output is not an issue for me. > > Acked-by: Carl-Daniel Hailfinger thanks, committed in r1464 -- Kind regards/Mit freundlichen Gr??en, Stefan Tauner From c-d.hailfinger.devel.2006 at gmx.net Sun Nov 13 23:23:39 2011 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Sun, 13 Nov 2011 23:23:39 +0100 Subject: [flashrom] [PATCH] Unsignify lengths and addresses in chip functions and structs In-Reply-To: <1316390511-31596-1-git-send-email-stefan.tauner@student.tuwien.ac.at> References: <201109180042.p8I0gEYE024377@mail2.student.tuwien.ac.at> <1316390511-31596-1-git-send-email-stefan.tauner@student.tuwien.ac.at> Message-ID: <4EC0436B.2090800@gmx.net> Am 19.09.2011 02:01 schrieb Stefan Tauner: > Push those changes forward where needed to prevent new sign > conversion warnings where possible. Thanks for your patch. > this is a crude rework of the reverted patch. i have tried to push > unsignedness wherever possible, but there are some problems: > ffs, min, max and some library/system calls require signed ints or > return them or both. We might want to provide type-safe min/max macros for those cases. An example is at http://gcc.gnu.org/onlinedocs/gcc/Typeof.html Not essential for this patch, but might be nice to have anyway. Later. > Signed-off-by: Stefan Tauner > > > diff --git a/flash.h b/flash.h > index 535c1b8..e7bfd4e 100644 > --- a/flash.h > +++ b/flash.h > @@ -121,8 +121,10 @@ struct flashchip { > > int (*probe) (struct flashchip *flash); > > - /* Delay after "enter/exit ID mode" commands in microseconds. */ > - int probe_timing; > + /* Delay after "enter/exit ID mode" commands in microseconds. > + * NB: negative values have special meanings, see TIMING_* below. > + */ > + signed int probe_timing; AFAICS the C standard defines that int is always signed. The only exception is char which is implementation-defined. Please kill signed here, but keep your comment. > > /* > * Erase blocks and associated erase function. Any chip erase function > diff --git a/ft2232_spi.c b/ft2232_spi.c > index 8ab89fa..8f00685 100644 > --- a/ft2232_spi.c > +++ b/ft2232_spi.c > @@ -106,10 +106,10 @@ static const char *get_ft2232_vendorname(int ft2232_vid, int ft2232_type) > } > > static int send_buf(struct ftdi_context *ftdic, const unsigned char *buf, > - int size) > + unsigned int size) > { > int r; > - r = ftdi_write_data(ftdic, (unsigned char *) buf, size); > + r = ftdi_write_data(ftdic, (unsigned char *) buf, (int)size); This cast is a sign that something is odd. Can you keep size as a signed int? > if (r < 0) { > msg_perr("ftdi_write_data: %d, %s\n", r, > ftdi_get_error_string(ftdic)); > @@ -119,19 +119,19 @@ static int send_buf(struct ftdi_context *ftdic, const unsigned char *buf, > } > > static int get_buf(struct ftdi_context *ftdic, const unsigned char *buf, > - int size) > + unsigned int size) > { > int r; > > while (size > 0) { > - r = ftdi_read_data(ftdic, (unsigned char *) buf, size); > + r = ftdi_read_data(ftdic, (unsigned char *) buf, (int)size); Same here. > if (r < 0) { > msg_perr("ftdi_read_data: %d, %s\n", r, > ftdi_get_error_string(ftdic)); > return 1; > } > - buf += r; > - size -= r; > + buf += (unsigned int)r; > + size -= (unsigned int)r; ... > } > return 0; > } > @@ -332,9 +332,10 @@ static int ft2232_spi_send_command(unsigned int writecnt, unsigned int readcnt, > struct ftdi_context *ftdic = &ftdic_context; > static unsigned char *buf = NULL; > /* failed is special. We use bitwise ops, but it is essentially bool. */ > - int i = 0, ret = 0, failed = 0; > - int bufsize; > - static int oldbufsize = 0; > + int ret = 0, failed = 0; > + unsigned int i = 0; > + unsigned int bufsize; > + static unsigned int oldbufsize = 0; > > if (writecnt > 65536 || readcnt > 65536) > return SPI_INVALID_LENGTH; get_buf and send_buf calls should be checked for size>=INT_MAX and the cast should happen in the call, not in get_buf/send_buf. > diff --git a/serprog.c b/serprog.c > index 9d554c9..94ae1c6 100644 > --- a/serprog.c > +++ b/serprog.c > @@ -707,7 +707,7 @@ uint8_t serprog_chip_readb(const chipaddr addr) > /* Local version that really does the job, doesn't care of max_read_n. */ > static void sp_do_read_n(uint8_t * buf, const chipaddr addr, size_t len) > { > - int rd_bytes = 0; > + unsigned int rd_bytes = 0; > unsigned char sbuf[6]; > msg_pspew("%s: addr=0x%lx len=%lu\n", __func__, addr, (unsigned long)len); > /* Stream the read-n -- as above. */ > @@ -725,7 +725,7 @@ static void sp_do_read_n(uint8_t * buf, const chipaddr addr, size_t len) > int r = read(sp_fd, buf + rd_bytes, len - rd_bytes); > if (r <= 0) > sp_die("Error: cannot read read-n data"); > - rd_bytes += r; > + rd_bytes += (unsigned int)r; Odd cast, but safe. You correctly analyzed that situation. > } while (rd_bytes != len); > return; > } > The flashrom.c changes were really hard to verify, but that's not your fault. The code in there is not easy to understand, but you got it exactly right. With the above comments this is Acked-by: Carl-Daniel Hailfinger Regards, Carl-Daniel -- http://www.hailfinger.org/ From c-d.hailfinger.devel.2006 at gmx.net Sun Nov 13 23:32:49 2011 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Sun, 13 Nov 2011 23:32:49 +0100 Subject: [flashrom] [PATCH] Create a directory for documentation files In-Reply-To: <1316305864-19614-1-git-send-email-stefan.tauner@student.tuwien.ac.at> References: <4E74A6C1.2090208@gmx.net> <1316305864-19614-1-git-send-email-stefan.tauner@student.tuwien.ac.at> Message-ID: <4EC04591.5060403@gmx.net> Am 18.09.2011 02:31 schrieb Stefan Tauner: > Move the serprog specification there and document a few things we could not > figure out on intel platforms yet. > > Signed-off-by: Stefan Tauner Acked-by: Carl-Daniel Hailfinger Regards, Carl-Daniel -- http://www.hailfinger.org/ From stefan.tauner at student.tuwien.ac.at Sun Nov 13 23:43:25 2011 From: stefan.tauner at student.tuwien.ac.at (Stefan Tauner) Date: Sun, 13 Nov 2011 23:43:25 +0100 Subject: [flashrom] [PATCH] Unsignify lengths and addresses in chip functions and structs In-Reply-To: <4EC0436B.2090800@gmx.net> References: <201109180042.p8I0gEYE024377@mail2.student.tuwien.ac.at> <1316390511-31596-1-git-send-email-stefan.tauner@student.tuwien.ac.at> <4EC0436B.2090800@gmx.net> Message-ID: <201111132243.pADMhLQb018443@mail2.student.tuwien.ac.at> On Sun, 13 Nov 2011 23:23:39 +0100 Carl-Daniel Hailfinger wrote: > > - /* Delay after "enter/exit ID mode" commands in microseconds. */ > > - int probe_timing; > > + /* Delay after "enter/exit ID mode" commands in microseconds. > > + * NB: negative values have special meanings, see TIMING_* below. > > + */ > > + signed int probe_timing; > > AFAICS the C standard defines that int is always signed. The only > exception is char which is implementation-defined. Please kill signed > here, but keep your comment. this was on purpose to make it really, really obvious to anyone reading the code that this is not just an unsigned delay (even if he ignores the comment). :) because you know... one could think that and change it in a patch which gets acked and committed by accident and produce really odd bugs ;) will review the other comments later, thanks! -- Kind regards/Mit freundlichen Gr??en, Stefan Tauner From svn at flashrom.org Mon Nov 14 00:03:31 2011 From: svn at flashrom.org (repository service) Date: Mon, 14 Nov 2011 00:03:31 +0100 Subject: [flashrom] [commit] r1465 - in trunk: . Documentation Message-ID: Author: stefanct Date: Mon Nov 14 00:03:30 2011 New Revision: 1465 URL: http://flashrom.org/trac/flashrom/changeset/1465 Log: Create a directory for documentation files Move the serprog specification there and document a few things we could not figure out on intel platforms yet. Signed-off-by: Stefan Tauner Acked-by: Carl-Daniel Hailfinger Added: trunk/Documentation/ trunk/Documentation/mysteries_intel.txt (contents, props changed) trunk/Documentation/serprog-protocol.txt (contents, props changed) - copied, changed from r1464, trunk/serprog-protocol.txt Deleted: trunk/serprog-protocol.txt Added: trunk/Documentation/mysteries_intel.txt ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/Documentation/mysteries_intel.txt Mon Nov 14 00:03:30 2011 (r1465) @@ -0,0 +1,18 @@ += BBAR on ICH8 = + There is no sign of BBAR (BIOS Base Address Configuration Register) in the + public datasheet (or specification update) of the ICH8. Also, the offset of + that register has changed between ICH7 (SPIBAR + 50h) and ICH9 (SPIBAR + + A0h), so we have no clue if or where it is on ICH8. Out current policy is to + not touch it at all and assume/hope it is 0. + += Accesses beyond region bounds in descriptor mode = + Intel's flash image tool will always expand the last region so that it covers + the whole flash chip, but some boards ship with a different configuration. + It seems that in descriptor mode all addresses outside the used regions can not + be accessed whatsoever. This is not specified anywhere publicly as far as we + could tell. flashrom does not handle this explicitly yet. It will just fail + when trying to touch an address outside of any region. + See also http://www.flashrom.org/pipermail/flashrom/2011-August/007606.html + += Unlocking the ME region = +TODO Copied and modified: trunk/Documentation/serprog-protocol.txt (from r1464, trunk/serprog-protocol.txt) ============================================================================== From stefan.tauner at student.tuwien.ac.at Mon Nov 14 00:04:24 2011 From: stefan.tauner at student.tuwien.ac.at (Stefan Tauner) Date: Mon, 14 Nov 2011 00:04:24 +0100 Subject: [flashrom] [PATCH] Create a directory for documentation files In-Reply-To: <4EC04591.5060403@gmx.net> References: <4E74A6C1.2090208@gmx.net> <1316305864-19614-1-git-send-email-stefan.tauner@student.tuwien.ac.at> <4EC04591.5060403@gmx.net> Message-ID: <201111132304.pADN4Lw6032510@mail2.student.tuwien.ac.at> On Sun, 13 Nov 2011 23:32:49 +0100 Carl-Daniel Hailfinger wrote: > Am 18.09.2011 02:31 schrieb Stefan Tauner: > > Move the serprog specification there and document a few things we could not > > figure out on intel platforms yet. > > > > Signed-off-by: Stefan Tauner > > Acked-by: Carl-Daniel Hailfinger > thx, r1465 -- Kind regards/Mit freundlichen Gr??en, Stefan Tauner From c-d.hailfinger.devel.2006 at gmx.net Mon Nov 14 01:24:38 2011 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Mon, 14 Nov 2011 01:24:38 +0100 Subject: [flashrom] [PATCH] Clean up error code definitions Message-ID: <4EC05FC6.7080505@gmx.net> This is split off the bus pirate buffer management revamp patch where it didn't really belong. Thanks to Stefan Tauner for the suggestion. Signed-off-by: Carl-Daniel Hailfinger Index: flashrom-errorcodes/flash.h =================================================================== --- flashrom-errorcodes/flash.h (Revision 1463) +++ flashrom-errorcodes/flash.h (Arbeitskopie) @@ -33,10 +33,18 @@ #undef max #endif +/* Error code list, specific errors first, generic errors second. */ +/* Out of memory */ +#define ERROR_OOM -100 +/* Timeout */ +#define ERROR_TIMEOUT -101 +/* Something happened that shouldn't happen, but we can go on. */ +#define ERROR_NONFATAL -110 +/* Something happened that shouldn't happen, we'll abort. */ +#define ERROR_FATAL -111 +/* For functions which can only return pointers */ #define ERROR_PTR ((void*)-1) -/* Error codes */ -#define TIMEOUT_ERROR -101 typedef unsigned long chipaddr; @@ -224,12 +232,6 @@ #define OK 0 #define NT 1 /* Not tested */ -/* Something happened that shouldn't happen, but we can go on. */ -#define ERROR_NONFATAL 0x100 - -/* Something happened that shouldn't happen, we'll abort. */ -#define ERROR_FATAL -0xee - /* cli_output.c */ /* Let gcc and clang check for correct printf-style format strings. */ int print(int type, const char *fmt, ...) __attribute__((format(printf, 2, 3))); Index: flashrom-errorcodes/spi25.c =================================================================== --- flashrom-errorcodes/spi25.c (Revision 1463) +++ flashrom-errorcodes/spi25.c (Arbeitskopie) @@ -769,7 +769,7 @@ while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) { if (++i > 490) { msg_cerr("Error: WIP bit after WRSR never cleared\n"); - return TIMEOUT_ERROR; + return ERROR_TIMEOUT; } programmer_delay(10 * 1000); } @@ -817,7 +817,7 @@ while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) { if (++i > 490) { msg_cerr("Error: WIP bit after WRSR never cleared\n"); - return TIMEOUT_ERROR; + return ERROR_TIMEOUT; } programmer_delay(10 * 1000); } -- http://www.hailfinger.org/ From stefan.tauner at student.tuwien.ac.at Mon Nov 14 08:54:47 2011 From: stefan.tauner at student.tuwien.ac.at (Stefan Tauner) Date: Mon, 14 Nov 2011 08:54:47 +0100 Subject: [flashrom] [PATCH] Clean up error code definitions In-Reply-To: <4EC05FC6.7080505@gmx.net> References: <4EC05FC6.7080505@gmx.net> Message-ID: <201111140754.pAE7shQu029892@mail2.student.tuwien.ac.at> On Mon, 14 Nov 2011 01:24:38 +0100 Carl-Daniel Hailfinger wrote: > This is split off the bus pirate buffer management revamp patch where it > didn't really belong. can we please also integrate the ones from ich_descriptors.h (and maybe others)? including the value indicating success would be nice too imho. i am willing to help with this if you tell me how... -- Kind regards/Mit freundlichen Gr??en, Stefan Tauner From stefan.tauner at student.tuwien.ac.at Mon Nov 14 09:02:32 2011 From: stefan.tauner at student.tuwien.ac.at (Stefan Tauner) Date: Mon, 14 Nov 2011 09:02:32 +0100 Subject: [flashrom] [PATCH] Clean up error code definitions In-Reply-To: <201111140754.pAE7shQu029892@mail2.student.tuwien.ac.at> References: <4EC05FC6.7080505@gmx.net> <201111140754.pAE7shQu029892@mail2.student.tuwien.ac.at> Message-ID: <201111140802.pAE82SOa004311@mail2.student.tuwien.ac.at> On Mon, 14 Nov 2011 08:54:47 +0100 Stefan Tauner wrote: > On Mon, 14 Nov 2011 01:24:38 +0100 > Carl-Daniel Hailfinger wrote: > > > This is split off the bus pirate buffer management revamp patch where it > > didn't really belong. > > can we please also integrate the ones from ich_descriptors.h (and > maybe others*)? including the value indicating success would be nice too > imho. i am willing to help with this if you tell me how... > SPI_GENERIC_ERROR etc. from spi.h shows up on my radar... and of course most of the exit(1) calls should be reviewed and changed after this is merged. serprog.c i am looking at you! -- Kind regards/Mit freundlichen Gr??en, Stefan Tauner From mugendai42 at gmail.com Mon Nov 14 09:17:57 2011 From: mugendai42 at gmail.com (Mugendai) Date: Mon, 14 Nov 2011 01:17:57 -0700 Subject: [flashrom] ASUS P4GV-LA (Guppy) (Resend; fixing link error) Message-ID: I accidentally mislinked for the superiotool in the last e-mail. Sorry about that. lspci: http://paste.flashrom.org/view.php?id=910 superiotool: http://paste.flashrom.org/view.php?id=911 flashrom: http://paste.flashrom.org/view.php?id=912 readout.rom: http://paste.flashrom.org/view.php?id=913 This is on the latest git revision. I am unable to erase the flash chip. Here is the error (with -V) outputted when I try to: http://paste.flashrom.org/view.php?id=909 This is from a hot flashing operation in order to attempt to recover from a bad BIOS update for another computer; the original chip was PMC Pm49FL004. The SST49LF004A/B was from a FIC K8MC51G mainboard. From mugendai42 at gmail.com Mon Nov 14 09:07:08 2011 From: mugendai42 at gmail.com (Mugendai) Date: Mon, 14 Nov 2011 01:07:08 -0700 Subject: [flashrom] ASUS P4GV-LA (Guppy) Message-ID: lspci: http://paste.flashrom.org/view.php?id=910 superiotool: http://paste.flashrom.org/view.php?id=912 flashrom: http://paste.flashrom.org/view.php?id=912 readout.rom: http://paste.flashrom.org/view.php?id=913 This is on the latest git revision. I am unable to erase the flash chip. Here is the error (with -V) outputted when I try to: http://paste.flashrom.org/view.php?id=909 This is from a hot flashing operation in order to attempt to recover from a bad BIOS update for another computer; the original chip was PMC Pm49FL004. The SST49LF004A/B was from a FIC K8MC51G mainboard. From c-d.hailfinger.devel.2006 at gmx.net Mon Nov 14 13:22:33 2011 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Mon, 14 Nov 2011 13:22:33 +0100 Subject: [flashrom] [PATCH] Clean up error code definitions In-Reply-To: <201111140802.pAE82SOa004311@mail2.student.tuwien.ac.at> References: <4EC05FC6.7080505@gmx.net> <201111140754.pAE7shQu029892@mail2.student.tuwien.ac.at> <201111140802.pAE82SOa004311@mail2.student.tuwien.ac.at> Message-ID: <4EC10809.5010109@gmx.net> Am 14.11.2011 09:02 schrieb Stefan Tauner: > On Mon, 14 Nov 2011 08:54:47 +0100 > Stefan Tauner wrote: > >> On Mon, 14 Nov 2011 01:24:38 +0100 >> Carl-Daniel Hailfinger wrote: >> >>> This is split off the bus pirate buffer management revamp patch where it >>> didn't really belong. >> can we please also integrate the ones from ich_descriptors.h (and >> maybe others*)? including the value indicating success would be nice too >> imho. i am willing to help with this if you tell me how... #define RET_OK 0 > SPI_GENERIC_ERROR etc. from spi.h shows up on my radar... and of course > most of the exit(1) calls should be reviewed and changed after this is > merged. serprog.c i am looking at you! Heh. serprog.c is already a bit better since my last programmer registration patch, but it still needs work, as do other places in the code. Here are the error codes I found, partially renamed. This is not for merge, we first have to get the names right. Regards, Carl-Daniel Signed-off-by: Carl-Daniel Hailfinger Index: flashrom-errorcodes/flash.h =================================================================== --- flashrom-errorcodes/flash.h (Revision 1463) +++ flashrom-errorcodes/flash.h (Arbeitskopie) @@ -33,10 +33,29 @@ #undef max #endif +/* Error code list, specific errors first, generic errors second. */ +#define ERROR_GENERIC -1 +#define SPI_INVALID_OPCODE -2 +#define SPI_INVALID_ADDRESS -3 +#define SPI_INVALID_LENGTH -4 +#define ERROR_FLASHROM_BUG -5 +#define ERROR_PROGRAMMER -6 +#define ICH_RET_OK 0 +#define ICH_RET_ERR -1 +#define ICH_RET_WARN -2 +#define ICH_RET_PARAM -3 +#define ICH_RET_OOB -4 +/* Out of memory */ +#define ERROR_OOM -100 +/* Timeout */ +#define ERROR_TIMEOUT -101 +/* Something happened that shouldn't happen, but we can go on. */ +#define ERROR_NONFATAL -110 +/* Something happened that shouldn't happen, we'll abort. */ +#define ERROR_FATAL -111 +/* For functions which can only return pointers */ #define ERROR_PTR ((void*)-1) -/* Error codes */ -#define TIMEOUT_ERROR -101 typedef unsigned long chipaddr; @@ -224,12 +243,6 @@ #define OK 0 #define NT 1 /* Not tested */ -/* Something happened that shouldn't happen, but we can go on. */ -#define ERROR_NONFATAL 0x100 - -/* Something happened that shouldn't happen, we'll abort. */ -#define ERROR_FATAL -0xee - /* cli_output.c */ /* Let gcc and clang check for correct printf-style format strings. */ int print(int type, const char *fmt, ...) __attribute__((format(printf, 2, 3))); Index: flashrom-errorcodes/spi25.c =================================================================== --- flashrom-errorcodes/spi25.c (Revision 1463) +++ flashrom-errorcodes/spi25.c (Arbeitskopie) @@ -769,7 +769,7 @@ while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) { if (++i > 490) { msg_cerr("Error: WIP bit after WRSR never cleared\n"); - return TIMEOUT_ERROR; + return ERROR_TIMEOUT; } programmer_delay(10 * 1000); } @@ -817,7 +817,7 @@ while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) { if (++i > 490) { msg_cerr("Error: WIP bit after WRSR never cleared\n"); - return TIMEOUT_ERROR; + return ERROR_TIMEOUT; } programmer_delay(10 * 1000); } @@ -1128,7 +1128,7 @@ msg_cerr("%s: start address not even! Please report a bug at " "flashrom at flashrom.org\n", __func__); if (spi_chip_write_1(flash, buf, start, start % 2)) - return SPI_GENERIC_ERROR; + return ERROR_GENERIC; pos += start % 2; cmds[1].writearr = (const unsigned char[]){ JEDEC_AAI_WORD_PROGRAM, @@ -1139,14 +1139,14 @@ buf[pos - start + 1] }; /* Do not return an error for now. */ - //return SPI_GENERIC_ERROR; + //return ERROR_GENERIC; } /* The data sheet requires total AAI write length to be even. */ if (len % 2) { msg_cerr("%s: total write length not even! Please report a " "bug at flashrom at flashrom.org\n", __func__); /* Do not return an error for now. */ - //return SPI_GENERIC_ERROR; + //return ERROR_GENERIC; } @@ -1182,7 +1182,7 @@ /* Write remaining byte (if any). */ if (pos < start + len) { if (spi_chip_write_1(flash, buf + pos - start, pos, pos % 2)) - return SPI_GENERIC_ERROR; + return ERROR_GENERIC; pos += pos % 2; } Index: flashrom-errorcodes/buspirate_spi.c =================================================================== --- flashrom-errorcodes/buspirate_spi.c (Revision 1463) +++ flashrom-errorcodes/buspirate_spi.c (Arbeitskopie) @@ -323,22 +323,22 @@ if (ret) { msg_perr("Bus Pirate communication error!\n"); - return SPI_GENERIC_ERROR; + return ERROR_GENERIC; } if (buf[0] != 0x01) { msg_perr("Protocol error while lowering CS#!\n"); - return SPI_GENERIC_ERROR; + return ERROR_GENERIC; } if (buf[1] != 0x01) { msg_perr("Protocol error while reading/writing SPI!\n"); - return SPI_GENERIC_ERROR; + return ERROR_GENERIC; } if (buf[i - 1] != 0x01) { msg_perr("Protocol error while raising CS#!\n"); - return SPI_GENERIC_ERROR; + return ERROR_GENERIC; } /* Skip CS#, length, writearr. */ Index: flashrom-errorcodes/ft2232_spi.c =================================================================== --- flashrom-errorcodes/ft2232_spi.c (Revision 1463) +++ flashrom-errorcodes/ft2232_spi.c (Arbeitskopie) @@ -363,7 +363,7 @@ if (!buf) { msg_perr("Out of memory!\n"); /* TODO: What to do with buf? */ - return SPI_GENERIC_ERROR; + return ERROR_GENERIC; } oldbufsize = bufsize; } Index: flashrom-errorcodes/spi.h =================================================================== --- flashrom-errorcodes/spi.h (Revision 1463) +++ flashrom-errorcodes/spi.h (Arbeitskopie) @@ -118,12 +118,4 @@ #define JEDEC_AAI_WORD_PROGRAM_CONT_OUTSIZE 0x03 #define JEDEC_AAI_WORD_PROGRAM_INSIZE 0x00 -/* Error codes */ -#define SPI_GENERIC_ERROR -1 -#define SPI_INVALID_OPCODE -2 -#define SPI_INVALID_ADDRESS -3 -#define SPI_INVALID_LENGTH -4 -#define SPI_FLASHROM_BUG -5 -#define SPI_PROGRAMMER_ERROR -6 - #endif /* !__SPI_H__ */ Index: flashrom-errorcodes/sb600spi.c =================================================================== --- flashrom-errorcodes/sb600spi.c (Revision 1463) +++ flashrom-errorcodes/sb600spi.c (Arbeitskopie) @@ -141,7 +141,7 @@ * the FIFO pointer to the first byte we want to send. */ if (reset_compare_internal_fifo_pointer(writecnt)) - return SPI_PROGRAMMER_ERROR; + return ERROR_PROGRAMMER; msg_pspew("Executing: \n"); execute_command(); @@ -158,7 +158,7 @@ * Usually, the chip will respond with 0x00 or 0xff. */ if (reset_compare_internal_fifo_pointer(writecnt + readcnt)) - return SPI_PROGRAMMER_ERROR; + return ERROR_PROGRAMMER; /* Skip the bytes we sent. */ msg_pspew("Skipping: "); @@ -168,7 +168,7 @@ } msg_pspew("\n"); if (compare_internal_fifo_pointer(writecnt)) - return SPI_PROGRAMMER_ERROR; + return ERROR_PROGRAMMER; msg_pspew("Reading: "); for (count = 0; count < readcnt; count++, readarr++) { @@ -177,7 +177,7 @@ } msg_pspew("\n"); if (reset_compare_internal_fifo_pointer(readcnt + writecnt)) - return SPI_PROGRAMMER_ERROR; + return ERROR_PROGRAMMER; if (mmio_readb(sb600_spibar + 1) != readwrite) { msg_perr("Unexpected change in SB600 read/write count!\n"); @@ -185,7 +185,7 @@ "causes random corruption.\nPlease stop all " "applications and drivers and IPMI which access the " "flash chip.\n"); - return SPI_PROGRAMMER_ERROR; + return ERROR_PROGRAMMER; } return 0; Index: flashrom-errorcodes/ich_descriptors.h =================================================================== --- flashrom-errorcodes/ich_descriptors.h (Revision 1463) +++ flashrom-errorcodes/ich_descriptors.h (Arbeitskopie) @@ -26,13 +26,6 @@ #include #include "programmer.h" /* for enum ich_chipset */ -/* FIXME: Replace with generic return codes */ -#define ICH_RET_OK 0 -#define ICH_RET_ERR -1 -#define ICH_RET_WARN -2 -#define ICH_RET_PARAM -3 -#define ICH_RET_OOB -4 - #define ICH9_REG_FDOC 0xB0 /* 32 Bits Flash Descriptor Observability Control */ /* 0-1: reserved */ #define FDOC_FDSI_OFF 2 /* 2-11: Flash Descriptor Section Index */ -- http://www.hailfinger.org/ From gp at high-consulting.de Mon Nov 14 13:04:48 2011 From: gp at high-consulting.de (Gerd Pauli) Date: Mon, 14 Nov 2011 13:04:48 +0100 Subject: [flashrom] flashrom tested on alix2d3 board Message-ID: Hello, i just got the flashrom utility from svn. Development System was voyage-0.8.0 Linux http://linux.voyage.hk/ ( Debian based ) After compiling and reading the bios, i tested writing and it worked. Great Job Guys :-) Here are the information needed. ---------------------------- Hardware: PC Engines Alix.2d3 Board http://pcengines.ch/alix2d3.htm ---------------------------- flashrom -V flashrom v0.9.4-r1465 on Linux 3.0.0-voyage (i586), built with libpci 3.1.7, GCC 4.4.5, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 14 usecs, 160M loops per second, 10 myus = 21 us, 100 myus = 108 us, 1000 myus = 1097 us, 10000 myus = 10101 us, 56 myus = 65 us, OK. Initializing internal programmer No coreboot table found. sh: dmidecode: not found dmidecode execution unsuccessful - continuing without DMI info Found chipset "AMD CS5536" with PCI ID 1022:2080. Enabling flash write... OK. WARNING: unexpected second chipset match: "AMD CS5536" ignoring, please report lspci and board URL to flashrom at flashrom.org with 'CHIPSET: your board name' in the subject line. This programmer supports the following protocols: Non-SPI. Probing for AMD Am29F010A/B, 128 kB: probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F002(N)BB, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F002(N)BT, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F016D, 2048 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F040B, 512 kB: probe_jedec_common: id1 0x03, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F080B, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV001BB, 128 kB: probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV001BT, 128 kB: probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV002BB, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV002BT, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV004BB, 512 kB: probe_jedec_common: id1 0x03, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV004BT, 512 kB: probe_jedec_common: id1 0x03, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV008BB, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV008BT, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV040B, 512 kB: probe_jedec_common: id1 0x03, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV081B, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC A29002B, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC A29002T, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC A29040B, 512 kB: probe_jedec_common: id1 0x03, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC A49LF040A, 512 kB: probe_jedec_common: id1 0x37, id2 0x9d Found AMIC flash chip "A49LF040A" (512 kB, LPC) at physical address 0xfff80000. Probing for Atmel AT29C512, 64 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for Atmel AT29C010A, 128 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for Atmel AT29C020, 256 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for Atmel AT29C040A, 512 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for Atmel AT49BV512, 64 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for Atmel AT49F020, 256 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for Atmel AT49F002(N), 256 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for Atmel AT49F002(N)T, 256 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for Atmel AT49LH002, 256 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Catalyst CAT28F512, 64 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for Bright BM29F040, 512 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for EMST F49B002UA, 256 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for Eon EN29F010, 128 kB: probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Eon EN29F002(A)(N)B, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Eon EN29F002(A)(N)T, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F004BC, 512 kB: probe_jedec_common: id1 0x03, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F004TC, 512 kB: probe_jedec_common: id1 0x03, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F400BC, 512 kB: probe_m29f400bt: id1 0x03, id2 0x00 Probing for Fujitsu MBM29F400TC, 512 kB: probe_m29f400bt: id1 0x03, id2 0x00 Probing for Hyundai HY29F002T, 256 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for Hyundai HY29F002B, 256 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for Hyundai HY29F040A, 512 kB: probe_jedec_common: id1 0x03, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F001BN/BX-B, 128 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for Intel 28F001BN/BX-T, 128 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for Intel 28F002BC/BL/BV/BX-T, 256 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F008S3/S5/SC, 512 kB: probe_82802ab: id1 0x03, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F004B5/BE/BV/BX-B, 512 kB: probe_82802ab: id1 0x03, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F004B5/BE/BV/BX-T, 512 kB: probe_82802ab: id1 0x03, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F400BV/BX/CE/CV-B, 512 kB: probe_82802ab: id1 0x03, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F400BV/BX/CE/CV-T, 512 kB: probe_82802ab: id1 0x03, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0x03, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F001B, 128 kB: probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F001T, 128 kB: probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F002(N)B, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F002(N)T, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F040, 512 kB: probe_jedec_common: id1 0x03, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29LV040, 512 kB: probe_jedec_common: id1 0x03, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for MoselVitelic V29C51000B, 64 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for MoselVitelic V29C51000T, 64 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for MoselVitelic V29C51400B, 512 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for MoselVitelic V29C51400T, 512 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for MoselVitelic V29LC51000, 64 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for MoselVitelic V29LC51001, 128 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for MoselVitelic V29LC51002, 256 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for PMC Pm29F002T, 256 kB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm29F002B, 256 kB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm39LV010, 128 kB: probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm39LV020, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm39LV040, 512 kB: probe_jedec_common: id1 0x03, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for Sharp LH28F008BJT-BTLZ1, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST28SF040A, 512 kB: probe_82802ab: id1 0x03, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST29EE010, 128 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for SST SST29LE010, 128 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for SST SST29EE020A, 256 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for SST SST29LE020, 256 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for SST SST39SF512, 64 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for SST SST39SF010A, 128 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for SST SST39SF020A, 256 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for SST SST39SF040, 512 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for SST SST39VF512, 64 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for SST SST39VF010, 128 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for SST SST39VF020, 256 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for SST SST39VF040, 512 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for SST SST39VF080, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0x03, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF020, 256 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for SST SST49LF020A, 256 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for SST SST49LF040, 512 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for SST SST49LF040B, 512 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for SST SST49LF080A, 1024 kB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF160C, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29F002B, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29F002T/NT, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29F040B, 512 kB: probe_jedec_common: id1 0x03, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29F400BB, 512 kB: probe_m29f400bt: id1 0x03, id2 0x00 Probing for ST M29F400BT, 512 kB: probe_m29f400bt: id1 0x03, id2 0x00 Probing for ST M29W010B, 128 kB: probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29W040B, 512 kB: probe_jedec_common: id1 0x03, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29W512B, 64 kB: probe_jedec_common: id1 0xeb, id2 0x05, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0x03, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0x03, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0x03, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50LPW116, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SyncMOS/MoselVitelic {F,S,V}29C51001B, 128 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for SyncMOS/MoselVitelic {F,S,V}29C51001T, 128 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for SyncMOS/MoselVitelic {F,S,V}29C51002B, 256 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for SyncMOS/MoselVitelic {F,S,V}29C51002T, 256 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for SyncMOS/MoselVitelic {F,S,V}29C51004B, 512 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for SyncMOS/MoselVitelic {F,S,V}29C51004T, 512 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for SyncMOS/MoselVitelic {S,V}29C31004B, 512 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for SyncMOS/MoselVitelic {S,V}29C31004T, 512 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for TI TMS29F002RB, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for TI TMS29F002RT, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W29C010(M)/W29C011A/W29EE011/W29EE012-old, 128 kB: Old Winbond W29* probe method disabled because the probing sequence puts the AMIC A49LF040A in a funky state. Use 'flashrom -c W29C010(M)/W29C011A/W29EE011/W29EE012-old' if you have a board with such a chip. Probing for Winbond W29C010(M)/W29C011A/W29EE011/W29EE012, 128 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for Winbond W29C020(C)/W29C022, 256 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for Winbond W29C040/P, 512 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for Winbond W39L040, 512 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for Winbond W39V040A, 512 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for Winbond W39V040B, 512 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for Winbond W39V040C, 512 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for Winbond W39V080A, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49F002U/N, 256 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for Winbond W49F020, 256 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for Winbond W49V002A, 256 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 0x37, id2 0x9d Found AMIC flash chip "A49LF040A" (512 kB, LPC). === This flash part has status UNTESTED for operations: WRITE The test status of this chip may have been updated in the latest development version of flashrom. If you are running the latest development version, please email a report to flashrom at flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -Vr, -Vw, -VE), and mention which mainboard or programmer you tested. Please mention your board in the subject line. Thanks for your help! No operations were specified. --------------------- flashrom -Vr Reading flash... done. --------------------- flashrom -VE Erasing and writing flash chip... Trying erase function 0... 0x000000-0x00ffff:E, 0x010000-0x01ffff:E, 0x020000-0x02ffff:E, 0x030000-0x03ffff:E, 0x040000-0x04ffff:E, 0x050000-0x05ffff:E, 0x060000-0x06ffff:E, 0x070000-0x07ffff:E Erase/write done. --------------------- flashrom -Vw flashrom v0.9.4-r1465 on Linux 3.0.0-voyage (i586), built with libpci 3.1.7, GCC 4.4.5, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 13 usecs, 160M loops per second, 10 myus = 21 us, 100 myus = 108 us, 1000 myus = 1019 us, 10000 myus = 10214 us, 52 myus = 62 us, OK. Initializing internal programmer No coreboot table found. sh: dmidecode: not found dmidecode execution unsuccessful - continuing without DMI info Found chipset "AMD CS5536" with PCI ID 1022:2080. Enabling flash write... OK. WARNING: unexpected second chipset match: "AMD CS5536" ignoring, please report lspci and board URL to flashrom at flashrom.org with 'CHIPSET: your board name' in the subject line. This programmer supports the following protocols: Non-SPI. Probing for AMD Am29F010A/B, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F002(N)BB, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F002(N)BT, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F016D, 2048 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F040B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F080B, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV001BB, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV001BT, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV002BB, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV002BT, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV004BB, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV004BT, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV008BB, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV008BT, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV040B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV081B, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC A29002B, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC A29002T, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC A29040B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC A49LF040A, 512 kB: probe_jedec_common: id1 0x37, id2 0x9d Found AMIC flash chip "A49LF040A" (512 kB, LPC) at physical address 0xfff80000. Probing for Atmel AT29C512, 64 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for Atmel AT29C010A, 128 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for Atmel AT29C020, 256 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for Atmel AT29C040A, 512 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for Atmel AT49BV512, 64 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for Atmel AT49F020, 256 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for Atmel AT49F002(N), 256 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for Atmel AT49F002(N)T, 256 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for Atmel AT49LH002, 256 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Catalyst CAT28F512, 64 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for Bright BM29F040, 512 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for EMST F49B002UA, 256 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for Eon EN29F010, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Eon EN29F002(A)(N)B, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Eon EN29F002(A)(N)T, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F004BC, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F004TC, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F400BC, 512 kB: probe_m29f400bt: id1 0xff, id2 0xff Probing for Fujitsu MBM29F400TC, 512 kB: probe_m29f400bt: id1 0xff, id2 0xff Probing for Hyundai HY29F002T, 256 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for Hyundai HY29F002B, 256 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for Hyundai HY29F040A, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F001BN/BX-B, 128 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for Intel 28F001BN/BX-T, 128 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for Intel 28F002BC/BL/BV/BX-T, 256 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F008S3/S5/SC, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F004B5/BE/BV/BX-B, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F004B5/BE/BV/BX-T, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F400BV/BX/CE/CV-B, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F400BV/BX/CE/CV-T, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F001B, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F001T, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F002(N)B, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F002(N)T, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F040, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29LV040, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for MoselVitelic V29C51000B, 64 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for MoselVitelic V29C51000T, 64 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for MoselVitelic V29C51400B, 512 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for MoselVitelic V29C51400T, 512 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for MoselVitelic V29LC51000, 64 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for MoselVitelic V29LC51001, 128 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for MoselVitelic V29LC51002, 256 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for PMC Pm29F002T, 256 kB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm29F002B, 256 kB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm39LV010, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm39LV020, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm39LV040, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for Sharp LH28F008BJT-BTLZ1, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST28SF040A, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST29EE010, 128 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for SST SST29LE010, 128 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for SST SST29EE020A, 256 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for SST SST29LE020, 256 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for SST SST39SF512, 64 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for SST SST39SF010A, 128 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for SST SST39SF020A, 256 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for SST SST39SF040, 512 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for SST SST39VF512, 64 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for SST SST39VF010, 128 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for SST SST39VF020, 256 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for SST SST39VF040, 512 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for SST SST39VF080, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF020, 256 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for SST SST49LF020A, 256 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for SST SST49LF040, 512 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for SST SST49LF040B, 512 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for SST SST49LF080A, 1024 kB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF160C, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29F002B, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29F002T/NT, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29F040B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29F400BB, 512 kB: probe_m29f400bt: id1 0xff, id2 0xff Probing for ST M29F400BT, 512 kB: probe_m29f400bt: id1 0xff, id2 0xff Probing for ST M29W010B, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29W040B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29W512B, 64 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50LPW116, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SyncMOS/MoselVitelic {F,S,V}29C51001B, 128 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for SyncMOS/MoselVitelic {F,S,V}29C51001T, 128 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for SyncMOS/MoselVitelic {F,S,V}29C51002B, 256 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for SyncMOS/MoselVitelic {F,S,V}29C51002T, 256 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for SyncMOS/MoselVitelic {F,S,V}29C51004B, 512 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for SyncMOS/MoselVitelic {F,S,V}29C51004T, 512 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for SyncMOS/MoselVitelic {S,V}29C31004B, 512 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for SyncMOS/MoselVitelic {S,V}29C31004T, 512 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for TI TMS29F002RB, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for TI TMS29F002RT, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W29C010(M)/W29C011A/W29EE011/W29EE012-old, 128 kB: Old Winbond W29* probe method disabled because the probing sequence puts the AMIC A49LF040A in a funky state. Use 'flashrom -c W29C010(M)/W29C011A/W29EE011/W29EE012-old' if you have a board with such a chip. Probing for Winbond W29C010(M)/W29C011A/W29EE011/W29EE012, 128 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for Winbond W29C020(C)/W29C022, 256 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for Winbond W29C040/P, 512 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for Winbond W39L040, 512 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for Winbond W39V040A, 512 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for Winbond W39V040B, 512 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for Winbond W39V040C, 512 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for Winbond W39V080A, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49F002U/N, 256 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for Winbond W49F020, 256 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for Winbond W49V002A, 256 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0x37, id2 0x9d Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 0x37, id2 0x9d Found AMIC flash chip "A49LF040A" (512 kB, LPC). === This flash part has status UNTESTED for operations: WRITE The test status of this chip may have been updated in the latest development version of flashrom. If you are running the latest development version, please email a report to flashrom at flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -Vr, -Vw, -VE), and mention which mainboard or programmer you tested. Please mention your board in the subject line. Thanks for your help! Flash image seems to be a legacy BIOS. Disabling coreboot-related checks. Reading old flash chip contents... done. Erasing and writing flash chip... Trying erase function 0... 0x000000-0x00ffff:W, 0x010000-0x01ffff:S, 0x020000-0x02ffff:S, 0x030000-0x03ffff:S, 0x040000-0x04ffff:S, 0x050000-0x05ffff:S, 0x060000-0x06ffff:W, 0x070000-0x07ffff:W Erase/write done. Verifying flash... VERIFIED. --------------------- lspci -nnvvxxx 00:01.0 Host bridge [0600]: Advanced Micro Devices [AMD] CS5536 [Geode companion] Host Bridge [1022:2080] (rev 33) Subsystem: Advanced Micro Devices [AMD] CS5536 [Geode companion] Host Bridge [1022:2080] Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- Region 4: I/O ports at 9d00 [size=128] Region 5: I/O ports at 9c00 [size=64] Kernel driver in use: cs5535-mfd 00: 22 10 90 20 09 00 a0 02 03 00 01 06 08 40 80 00 10: 01 60 00 00 01 61 00 00 01 62 00 00 01 00 00 00 20: 01 9d 00 00 01 9c 00 00 00 00 00 00 22 10 90 20 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:0f.2 IDE interface [0101]: Advanced Micro Devices [AMD] CS5536 [Geode companion] IDE [1022:209a] (rev 01) (prog-if 80 [Master]) Subsystem: Advanced Micro Devices [AMD] CS5536 [Geode companion] IDE [1022:209a] Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- SERR- TAbort- SERR- TAbort- SERR- Author: stefanct Date: Mon Nov 14 14:00:12 2011 New Revision: 1466 URL: http://flashrom.org/trac/flashrom/changeset/1466 Log: board_enable.c: Make it8712f_gpio_set generic This looks suspiciously like intel_ich_gpio_set. Based on that, add board enables for the ASUS P5N-D and P5N-E SLI. This was tested by Guillaume Poirier-Morency on a P5N-D: http://www.flashrom.org/pipermail/flashrom/2011-August/007706.html Signed-off-by: Joshua Roys Small changes were also contributed and Signed-off-by: Stefan Tauner Acked-by: Stefan Tauner Modified: trunk/board_enable.c trunk/print.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Mon Nov 14 00:03:30 2011 (r1465) +++ trunk/board_enable.c Mon Nov 14 14:00:12 2011 (r1466) @@ -1917,54 +1917,90 @@ } /* - * General routine for raising/dropping GPIO lines on the ITE IT8712F. - * There is only some limited checking on the port numbers. + * General routine for raising/dropping GPIO lines on the ITE IT87xx. */ -static int it8712f_gpio_set(unsigned int line, int raise) +static int it87_gpio_set(unsigned int gpio, int raise) { + int allowed, sio; unsigned int port; - uint16_t id, base; + uint16_t base, sioport; uint8_t tmp; - port = line / 10; - port--; - line %= 10; - - /* Check line */ - if ((port > 4) || /* also catches unsigned -1 */ - ((port < 4) && (line > 7)) || ((port == 4) && (line > 5))) { - msg_perr("\nERROR: Unsupported IT8712F GPIO line %02d.\n", line); + /* IT87 GPIO configuration table */ + static const struct it87cfg { + uint16_t id; + uint8_t base_reg; + uint32_t bank0; + uint32_t bank1; + uint32_t bank2; + } it87_gpio_table[] = { + {0x8712, 0x62, 0xCFF3FC00, 0x00FCFF3F, 0}, + {0x8718, 0x62, 0xCFF37C00, 0xF3FCDF3F, 0x0000000F}, + {0, 0, 0, 0, 0} /* end marker */ + }; + const struct it87cfg *cfg = NULL; + + /* Find the Super I/O in the probed list */ + for (sio = 0; sio < superio_count; sio++) { + int i; + if (superios[sio].vendor != SUPERIO_VENDOR_ITE) + continue; + + /* Is this device in our list? */ + for (i = 0; it87_gpio_table[i].id; i++) + if (superios[sio].model == it87_gpio_table[i].id) { + cfg = &it87_gpio_table[i]; + goto found; + } + } + + if (cfg == NULL) { + msg_perr("\nERROR: No IT87 Super I/O GPIO configuration " + "found.\n"); return -1; } - /* Find the IT8712F. */ - enter_conf_mode_ite(0x2E); - id = (sio_read(0x2E, 0x20) << 8) | sio_read(0x2E, 0x21); - exit_conf_mode_ite(0x2E); +found: + /* Check whether the gpio is allowed. */ + if (gpio < 32) + allowed = (cfg->bank0 >> gpio) & 0x01; + else if (gpio < 64) + allowed = (cfg->bank1 >> (gpio - 32)) & 0x01; + else if (gpio < 96) + allowed = (cfg->bank2 >> (gpio - 64)) & 0x01; + else + allowed = 0; - if (id != 0x8712) { - msg_perr("\nERROR: IT8712F Super I/O not found.\n"); + if (!allowed) { + msg_perr("\nERROR: IT%02X does not allow setting GPIO%02u.\n", + cfg->id, gpio); return -1; } - /* Get the GPIO base */ - enter_conf_mode_ite(0x2E); - sio_write(0x2E, 0x07, 0x07); - base = (sio_read(0x2E, 0x62) << 8) | sio_read(0x2E, 0x63); - exit_conf_mode_ite(0x2E); + /* Read the Simple I/O Base Address Register */ + sioport = superios[sio].port; + enter_conf_mode_ite(sioport); + sio_write(sioport, 0x07, 0x07); + base = (sio_read(sioport, cfg->base_reg) << 8) | + sio_read(sioport, cfg->base_reg + 1); + exit_conf_mode_ite(sioport); if (!base) { - msg_perr("\nERROR: Failed to read IT8712F Super I/O GPIO" - " Base.\n"); + msg_perr("\nERROR: Failed to read IT87 Super I/O GPIO Base.\n"); return -1; } - /* Set GPIO. */ + msg_pdbg("Using IT87 GPIO base 0x%04x\n", base); + + port = gpio / 10 - 1; + gpio %= 10; + + /* set GPIO. */ tmp = INB(base + port); if (raise) - tmp |= 1 << line; + tmp |= 1 << gpio; else - tmp &= ~(1 << line); + tmp &= ~(1 << gpio); OUTB(tmp, base + port); return 0; @@ -1975,9 +2011,19 @@ * - ASUS A7V600-X: VIA KT600 + VT8237 + IT8712F * - ASUS A7V8X-X: VIA KT400 + VT8235 + IT8712F */ -static int it8712f_gpio3_1_raise(void) +static int it8712f_gpio31_raise(void) +{ + return it87_gpio_set(32, 1); +} + +/* + * Suited for: + * - ASUS P5N-D: NVIDIA MCP51 + IT8718F + * - ASUS P5N-E SLI: NVIDIA MCP51 + IT8718F + */ +static int it8718f_gpio63_raise(void) { - return it8712f_gpio_set(32, 1); + return it87_gpio_set(63, 1); } #endif @@ -2047,11 +2093,11 @@ {0x1039, 0x0741, 0x1849, 0x0741, 0x1039, 0x5513, 0x1849, 0x5513, "^K7S41GX$", NULL, NULL, P3, "ASRock", "K7S41GX", 0, OK, w836xx_memw_enable_2e}, {0x8086, 0x24D4, 0x1849, 0x24D0, 0x8086, 0x24D5, 0x1849, 0x9739, NULL, NULL, NULL, P3, "ASRock", "P4i65GV", 0, OK, intel_ich_gpio23_raise}, {0x8086, 0x2570, 0x1849, 0x2570, 0x8086, 0x24d3, 0x1849, 0x24d0, NULL, NULL, NULL, P3, "ASRock", "775i65G", 0, OK, intel_ich_gpio23_raise}, - {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3065, 0x1043, 0x80ED, NULL, NULL, NULL, P3, "ASUS", "A7V600-X", 0, OK, it8712f_gpio3_1_raise}, + {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3065, 0x1043, 0x80ED, NULL, NULL, NULL, P3, "ASUS", "A7V600-X", 0, OK, it8712f_gpio31_raise}, {0x1106, 0x3177, 0x1043, 0x80A1, 0x1106, 0x3205, 0x1043, 0x8118, NULL, NULL, NULL, P3, "ASUS", "A7V8X-MX SE", 0, OK, w836xx_memw_enable_2e}, {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x808C, NULL, NULL, NULL, P3, "ASUS", "A7V8X", 0, OK, it8703f_gpio51_raise}, {0x1106, 0x3099, 0x1043, 0x807F, 0x1106, 0x3147, 0x1043, 0x808C, NULL, NULL, NULL, P3, "ASUS", "A7V333", 0, OK, it8703f_gpio51_raise}, - {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x80A1, NULL, NULL, NULL, P3, "ASUS", "A7V8X-X", 0, OK, it8712f_gpio3_1_raise}, + {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x80A1, NULL, NULL, NULL, P3, "ASUS", "A7V8X-X", 0, OK, it8712f_gpio31_raise}, {0x1002, 0x4372, 0x103c, 0x2a26, 0x1002, 0x4377, 0x103c, 0x2a26, NULL, NULL, NULL, P3, "ASUS", "A8AE-LE", 0, OK, amd_sbxxx_gpio9_raise}, {0x8086, 0x27A0, 0x1043, 0x1287, 0x8086, 0x27DF, 0x1043, 0x1287, "^A8J", NULL, NULL, P3, "ASUS", "A8Jm", 0, NT, intel_ich_gpio34_raise}, {0x10DE, 0x0260, 0x103C, 0x2A34, 0x10DE, 0x0264, 0x103C, 0x2A34, "NODUSM3", NULL, NULL, P3, "ASUS", "A8M2N-LA (NodusM3-GL8E)", 0, OK, nvidia_mcp_gpio0_raise}, @@ -2084,6 +2130,8 @@ {0x8086, 0x27b8, 0x1043, 0x2a22, 0x8086, 0x2770, 0x1043, 0x2a22, "^P5LP-LE$", NULL, NULL, P3, "ASUS", "P5LP-LE (Epson OEM)", 0, OK, intel_ich_gpio34_raise}, {0x8086, 0x27da, 0x1043, 0x8179, 0x8086, 0x27b8, 0x1043, 0x8179, "^P5LD2$", NULL, NULL, P3, "ASUS", "P5LD2", 0, NT, intel_ich_gpio16_raise}, {0x10DE, 0x0030, 0x1043, 0x818a, 0x8086, 0x100E, 0x1043, 0x80EE, NULL, NULL, NULL, P3, "ASUS", "P5ND2-SLI Deluxe", 0, OK, nvidia_mcp_gpio10_raise}, + {0x10DE, 0x0260, 0x1043, 0x81BC, 0x10DE, 0x026C, 0x1043, 0x829E, "^P5N-D$", NULL, NULL, P3, "ASUS", "P5N-D", 0, OK, it8718f_gpio63_raise}, + {0x10DE, 0x0260, 0x1043, 0x81BC, 0x10DE, 0x026C, 0x1043, 0x8249, "^P5N-E SLI$",NULL, NULL, P3, "ASUS", "P5N-E SLI", 0, NT, it8718f_gpio63_raise}, {0x8086, 0x24dd, 0x1043, 0x80a6, 0x8086, 0x2570, 0x1043, 0x8157, NULL, NULL, NULL, P3, "ASUS", "P5PE-VM", 0, OK, intel_ich_gpio21_raise}, {0x10b7, 0x9055, 0x1028, 0x0082, 0x8086, 0x7190, 0, 0, NULL, NULL, NULL, P3, "Dell", "OptiPlex GX1", 0, OK, intel_piix4_gpo30_lower}, {0x8086, 0x3590, 0x1028, 0x016c, 0x1000, 0x0030, 0x1028, 0x016c, NULL, NULL, NULL, P3, "Dell", "PowerEdge 1850", 0, OK, intel_ich_gpio23_raise}, Modified: trunk/print.c ============================================================================== --- trunk/print.c Mon Nov 14 00:03:30 2011 (r1465) +++ trunk/print.c Mon Nov 14 14:00:12 2011 (r1466) @@ -661,6 +661,8 @@ B("ASUS", "P5LP-LE (Epson OEM)", 1, NULL, "This is an OEM board from Epson (e.g. Endeavor MT7700)."), B("ASUS", "P5LP-LE", 0, NULL, "This designation is used for OEM boards from HP, Epson and maybe others. The HP names vary and not all of them have been tested yet. Please report any success or failure, thanks."), B("ASUS", "P5N-E SLI", 0, "http://www.asus.com/product.aspx?P_ID=KyHOsOKWujC2QguJ", "Needs a board enable (http://patchwork.coreboot.org/patch/3298/)."), + B("ASUS", "P5N-D", 1, "http://www.asus.com/Motherboards/Intel_Socket_775/P5ND/", NULL), + B("ASUS", "P5N-E SLI", 0, "http://www.asus.com/Motherboards/Intel_Socket_775/P5NE_SLI/", "Untested board enable."), B("ASUS", "P5N32-E SLI", 1, "http://www.asus.com/product.aspx?P_ID=vBZLIBtPzYB2bLcb", NULL), B("ASUS", "P5ND2-SLI Deluxe", 1, "http://www.asus.com/product.aspx?P_ID=WY7XroDuUImVbgp5", NULL), B("ASUS", "P5PE-VM", 1, "http://www.asus.com/product.aspx?P_ID=k3h0ZFVu9Lo1dUvk", NULL), From stefan.tauner at student.tuwien.ac.at Mon Nov 14 14:01:54 2011 From: stefan.tauner at student.tuwien.ac.at (Stefan Tauner) Date: Mon, 14 Nov 2011 14:01:54 +0100 Subject: [flashrom] [PATCH] board_enable: Make it8712f_gpio_set generic In-Reply-To: <1314102936-879-1-git-send-email-stefan.tauner@student.tuwien.ac.at> References: <4E5291ED.60301@gmail.com> <1314102936-879-1-git-send-email-stefan.tauner@student.tuwien.ac.at> Message-ID: <201111141301.pAED1oP6015372@mail2.student.tuwien.ac.at> On Tue, 23 Aug 2011 14:35:36 +0200 Stefan Tauner wrote: > This looks suspiciously like intel_ich_gpio_set. > > Based on that, add board enables for the ASUS P5N-D and P5N-E SLI. > This was tested by Guillaume Poirier-Morency on a P5N-D: > http://www.flashrom.org/pipermail/flashrom/2011-August/007706.html > > Signed-off-by: Joshua Roys > Acked-by: Stefan Tauner > --- > i have made a few changes: > - renamed functions to our usual scheme > - marked the P5E (board enable) as not tested > - use a pointer to the config entry to access it instead of its index > > the latter together with the goto makes the execution flow more obvious imho. > > if anyone asks this is of course also > Signed-off-by: Stefan Tauner > but i don't deserve it imo. as discussed on IRC i have committed this in r1466 with a few further modifications (better and earlier input validation). -- Kind regards/Mit freundlichen Gr??en, Stefan Tauner From stefan.tauner at student.tuwien.ac.at Mon Nov 14 20:23:18 2011 From: stefan.tauner at student.tuwien.ac.at (Stefan Tauner) Date: Mon, 14 Nov 2011 20:23:18 +0100 Subject: [flashrom] [PATCH] Add board enable for ASUS P4GV-LA (Guppy) In-Reply-To: References: Message-ID: <1321298598-13925-1-git-send-email-stefan.tauner@student.tuwien.ac.at> The Reverse engineering was done by Joshua. The actual patch was fabricated by Stefan. Signed-off-by: Joshua Roys Signed-off-by: Stefan Tauner --- board_enable.c | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/board_enable.c b/board_enable.c index 1173b9c..7ef3db4 100644 --- a/board_enable.c +++ b/board_enable.c @@ -2111,6 +2111,7 @@ const struct board_match board_matches[] = { {0x8086, 0x1A30, 0x1043, 0x8025, 0x8086, 0x244B, 0x104D, 0x80F0, NULL, NULL, NULL, P3, "ASUS", "P4B266-LM", 0, OK, intel_ich_gpio21_raise}, {0x8086, 0x1a30, 0x1043, 0x8070, 0x8086, 0x244b, 0x1043, 0x8028, NULL, NULL, NULL, P3, "ASUS", "P4B266", 0, OK, intel_ich_gpio22_raise}, {0x8086, 0x1A30, 0x1043, 0x8088, 0x8086, 0x24C3, 0x1043, 0x8089, NULL, NULL, NULL, P3, "ASUS", "P4B533-E", 0, NT, intel_ich_gpio22_raise}, + {0x8086, 0x2560, 0x103C, 0x2A00, 0x8086, 0x24C3, 0x103C, 0x2A01, "^Guppy", NULL, NULL, P3, "ASUS", "P4GV-LA (Guppy)", 0, OK, intel_ich_gpio21_raise}, {0x8086, 0x24D3, 0x1043, 0x80A6, 0x8086, 0x2578, 0x1043, 0x80F6, NULL, NULL, NULL, P3, "ASUS", "P4C800-E Deluxe", 0, OK, intel_ich_gpio21_raise}, {0x8086, 0x2570, 0x1043, 0x80F2, 0x8086, 0x24D5, 0x1043, 0x80F3, NULL, NULL, NULL, P3, "ASUS", "P4P800", 0, NT, intel_ich_gpio21_raise}, {0x8086, 0x2570, 0x1043, 0x80F2, 0x8086, 0x24D3, 0x1043, 0x80A6, "^P4P800-E$", NULL, NULL, P3, "ASUS", "P4P800-E Deluxe", 0, OK, intel_ich_gpio21_raise}, -- 1.7.1 From c-d.hailfinger.devel.2006 at gmx.net Mon Nov 14 23:32:42 2011 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Mon, 14 Nov 2011 23:32:42 +0100 Subject: [flashrom] [PATCH] Add board enable for ASUS P4GV-LA (Guppy) In-Reply-To: <1321298598-13925-1-git-send-email-stefan.tauner@student.tuwien.ac.at> References: <1321298598-13925-1-git-send-email-stefan.tauner@student.tuwien.ac.at> Message-ID: <4EC1970A.6020608@gmx.net> Am 14.11.2011 20:23 schrieb Stefan Tauner: > The Reverse engineering was done by Joshua. The actual patch was > fabricated by Stefan. > Signed-off-by: Joshua Roys > Signed-off-by: Stefan Tauner Acked-by: Carl-Daniel Hailfinger Regards, Carl-Daniel -- http://www.hailfinger.org/ From c-d.hailfinger.devel.2006 at gmx.net Tue Nov 15 08:54:23 2011 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Tue, 15 Nov 2011 08:54:23 +0100 Subject: [flashrom] [PATCH] Bus Pirate buffer management revamp In-Reply-To: <201108111500.p7BF0isF015924@mail2.student.tuwien.ac.at> References: <201108111500.p7BF0isF015924@mail2.student.tuwien.ac.at> Message-ID: <4EC21AAF.5060302@gmx.net> Am 11.08.2011 17:00 schrieb Stefan Tauner: >> Use a separate function for managing the Bus Pirate command/data buffer. >> Open-coding the buffer management was the first step, now the goal is to >> make it readable. >> >> The buffer management of the Bus Pirate driver has been revamped >> to use grow-only buffers with a reasonable initial default size >> so realloc() will not have to be called in normal operation. >> A side effect is the ability to switch to a static buffer without >> major hassle. >> Handle OOM gracefully. >> >> Signed-off-by: Carl-Daniel Hailfinger New version, significant changes to fix all memleaks and to address all review comments. Stefan, I know you already acked the earlier version subject to a few changes, but this version probably needs a new review. Sorry about that. If you want a diff between the old and new version, tell me and I'll send it. The shutdown function still has its own static buffer to allow shutdown even if memory is tight, but AFAICS that should not be needed because the buffer can never be too small for shutdown once init is complete. If you agree with that assessment, I could change the shutdown function to use the common buffer as well. Signed-off-by: Carl-Daniel Hailfinger Index: flashrom-buspirate_buffermanagement/flash.h =================================================================== --- flashrom-buspirate_buffermanagement/flash.h (Revision 1464) +++ flashrom-buspirate_buffermanagement/flash.h (Arbeitskopie) @@ -36,6 +36,7 @@ #define ERROR_PTR ((void*)-1) /* Error codes */ +#define ERROR_OOM -100 #define TIMEOUT_ERROR -101 typedef unsigned long chipaddr; Index: flashrom-buspirate_buffermanagement/buspirate_spi.c =================================================================== --- flashrom-buspirate_buffermanagement/buspirate_spi.c (Revision 1464) +++ flashrom-buspirate_buffermanagement/buspirate_spi.c (Arbeitskopie) @@ -39,6 +39,7 @@ { /* 115200bps, 8 databits, no parity, 1 stopbit */ sp_fd = sp_openserport(dev, 115200); + /* FIXME: Error checking */ return 0; } #else @@ -49,6 +50,29 @@ #define sp_flush_incoming(...) 0 #endif +static unsigned char *bp_commbuf = NULL; +static int bp_commbufsize = 0; + +static int buspirate_commbuf_grow(int bufsize) +{ + unsigned char *tmpbuf; + + /* Never shrink. realloc() calls are expensive. */ + if (bufsize <= bp_commbufsize) + return 0; + + tmpbuf = realloc(bp_commbuf, bufsize); + if (!tmpbuf) { + /* Keep the existing buffer because memory is already tight. */ + msg_perr("Out of memory!\n"); + return ERROR_OOM; + } + + bp_commbuf = tmpbuf; + bp_commbufsize = bufsize; + return 0; +} + static int buspirate_sendrecv(unsigned char *buf, unsigned int writecnt, unsigned int readcnt) { @@ -114,41 +138,48 @@ static int buspirate_spi_shutdown(void *data) { unsigned char buf[5]; - int ret = 0; + int ret = 0, ret2 = 0; /* Exit raw SPI mode (enter raw bitbang mode) */ buf[0] = 0x00; ret = buspirate_sendrecv(buf, 1, 5); if (ret) - return ret; + goto out_shutdown; if (memcmp(buf, "BBIO", 4)) { msg_perr("Entering raw bitbang mode failed!\n"); - return 1; + ret = 1; + goto out_shutdown; } msg_pdbg("Raw bitbang mode version %c\n", buf[4]); if (buf[4] != '1') { msg_perr("Can't handle raw bitbang mode version %c!\n", buf[4]); - return 1; + ret = 1; + goto out_shutdown; } /* Reset Bus Pirate (return to user terminal) */ buf[0] = 0x0f; ret = buspirate_sendrecv(buf, 1, 0); - if (ret) - return ret; +out_shutdown: /* Shut down serial port communication */ - ret = serialport_shutdown(NULL); + ret2 = serialport_shutdown(NULL); + /* Keep the oldest error, it is probably the best indicator. */ + if (ret2 && !ret) + ret = ret2; + bp_commbufsize = 0; + free(bp_commbuf); + bp_commbuf = NULL; if (ret) - return ret; - msg_pdbg("Bus Pirate shutdown completed.\n"); + msg_pdbg("Bus Pirate shutdown failed.\n"); + else + msg_pdbg("Bus Pirate shutdown completed.\n"); - return 0; + return ret; } int buspirate_spi_init(void) { - unsigned char buf[512]; char *dev = NULL; char *speed = NULL; int spispeed = 0x7; @@ -178,10 +209,24 @@ /* This works because speeds numbering starts at 0 and is contiguous. */ msg_pdbg("SPI speed is %sHz\n", spispeeds[spispeed].name); + /* Default buffer size is 19: 16 bytes data, 3 bytes control. */ +#define DEFAULT_BUFSIZE (16 + 3) + bp_commbuf = malloc(DEFAULT_BUFSIZE); + if (!bp_commbuf) { + bp_commbufsize = 0; + msg_perr("Out of memory!\n"); + return ERROR_OOM; + } + bp_commbufsize = DEFAULT_BUFSIZE; + ret = buspirate_serialport_setup(dev); - if (ret) + free(dev); + if (ret) { + bp_commbufsize = 0; + free(bp_commbuf); + bp_commbuf = NULL; return ret; - free(dev); + } if (register_shutdown(buspirate_spi_shutdown, NULL)) return 1; @@ -189,9 +234,9 @@ /* This is the brute force version, but it should work. */ for (i = 0; i < 19; i++) { /* Enter raw bitbang mode */ - buf[0] = 0x00; + bp_commbuf[0] = 0x00; /* Send the command, don't read the response. */ - ret = buspirate_sendrecv(buf, 1, 0); + ret = buspirate_sendrecv(bp_commbuf, 1, 0); if (ret) return ret; /* Read any response and discard it. */ @@ -212,76 +257,78 @@ sp_flush_incoming(); } /* Enter raw bitbang mode */ - buf[0] = 0x00; - ret = buspirate_sendrecv(buf, 1, 5); + bp_commbuf[0] = 0x00; + ret = buspirate_sendrecv(bp_commbuf, 1, 5); if (ret) return ret; - if (memcmp(buf, "BBIO", 4)) { + if (memcmp(bp_commbuf, "BBIO", 4)) { msg_perr("Entering raw bitbang mode failed!\n"); msg_pdbg("Got %02x%02x%02x%02x%02x\n", - buf[0], buf[1], buf[2], buf[3], buf[4]); + bp_commbuf[0], bp_commbuf[1], bp_commbuf[2], + bp_commbuf[3], bp_commbuf[4]); return 1; } - msg_pdbg("Raw bitbang mode version %c\n", buf[4]); - if (buf[4] != '1') { + msg_pdbg("Raw bitbang mode version %c\n", bp_commbuf[4]); + if (bp_commbuf[4] != '1') { msg_perr("Can't handle raw bitbang mode version %c!\n", - buf[4]); + bp_commbuf[4]); return 1; } /* Enter raw SPI mode */ - buf[0] = 0x01; - ret = buspirate_sendrecv(buf, 1, 4); + bp_commbuf[0] = 0x01; + ret = buspirate_sendrecv(bp_commbuf, 1, 4); if (ret) return ret; - if (memcmp(buf, "SPI", 3)) { + if (memcmp(bp_commbuf, "SPI", 3)) { msg_perr("Entering raw SPI mode failed!\n"); msg_pdbg("Got %02x%02x%02x%02x\n", - buf[0], buf[1], buf[2], buf[3]); + bp_commbuf[0], bp_commbuf[1], bp_commbuf[2], + bp_commbuf[3]); return 1; } - msg_pdbg("Raw SPI mode version %c\n", buf[3]); - if (buf[3] != '1') { + msg_pdbg("Raw SPI mode version %c\n", bp_commbuf[3]); + if (bp_commbuf[3] != '1') { msg_perr("Can't handle raw SPI mode version %c!\n", - buf[3]); + bp_commbuf[3]); return 1; } /* Initial setup (SPI peripherals config): Enable power, CS high, AUX */ - buf[0] = 0x40 | 0xb; - ret = buspirate_sendrecv(buf, 1, 1); + bp_commbuf[0] = 0x40 | 0xb; + ret = buspirate_sendrecv(bp_commbuf, 1, 1); if (ret) return 1; - if (buf[0] != 0x01) { + if (bp_commbuf[0] != 0x01) { msg_perr("Protocol error while setting power/CS/AUX!\n"); return 1; } /* Set SPI speed */ - buf[0] = 0x60 | spispeed; - ret = buspirate_sendrecv(buf, 1, 1); + bp_commbuf[0] = 0x60 | spispeed; + ret = buspirate_sendrecv(bp_commbuf, 1, 1); if (ret) return 1; - if (buf[0] != 0x01) { + if (bp_commbuf[0] != 0x01) { msg_perr("Protocol error while setting SPI speed!\n"); return 1; } /* Set SPI config: output type, idle, clock edge, sample */ - buf[0] = 0x80 | 0xa; - ret = buspirate_sendrecv(buf, 1, 1); + bp_commbuf[0] = 0x80 | 0xa; + ret = buspirate_sendrecv(bp_commbuf, 1, 1); if (ret) return 1; - if (buf[0] != 0x01) { + if (bp_commbuf[0] != 0x01) { msg_perr("Protocol error while setting SPI config!\n"); return 1; } /* De-assert CS# */ - buf[0] = 0x03; - ret = buspirate_sendrecv(buf, 1, 1); + bp_commbuf[0] = 0x03; + ret = buspirate_sendrecv(bp_commbuf, 1, 1); if (ret) return 1; - if (buf[0] != 0x01) { + if (bp_commbuf[0] != 0x01) { msg_perr("Protocol error while raising CS#!\n"); return 1; } @@ -294,55 +341,51 @@ static int buspirate_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { - static unsigned char *buf = NULL; int i = 0, ret = 0; if (writecnt > 16 || readcnt > 16 || (readcnt + writecnt) > 16) return SPI_INVALID_LENGTH; /* 3 bytes extra for CS#, len, CS#. */ - buf = realloc(buf, writecnt + readcnt + 3); - if (!buf) { - msg_perr("Out of memory!\n"); - exit(1); // -1 - } + if (buspirate_commbuf_grow(writecnt + readcnt + 3)) + return ERROR_OOM; /* Assert CS# */ - buf[i++] = 0x02; + bp_commbuf[i++] = 0x02; - buf[i++] = 0x10 | (writecnt + readcnt - 1); - memcpy(buf + i, writearr, writecnt); + bp_commbuf[i++] = 0x10 | (writecnt + readcnt - 1); + memcpy(bp_commbuf + i, writearr, writecnt); i += writecnt; - memset(buf + i, 0, readcnt); + memset(bp_commbuf + i, 0, readcnt); i += readcnt; /* De-assert CS# */ - buf[i++] = 0x03; + bp_commbuf[i++] = 0x03; - ret = buspirate_sendrecv(buf, i, i); + ret = buspirate_sendrecv(bp_commbuf, i, i); if (ret) { msg_perr("Bus Pirate communication error!\n"); return SPI_GENERIC_ERROR; } - if (buf[0] != 0x01) { + if (bp_commbuf[0] != 0x01) { msg_perr("Protocol error while lowering CS#!\n"); return SPI_GENERIC_ERROR; } - if (buf[1] != 0x01) { + if (bp_commbuf[1] != 0x01) { msg_perr("Protocol error while reading/writing SPI!\n"); return SPI_GENERIC_ERROR; } - if (buf[i - 1] != 0x01) { + if (bp_commbuf[i - 1] != 0x01) { msg_perr("Protocol error while raising CS#!\n"); return SPI_GENERIC_ERROR; } /* Skip CS#, length, writearr. */ - memcpy(readarr, buf + 2 + writecnt, readcnt); + memcpy(readarr, bp_commbuf + 2 + writecnt, readcnt); return ret; } -- http://www.hailfinger.org/ From svn at flashrom.org Tue Nov 15 09:08:16 2011 From: svn at flashrom.org (repository service) Date: Tue, 15 Nov 2011 09:08:16 +0100 Subject: [flashrom] [commit] r1467 - trunk Message-ID: Author: stefanct Date: Tue Nov 15 09:08:15 2011 New Revision: 1467 URL: http://flashrom.org/trac/flashrom/changeset/1467 Log: Add board enable for ASUS P4GV-LA (Guppy) The reverse engineering was done by Joshua. The actual patch was fabricated by Stefan. Request: http://www.flashrom.org/pipermail/flashrom/2011-November/008241.html Success report: http://paste.flashrom.org/view.php?id=914 Signed-off-by: Joshua Roys Signed-off-by: Stefan Tauner Tested-by: Mugendai Acked-by: Carl-Daniel Hailfinger Modified: trunk/board_enable.c trunk/print.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Mon Nov 14 14:00:12 2011 (r1466) +++ trunk/board_enable.c Tue Nov 15 09:08:15 2011 (r1467) @@ -2111,6 +2111,7 @@ {0x8086, 0x1A30, 0x1043, 0x8025, 0x8086, 0x244B, 0x104D, 0x80F0, NULL, NULL, NULL, P3, "ASUS", "P4B266-LM", 0, OK, intel_ich_gpio21_raise}, {0x8086, 0x1a30, 0x1043, 0x8070, 0x8086, 0x244b, 0x1043, 0x8028, NULL, NULL, NULL, P3, "ASUS", "P4B266", 0, OK, intel_ich_gpio22_raise}, {0x8086, 0x1A30, 0x1043, 0x8088, 0x8086, 0x24C3, 0x1043, 0x8089, NULL, NULL, NULL, P3, "ASUS", "P4B533-E", 0, NT, intel_ich_gpio22_raise}, + {0x8086, 0x2560, 0x103C, 0x2A00, 0x8086, 0x24C3, 0x103C, 0x2A01, "^Guppy", NULL, NULL, P3, "ASUS", "P4GV-LA (Guppy)", 0, OK, intel_ich_gpio21_raise}, {0x8086, 0x24D3, 0x1043, 0x80A6, 0x8086, 0x2578, 0x1043, 0x80F6, NULL, NULL, NULL, P3, "ASUS", "P4C800-E Deluxe", 0, OK, intel_ich_gpio21_raise}, {0x8086, 0x2570, 0x1043, 0x80F2, 0x8086, 0x24D5, 0x1043, 0x80F3, NULL, NULL, NULL, P3, "ASUS", "P4P800", 0, NT, intel_ich_gpio21_raise}, {0x8086, 0x2570, 0x1043, 0x80F2, 0x8086, 0x24D3, 0x1043, 0x80A6, "^P4P800-E$", NULL, NULL, P3, "ASUS", "P4P800-E Deluxe", 0, OK, intel_ich_gpio21_raise}, Modified: trunk/print.c ============================================================================== --- trunk/print.c Mon Nov 14 14:00:12 2011 (r1466) +++ trunk/print.c Tue Nov 15 09:08:15 2011 (r1467) @@ -635,6 +635,7 @@ B("ASUS", "P4B266-LM", 1, "http://esupport.sony.com/US/perl/swu-list.pl?mdl=PCVRX650", NULL), B("ASUS", "P4B533-E", 1, "ftp://ftp.asus.com.tw/pub/ASUS/mb/sock478/p4b533-e/", NULL), B("ASUS", "P4C800-E Deluxe", 1, "http://www.asus.com/product.aspx?P_ID=cFuVCr9bXXCckmcK", NULL), + B("ASUS", "P4GV-LA (Guppy)", 1, NULL, NULL), B("ASUS", "P4P800", 1, "http://www.asus.com/product.aspx?P_ID=DYt1Et9MlBChqzLb", NULL), B("ASUS", "P4P800-E Deluxe", 1, "http://www.asus.com/product.aspx?P_ID=INIJUvLlif7LHp3g", NULL), B("ASUS", "P4P800-VM", 1, NULL, NULL), From stefan.tauner at student.tuwien.ac.at Tue Nov 15 09:14:34 2011 From: stefan.tauner at student.tuwien.ac.at (Stefan Tauner) Date: Tue, 15 Nov 2011 09:14:34 +0100 Subject: [flashrom] [PATCH] Add board enable for ASUS P4GV-LA (Guppy) In-Reply-To: <4EC1970A.6020608@gmx.net> References: <1321298598-13925-1-git-send-email-stefan.tauner@student.tuwien.ac.at> <4EC1970A.6020608@gmx.net> Message-ID: <201111150814.pAF8ESdk011650@mail2.student.tuwien.ac.at> On Mon, 14 Nov 2011 23:32:42 +0100 Carl-Daniel Hailfinger wrote: > Am 14.11.2011 20:23 schrieb Stefan Tauner: > > The Reverse engineering was done by Joshua. The actual patch was > > fabricated by Stefan. > > Signed-off-by: Joshua Roys > > Signed-off-by: Stefan Tauner > > Acked-by: Carl-Daniel Hailfinger i forgot the print.c entry because i was in a hurry. it was added before committing this in r1467. Success report: http://paste.flashrom.org/view.php?id=914 -- Kind regards/Mit freundlichen Gr??en, Stefan Tauner From stefan.tauner at student.tuwien.ac.at Tue Nov 15 09:38:54 2011 From: stefan.tauner at student.tuwien.ac.at (Stefan Tauner) Date: Tue, 15 Nov 2011 09:38:54 +0100 Subject: [flashrom] [PATCH] Bus Pirate buffer management revamp In-Reply-To: <4EC21AAF.5060302@gmx.net> References: <201108111500.p7BF0isF015924@mail2.student.tuwien.ac.at> <4EC21AAF.5060302@gmx.net> Message-ID: <201111150838.pAF8cmqb030827@mail2.student.tuwien.ac.at> On Tue, 15 Nov 2011 08:54:23 +0100 Carl-Daniel Hailfinger wrote: > The shutdown function still has its own static buffer to allow shutdown > even if memory is tight, but AFAICS that should not be needed because > the buffer can never be too small for shutdown once init is complete. If > you agree with that assessment, I could change the shutdown function to > use the common buffer as well. from a glimpse that's true afaics. the shutdown function is registered after the buffer is set to DEFAULT_BUFSIZE. one would want to assert that this is big enough for the shutdown function to work in general... the grow function does what it says. i have not investigated if the buffer makes sense at all, or if it should by generalized... nevertheless i think it would make sense to implement your proposal before a final review... wont get much messier than it is now i guess :) -- Kind regards/Mit freundlichen Gr??en, Stefan Tauner From stefan.tauner at student.tuwien.ac.at Tue Nov 15 10:03:07 2011 From: stefan.tauner at student.tuwien.ac.at (Stefan Tauner) Date: Tue, 15 Nov 2011 10:03:07 +0100 Subject: [flashrom] flashrom tested on alix2d3 board In-Reply-To: References: Message-ID: <201111150903.pAF931aT024129@mail2.student.tuwien.ac.at> On Mon, 14 Nov 2011 13:04:48 +0100 Gerd Pauli wrote: > Found AMIC flash chip "A49LF040A" (512 kB, LPC). > === > This flash part has status UNTESTED for operations: WRITE > The test status of this chip may have been updated in the latest development > version of flashrom. If you are running the latest development version, > please email a report to flashrom at flashrom.org if any of the above operations > work correctly for you with this flash part. Please include the flashrom > output with the additional -V option for all operations you tested (-V, -Vr, > -Vw, -VE), and mention which mainboard or programmer you tested. > Please mention your board in the subject line. Thanks for your help! > Flash image seems to be a legacy BIOS. Disabling coreboot-related checks. > Reading old flash chip contents... done. > Erasing and writing flash chip... Trying erase function 0... 0x000000-0x00ffff:W, 0x010000-0x01ffff:S, 0x020000-0x02ffff:S, 0x030000-0x03ffff:S, 0x040000-0x04ffff:S, 0x050000-0x05ffff:S, 0x060000-0x06ffff:W, 0x070000-0x07ffff:W > Erase/write done. > Verifying flash... VERIFIED. Hello Gerd, thanks for your report! I have marked the flash chip as fully tested and added the alix board to our list of supported hardware. I will commit that later together with other small changes. > Found chipset "AMD CS5536" with PCI ID 1022:2080. Enabling flash write... OK. > WARNING: unexpected second chipset match: "AMD CS5536" > ignoring, please report lspci and board URL to flashrom at flashrom.org > with 'CHIPSET: your board name' in the subject line. no idea about that... -- Kind regards/Mit freundlichen Gr??en, Stefan Tauner From mp at rnt.de Tue Nov 15 16:42:20 2011 From: mp at rnt.de (Panny, Martin) Date: Tue, 15 Nov 2011 16:42:20 +0100 Subject: [flashrom] flashrom v0.9.4-r1467 + SUPERMICOR X9SCL Message-ID: hi, just a report, flashrom does not work with SUPEMRICRO X9SCL, errors while trying to backup bios with "flashrom -r out.rom": "Transaction error! Read operation failed!" logs attached. thank you regards martin panny -------------- next part -------------- A non-text attachment was scrubbed... Name: flashrom_v0.9.4-r1467_SUPERMICRO_X9SCL-V.log Type: application/octet-stream Size: 20804 bytes Desc: flashrom_v0.9.4-r1467_SUPERMICRO_X9SCL-V.log URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: flashrom_v0.9.4-r1467_SUPERMICRO_X9SCL-V-r.log Type: application/octet-stream Size: 20967 bytes Desc: flashrom_v0.9.4-r1467_SUPERMICRO_X9SCL-V-r.log URL: From paulk at paulk.fr Tue Nov 15 19:53:40 2011 From: paulk at paulk.fr (PaulK) Date: Tue, 15 Nov 2011 19:53:40 +0100 Subject: [flashrom] ASRock ConRoeXFire-eSATA2 board support Message-ID: <1321383220.1581.11.camel@aldrin> Hi! I'm new to this list so I'll start by introducing myself a bit: I'm a french student involved in free software: I use GNU/Linux distros on all my PCs, mostly with the fully free Trisquel distro and I'm also a developer (I know C quite well) mostly involved in the Replicant project (fully free Android derivate) as a hacker (lower-level stuff). The lead dev on the project (GNUtoo) decided to look at how doable it is to port his board to coreboot, so I decided to follow his lead and look at which of the motherboards I own would be the best one for coreboot. I have 2 boards that might be good candidates, ASRock ConRoeXFire-eSATA2 (which has a socketed PLCC32 chip) and Asus P5LP-LE (Lithium) with a soldered PLCC32 chip. Both boards have supported North/Southbridge and SuperIO already supported in coreboot. I decided to start the work on the ASRock ConRoeXFire-eSATA2 one and got a few needed things from the local electronics shop. Then I started to run flashrom on it. So far, I've been able to read the content of the PLCC chip with flashrom (http://download.paulk.fr/coreboot/conroe-xfire-esata2.bin) but it failed at write. All the logs and necessary informations should be attached to this mail. What are the next steps for me to have working write on flashrom with that board? -- Paul Kocialkowski * Website : http://www.paulk.fr/ * Blog : http://blog.paulk.fr/ * Microblogging : http://status.paulk.fr/ -------------- next part -------------- A non-text attachment was scrubbed... Name: flashrom-V.log Type: text/x-log Size: 7458 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: lspci-full.log Type: text/x-log Size: 41133 bytes Desc: not available URL: -------------- next part -------------- W83627DHG -------------- next part -------------- A non-text attachment was scrubbed... Name: superio-deV.log Type: text/x-log Size: 359646 bytes Desc: not available URL: From marcosfrm at gmail.com Wed Nov 16 11:27:02 2011 From: marcosfrm at gmail.com (Marcos Felipe Rasia de Mello) Date: Wed, 16 Nov 2011 08:27:02 -0200 Subject: [flashrom] Question about the EC code Message-ID: Hi flashrom people, Reading the wiki, I understood the basics about the laptops ECs. A friend brought to me a bricked Clevo M540SE/M550SE (main board "6-71-M5E50-D02A") after an unsuccessful BIOS upgrade. He used these two files: ftp://usftp.clevo.com.tw/ALLBIOS/M5xxSE/M5xSE_H805.zip ftp://usftp.clevo.com.tw/ALLBIOS/M5xxSE/M5xSE_13.zip (he found the files in this forum: http://forum.notebookreview.com/sager-clevo/416916-clevo-bios-thread-55.html ) The first file is the "EC update", which need to be updated before que second one, the BIOS itself. What I do not understand is why the EC code is separated. According to what I understand, the EC code is part of BIOS image and the update utility needs some voodoo work to put the EC in a "loop", update the flash chip and then put the EC into operation again. It is an old laptop, with a soldered PLCC-32 chip (I do not remember the exact model now, but it is a plain SST 512KB LPC chip). If I put a socket in the laptop and program the chip with the WPH file (second link) via hot swap using a desktop board (same flash voltage, bus) will it work? Marcos From paulk at paulk.fr Wed Nov 16 21:10:41 2011 From: paulk at paulk.fr (PaulK) Date: Wed, 16 Nov 2011 21:10:41 +0100 Subject: [flashrom] [PATCH] ASRock ConRoeXFire-eSATA2 board support In-Reply-To: <1321383220.1581.11.camel@aldrin> References: <1321383220.1581.11.camel@aldrin> Message-ID: <1321474241.1577.5.camel@aldrin> Thanks to roysjosh on IRC, I was able to quickly get the write protection off with intel_ich_gpio16_raise I was able to write the non-free BIOS to another chip and boot this chip: it works perfectly! So the logs of write in flashrom along with the diff I made of the board line in board_enable.c are attached to this mail Diff should be: Signed-off-by: Joshua Roys Signed-off-by: Paul Kocialkowski -- Paul Kocialkowski * Website : http://www.paulk.fr/ * Blog : http://blog.paulk.fr/ * Microblogging : http://status.paulk.fr/ -------------- next part -------------- A non-text attachment was scrubbed... Name: conroe-xfire-esata2-board_enable.diff Type: text/x-patch Size: 1453 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: conroe-xfire-esata2-write.log Type: text/x-log Size: 8217 bytes Desc: not available URL: From svn at flashrom.org Wed Nov 16 23:08:12 2011 From: svn at flashrom.org (repository service) Date: Wed, 16 Nov 2011 23:08:12 +0100 Subject: [flashrom] [commit] r1468 - trunk Message-ID: Author: stefanct Date: Wed Nov 16 23:08:11 2011 New Revision: 1468 URL: http://flashrom.org/trac/flashrom/changeset/1468 Log: Add board enable for ASRock ConRoeXFire-eSATA2 The reverse engineering was done by Joshua. The actual patch was fabricated by Paul with some polishing by Stefan. Success log: http://www.flashrom.org/pipermail/flashrom/2011-November/008257.html Signed-off-by: Joshua Roys Signed-off-by: Paul Kocialkowski Acked-by: Stefan Tauner Modified: trunk/board_enable.c trunk/print.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Tue Nov 15 09:08:15 2011 (r1467) +++ trunk/board_enable.c Wed Nov 16 23:08:11 2011 (r1468) @@ -2089,6 +2089,7 @@ {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe61", P3, "Artec Group", "DBE61", 0, OK, board_artecgroup_dbe6x}, {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe62", P3, "Artec Group", "DBE62", 0, OK, board_artecgroup_dbe6x}, {0x8086, 0x277c, 0xa0a0, 0x060b, 0x8086, 0x27da, 0xa0a0, 0x060b, NULL, NULL, NULL, P3, "AOpen", "i975Xa-YDG", 0, OK, board_aopen_i975xa_ydg}, + {0x8086, 0x27b8, 0x1849, 0x27b8, 0x8086, 0x27da, 0x1849, 0x27da, "^ConRoeXFire-eSATA2", NULL, NULL, P3, "ASRock", "ConRoeXFire-eSATA2", 0, OK, intel_ich_gpio16_raise}, {0x1039, 0x0741, 0x1849, 0x0741, 0x1039, 0x5513, 0x1849, 0x5513, "^K7S41 $", NULL, NULL, P3, "ASRock", "K7S41", 0, OK, w836xx_memw_enable_2e}, {0x1039, 0x0741, 0x1849, 0x0741, 0x1039, 0x5513, 0x1849, 0x5513, "^K7S41GX$", NULL, NULL, P3, "ASRock", "K7S41GX", 0, OK, w836xx_memw_enable_2e}, {0x8086, 0x24D4, 0x1849, 0x24D0, 0x8086, 0x24D5, 0x1849, 0x9739, NULL, NULL, NULL, P3, "ASRock", "P4i65GV", 0, OK, intel_ich_gpio23_raise}, Modified: trunk/print.c ============================================================================== --- trunk/print.c Tue Nov 15 09:08:15 2011 (r1467) +++ trunk/print.c Wed Nov 16 23:08:11 2011 (r1468) @@ -562,6 +562,7 @@ B("ASRock", "A330GC", 1, "http://www.asrock.com/mb/overview.asp?Model=A330GC", NULL), B("ASRock", "A770CrossFire", 1, "http://www.asrock.com/mb/overview.asp?Model=A770CrossFire", NULL), B("ASRock", "ALiveNF6G-DVI", 1, "http://www.asrock.com/mb/overview.asp?Model=ALiveNF6G-DVI", NULL), + B("ASRock", "ConRoeXFire-eSATA2", 1, "http://www.asrock.com/mb/overview.asp?model=conroexfire-esata2", NULL), B("ASRock", "K7S41", 1, "http://www.asrock.com/mb/overview.asp?Model=K7S41", NULL), B("ASRock", "K7S41GX", 1, "http://www.asrock.com/mb/overview.asp?Model=K7S41GX", NULL), B("ASRock", "K7VT4A+", 0, "http://www.asrock.com/mb/overview.asp?Model=K7VT4A%2b", "No chip found, probably due to flash translation. http://www.flashrom.org/pipermail/flashrom/2009-August/000393.html"), From stefan.tauner at student.tuwien.ac.at Wed Nov 16 23:14:57 2011 From: stefan.tauner at student.tuwien.ac.at (Stefan Tauner) Date: Wed, 16 Nov 2011 23:14:57 +0100 Subject: [flashrom] [PATCH] ASRock ConRoeXFire-eSATA2 board support In-Reply-To: <1321474241.1577.5.camel@aldrin> References: <1321383220.1581.11.camel@aldrin> <1321474241.1577.5.camel@aldrin> Message-ID: <201111162214.pAGMEm1p008849@mail2.student.tuwien.ac.at> On Wed, 16 Nov 2011 21:10:41 +0100 PaulK wrote: > Thanks to roysjosh on IRC, I was able to quickly get the write > protection off with intel_ich_gpio16_raise > > I was able to write the non-free BIOS to another chip and boot this > chip: it works perfectly! > > So the logs of write in flashrom along with the diff I made of the board > line in board_enable.c are attached to this mail > > Diff should be: > Signed-off-by: Joshua Roys > Signed-off-by: Paul Kocialkowski > thanks paul (and joshua!) i have added another pci id set and also an entry for the board to print.c. Acked-by: Stefan Tauner and committed in r1468. -- Kind regards/Mit freundlichen Gr??en, Stefan Tauner From c-d.hailfinger.devel.2006 at gmx.net Thu Nov 17 00:13:35 2011 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Thu, 17 Nov 2011 00:13:35 +0100 Subject: [flashrom] FOSDEM 2012 In-Reply-To: <4EBD5FE7.3050609@gmx.net> References: <4EBD5FE7.3050609@gmx.net> Message-ID: <4EC4439F.5020406@gmx.net> Call for lightning talks and stands is NOW! http://fosdem.org/2012/call-for-participation I will be at FOSDEM. Anybody else? Regards, Carl-Daniel Am 11.11.2011 18:48 schrieb Carl-Daniel Hailfinger: > Hey, > > it seems we forgot to apply for a devroom (well, at least I didn't see > anything on the mailing list). > Should we submit talks to the individual devrooms? > Should we ask for a coreboot/flashrom booth/table? > > Regards, > Carl-Daniel -- http://www.hailfinger.org/ From svante at fyraess.com Thu Nov 17 13:58:23 2011 From: svante at fyraess.com (Svante Olofsson) Date: Thu, 17 Nov 2011 14:58:23 +0200 Subject: [flashrom] Asus A7NVM400 (A7NX8-VM400) Message-ID: Hi, I tried to flash an A7N8X-VM400 board with the current bios (got it with flashrom -r). The current bios rom was of identical size as the downloaded newer bios rom. I figured it would be safest to try to flash with the old one :) The information below is copied from the terminal: svante at stereo:~$ sudo flashrom -wV current_A7NVM400-ASUS.080009.rom flashrom v0.9.1-r946 No coreboot table found. DMI string system-manufacturer: "Ssystem manufacturer" DMI string system-product-name: "System product name" DMI string system-version: "System version" DMI string baseboard-manufacturer: "ASUSTeK Computer INC." DMI string baseboard-product-name: "A7NVM400" DMI string baseboard-version: "Rev 2.xx" DMI string chassis-type: "Desktop" Found ITE Super I/O, id 8712 Found chipset "NVIDIA NForce2", enabling flash write... OK. This chipset supports the following protocols: Non-SPI. Calibrating delay loop... 567M loops per second, 100 myus = 202 us. OK. Probing for AMD Am29F010A/B, 128 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F002(N)BB, 256 KB: probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F002(N)BT, 256 KB: probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F016D, 2048 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F040B, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F080B, 1024 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV040B, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV081B, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ASD AE49F2008, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x9d, id2 0x6e Probing for Atmel AT25DF021, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25DF041A, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25DF081, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25DF161, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25DF321, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25DF321A, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25DF641, 8192 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25F512B, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25FS010, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25FS040, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT26DF041, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT26DF081A, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT26DF161, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT26DF161A, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT26F004, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT29C512, 64 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Atmel AT29C010A, 128 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Atmel AT29C020, 256 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Atmel AT29C040A, 512 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Atmel AT45CS1282, 16896 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB011D, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB021D, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB041D, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB081D, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB161D, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB321C, 4224 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB321D, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB642D, 8192 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT49BV512, 64 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Atmel AT49F002(N), 256 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Atmel AT49F002(N)T, 256 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for AMIC A25L40PT, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for AMIC A25L40PU, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for AMIC A29002B, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC A29002T, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC A29040B, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC A49LF040A, 512 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for EMST F49B002UA, 256 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Eon EN25B05, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B05T, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B10, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B10T, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B20, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B20T, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B40, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B40T, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B80, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B80T, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B16, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B16T, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B32, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B32T, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B64, 8192 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B64T, 8192 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25D16, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25F05, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25F10, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25F20, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25F40, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25F80, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25F16, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25F32, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN29F010, 128 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for EON EN29F002(A)(N)B, 256 KB: probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for EON EN29F002(A)(N)T, 256 KB: probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F004BC, 512 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F004TC, 512 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F400BC, 512 KB: probe_m29f400bt: id1 0xff, id2 0xff Probing for Fujitsu MBM29F400TC, 512 KB: probe_m29f400bt: id1 0xff, id2 0xff Probing for Intel 28F001BX-B, 128 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Intel 28F001BX-T, 128 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Intel 28F004S5, 512 KB: probe_82802ab: id1 0xff, id2 0xff Probing for Intel 82802AB, 512 KB: probe_82802ab: id1 0xff, id2 0xff Probing for Intel 82802AC, 1024 KB: probe_82802ab: id1 0xff, id2 0xff Probing for Macronix MX25L512, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L1005, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L2005, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L4005, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L8005, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L1605, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L1635D, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L3205, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L3235D, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L6405, 8192 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L12805, 16384 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX29F001B, 128 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F001T, 128 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F002B, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F002T, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29LV040, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Numonyx M25PE10, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Numonyx M25PE20, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Numonyx M25PE40, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Numonyx M25PE80, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Numonyx M25PE16, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm25LV010, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm25LV016B, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm25LV020, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm25LV040, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm25LV080B, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm25LV512, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm29F002T, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm29F002B, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm39LV010, 128 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL002, 256 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for PMC Pm49FL004, 512 KB: probe_jedec_common: id1 0x9d, id2 0x6e Found chip "PMC Pm49FL004" (512 KB, LPC,FWH) at physical address 0xfff80000. Probing for Sanyo LF25FW203A, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Sharp LHF00L04, 1024 KB: probe_82802ab: id1 0xff, id2 0xff Probing for Spansion S25FL008A, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Spansion S25FL016A, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST25VF016B, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST25VF032B, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST25VF040.REMS, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST25VF040B, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST25VF040B.REMS, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST25VF080B, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST28SF040A, 512 KB: probe_82802ab: id1 0xff, id2 0xff Probing for SST SST29EE010, 128 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST29LE010, 128 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST29EE020A, 256 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST29LE020, 256 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST39SF512, 64 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST39SF010A, 128 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST39SF020A, 256 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST39SF040, 512 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST39VF512, 64 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST39VF010, 128 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST39VF020, 256 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST39VF040, 512 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST39VF080, 1024 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF002A/B, 256 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST49LF003A/B, 384 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST49LF004A/B, 512 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST49LF004C, 512 KB: probe_82802ab: id1 0xff, id2 0xff Probing for SST SST49LF008A, 1024 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 KB: probe_82802ab: id1 0xff, id2 0xff Probing for SST SST49LF016C, 2048 KB: probe_82802ab: id1 0xff, id2 0xff Probing for SST SST49LF020, 256 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST49LF020A, 256 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST49LF040, 512 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST49LF040B, 512 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST49LF080A, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF160C, 2048 KB: probe_82802ab: id1 0xff, id2 0xff Probing for ST M25P05-A, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P05.RES, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P10-A, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P10.RES, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P20, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P40, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P40-old, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P80, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P16, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P32, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P64, 8192 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P128, 16384 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M29F002B, 256 KB: probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29F002T/NT, 256 KB: probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29F040B, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29F400BT, 512 KB: probe_m29f400bt: id1 0xff, id2 0xff Probing for ST M29W010B, 128 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29W040B, 512 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29W512B, 64 KB: probe_jedec_common: id1 0x3f, id2 0xae, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040A, 512 KB: probe_82802ab: id1 0xff, id2 0xff Probing for ST M50FLW040B, 512 KB: probe_82802ab: id1 0xff, id2 0xff Probing for ST M50FLW080A, 1024 KB: probe_82802ab: id1 0xff, id2 0xff Probing for ST M50FLW080B, 1024 KB: probe_82802ab: id1 0xff, id2 0xff Probing for ST M50FW002, 256 KB: probe_82802ab: id1 0x65, id2 0xd0 Probing for ST M50FW016, 2048 KB: probe_82802ab: id1 0xff, id2 0xff Probing for ST M50FW040, 512 KB: probe_82802ab: id1 0xff, id2 0xff Probing for ST M50FW080, 1024 KB: probe_82802ab: id1 0xff, id2 0xff Probing for ST M50LPW116, 2048 KB: probe_82802ab: id1 0xff, id2 0xff Probing for SyncMOS S29C31004T, 512 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SyncMOS S29C51001T, 128 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SyncMOS S29C51002T, 256 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SyncMOS S29C51004T, 512 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for TI TMS29F002RB, 256 KB: probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for TI TMS29F002RT, 256 KB: probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W25x10, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Winbond W25x20, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Winbond W25x40, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Winbond W25x80, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Winbond W25x16, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Winbond W25x32, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Winbond W25x64, 8192 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Winbond W29C011, 128 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W29C020C, 256 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W29C040P, 512 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W29EE011, 128 KB: Probing disabled for Winbond W29EE011 because the probing sequence puts the AMIC A49LF040A in a funky state. Use 'flashrom -c W29EE011' if you have a board with this chip. Probing for Winbond W39V040A, 512 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W39V040B, 512 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W39V040C, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W39V040FA, 512 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W39V080A, 1024 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49F002U, 256 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W49V002A, 256 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W49V002FA, 256 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W39V080FA, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA (dual mode), 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x9d, id2 0x6e Probing for Atmel unknown Atmel SPI chip, 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for EON unknown EON SPI chip, 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix unknown Macronix SPI chip, 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC unknown PMC SPI chip, 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST unknown SST SPI chip, 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST unknown ST SPI chip, 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Sanyo unknown Sanyo SPI chip, 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Generic unknown SPI chip (RDID), 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Generic unknown SPI chip (REMS), 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. === This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE Please email a report to flashrom at flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -rV, -wV, -EV), and mention which mainboard or programmer you tested. Thanks for your help! === Flash image seems to be a legacy BIOS. Disabling checks. Writing flash chip... Erasing flash chip... Looking at blockwise erase function 0... trying... 0x000000-0x000fff, ERASE FAILED at 0x00000008! Expected=0xff, Read=0x4c, failed byte count from 0x00000000-0x00000fff: 0xfdc ERASE FAILED! Looking at blockwise erase function 1... trying... 0x000000-0x00ffff, ERASE FAILED at 0x00000008! Expected=0xff, Read=0x4c, failed byte count from 0x00000000-0x0000ffff: 0xfed5 ERASE FAILED! Looking at blockwise erase function 2... trying... 0x000000-0x07ffff, ERASE FAILED at 0x00000008! Expected=0xff, Read=0x4c, failed byte count from 0x00000000-0x0007ffff: 0x687be ERASE FAILED! Looking at blockwise erase function 3... not defined. Looking for another erase function. Looking at blockwise erase function 4... not defined. Looking for another erase function. FAILED! ERASE FAILED! FAILED! Your flash chip is in an unknown state. Get help on IRC at irc.freenode.net (channel #flashrom) or mail flashrom at flashrom.org! ------------------------------------------------------------------------------- DO NOT REBOOT OR POWEROFF! what do you think, am I screwed? Best regards, --Svante -------------- next part -------------- An HTML attachment was scrubbed... URL: From stefan.tauner at student.tuwien.ac.at Thu Nov 17 15:12:34 2011 From: stefan.tauner at student.tuwien.ac.at (Stefan Tauner) Date: Thu, 17 Nov 2011 15:12:34 +0100 Subject: [flashrom] Asus A7NVM400 (A7NX8-VM400) In-Reply-To: References: Message-ID: <201111171412.pAHECO7v026468@mail2.student.tuwien.ac.at> On Thu, 17 Nov 2011 14:58:23 +0200 Svante Olofsson wrote: > Hi, > > I tried to flash an A7N8X-VM400 board with the current bios (got it with > flashrom -r). The current bios rom was of identical size as the downloaded > newer bios rom. I figured it would be safest to try to flash with the old > one :) hello by "old one" you mean the backed up rom contents i guess? well in newer versions of flashrom this would lead to a complete skipped write because it checks for equal content on the chip before erasing anything ;) what is more of a problem is the *old* version of flashrom you have used, as you have seen... > > The information below is copied from the terminal: > > svante at stereo:~$ sudo flashrom -wV current_A7NVM400-ASUS.080009.rom > flashrom v0.9.1-r946 > [?] > Flash image seems to be a legacy BIOS. Disabling checks. > Writing flash chip... Erasing flash chip... Looking at blockwise erase > function 0... trying... 0x000000-0x000fff, ERASE FAILED at 0x00000008! > Expected=0xff, Read=0x4c, failed byte count from 0x00000000-0x00000fff: > 0xfdc > ERASE FAILED! > > Looking at blockwise erase function 1... trying... 0x000000-0x00ffff, ERASE > FAILED at 0x00000008! Expected=0xff, Read=0x4c, failed byte count from > 0x00000000-0x0000ffff: 0xfed5 > ERASE FAILED! > > Looking at blockwise erase function 2... trying... 0x000000-0x07ffff, ERASE > FAILED at 0x00000008! Expected=0xff, Read=0x4c, failed byte count from > 0x00000000-0x0007ffff: 0x687be > ERASE FAILED! this looks like a complete write protection, which is quite common... see http://flashrom.org/Board_Enable for details. > > what do you think, am I screwed? not at all, but we will probably need to add some code to enable writing on your board. first of all please get a current version of flashrom from subversion and compile it. http://flashrom.org/Downloads then verify that the rom content is still the same as the backed up image (e.g. flashrom -v backup.rom). then reply with the logs of the following commands (run as root) attached/embedded: lspci -xxnnvvv flashrom -V if possible also superiotool -deV you can of course also try to reverse engineer the needed code yourself as described here: http://flashrom.org/Finding_Board_Enable_by_Reverse_Engineering if you wait for us to do it it can take its time... -- Kind regards/Mit freundlichen Gr??en, Stefan Tauner From roysjosh at gmail.com Thu Nov 17 15:05:42 2011 From: roysjosh at gmail.com (Joshua Roys) Date: Thu, 17 Nov 2011 09:05:42 -0500 Subject: [flashrom] Asus A7NVM400 (A7NX8-VM400) In-Reply-To: References: Message-ID: <4EC514B6.3060508@gmail.com> On 11/17/2011 07:58 AM, Svante Olofsson wrote: > Hi, > > I tried to flash an A7N8X-VM400 board with the current bios (got it with > flashrom -r). The current bios rom was of identical size as the > downloaded newer bios rom. I figured it would be safest to try to flash > with the old one :) > > The information below is copied from the terminal: > > svante at stereo:~$ sudo flashrom -wV current_A7NVM400-ASUS.080009.rom > flashrom v0.9.1-r946 This is a very old version of flashrom. Can you please download and try the latest? Then try writing the original rom back with the newer flashrom. This may restore the bits that were written by the old flashrom. It is likely that you will need a "board enable" in order to write to your entire chip. Please reply with the output of `lspci -vvvnnxxx' and `superiotool -deV' both as root. Oh, and the output of the newer `flashrom -V' . Thanks, Josh From svante at fyraess.com Thu Nov 17 17:23:32 2011 From: svante at fyraess.com (Svante Olofsson) Date: Thu, 17 Nov 2011 18:23:32 +0200 Subject: [flashrom] Asus A7NVM400 (A7NX8-VM400) In-Reply-To: <201111171412.pAHECO7v026468@mail2.student.tuwien.ac.at> References: <201111171412.pAHECO7v026468@mail2.student.tuwien.ac.at> Message-ID: Hi, thank you very much for taking time to look into this. I used the ubuntu version of flashrom (an old ubuntu). I have now installed a newer version of flashrom. I used flashrom -r to get a new backup and diffed it against the one I got with the old flashrom version. They are the same :) I tried to write the backup.rom with flashrom -V -w backup.rom and that seemed to work even if the rom was identical to the one already present. To me everything looks quite good and I am considering writing the new rom that I downloaded. What do you thing? Do you still want me to post any more information with lspci -xxnnvvv, flashrom -V and superiotool -deV ? Below is the output of the write operation: svante at stereo:/backup$ sudo flashrom -V -w backup.rom flashrom v0.9.4-r1395 on Linux 2.6.32-35-generic (i686), built with libpci 3.0.0, GCC 4.4.3, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 294M loops per second, delay more than 10% too short (got 38% of expected delay), recalculating... 279M loops per second, delay more than 10% too short (got 36% of expected delay), recalculating... 279M loops per second, delay more than 10% too short (got 36% of expected delay), recalculating... 283M loops per second, delay more than 10% too short (got 37% of expected delay), recalculating... 357M loops per second, delay loop is unreliable, trying to continue 10 myus = 6 us, 100 myus = 46 us, 1000 myus = 446 us, 10000 myus = 17513 us, 4 myus = 4 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "Ssystem manufacturer" DMI string system-product-name: "System product name" DMI string system-version: "System version" DMI string baseboard-manufacturer: "ASUSTeK Computer INC." DMI string baseboard-product-name: "A7NVM400" DMI string baseboard-version: "Rev 2.xx" DMI string chassis-type: "Desktop" Found ITE Super I/O, ID 0x8712 on port 0x2e Found chipset "NVIDIA NForce2" with PCI ID 10de:0060. Enabling flash write... OK. This chipset supports the following protocols: Non-SPI. Super I/O ID 0x8712 is not on the list of flash capable controllers. Probing for AMD Am29F010A/B, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F002(N)BB, 256 kB: probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F002(N)BT, 256 kB: probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F016D, 2048 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F040B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F080B, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV001BB, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV001BT, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV002BB, 256 kB: probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV002BT, 256 kB: probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV004BB, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV004BT, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV008BB, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV008BT, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV040B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV081B, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC A29002B, 256 kB: probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC A29002T, 256 kB: probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC A29040B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC A49LF040A, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Atmel AT29C512, 64 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Atmel AT29C010A, 128 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Atmel AT29C020, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Atmel AT29C040A, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Atmel AT49BV512, 64 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Atmel AT49F020, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Atmel AT49F002(N), 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Atmel AT49F002(N)T, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Bright BM29F040, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for EMST F49B002UA, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Eon EN29F010, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Eon EN29F002(A)(N)B, 256 kB: probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Eon EN29F002(A)(N)T, 256 kB: probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F004BC, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F004TC, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F400BC, 512 kB: probe_m29f400bt: id1 0xff, id2 0xff Probing for Fujitsu MBM29F400TC, 512 kB: probe_m29f400bt: id1 0xff, id2 0xff Probing for Hyundai HY29F002T, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Hyundai HY29F002B, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Hyundai HY29F040A, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F001BN/BX-B, 128 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Intel 28F001BN/BX-T, 128 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Intel 28F002BC/BL/BV/BX-T, 256 kB: probe_82802ab: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F008S3/S5/SC, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F004B5/BE/BV/BX-B, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F004B5/BE/BV/BX-T, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F400BV/BX/CE/CV-B, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F400BV/BX/CE/CV-T, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F001B, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F001T, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F002B, 256 kB: probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F002T, 256 kB: probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F040, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29LV040, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for MoselVitelic V29C51000B, 64 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for MoselVitelic V29C51000T, 64 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for MoselVitelic V29C51400B, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for MoselVitelic V29C51400T, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for MoselVitelic V29LC51000, 64 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for MoselVitelic V29LC51001, 128 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for MoselVitelic V29LC51002, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for PMC Pm29F002T, 256 kB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm29F002B, 256 kB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm39LV010, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm39LV020, 256 kB: probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm39LV040, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Found PMC flash chip "Pm49FL004" (512 kB, LPC, FWH) at physical address 0xfff80000. Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST28SF040A, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST29EE010, 128 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST29LE010, 128 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST29EE020A, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST29LE020, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST39SF512, 64 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST39SF010A, 128 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST39SF020A, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST39SF040, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST39VF512, 64 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST39VF010, 128 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST39VF020, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST39VF040, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST39VF080, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF020, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST49LF020A, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST49LF040, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST49LF040B, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST49LF080A, 1024 kB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF160C, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29F002B, 256 kB: probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29F002T/NT, 256 kB: probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29F040B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29F400BB, 512 kB: probe_m29f400bt: id1 0xff, id2 0xff Probing for ST M29F400BT, 512 kB: probe_m29f400bt: id1 0xff, id2 0xff Probing for ST M29W010B, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29W040B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29W512B, 64 kB: probe_jedec_common: id1 0x3f, id2 0xae, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50LPW116, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SyncMOS/MoselVitelic {F,S,V}29C51001B, 128 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SyncMOS/MoselVitelic {F,S,V}29C51001T, 128 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SyncMOS/MoselVitelic {F,S,V}29C51002B, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SyncMOS/MoselVitelic {F,S,V}29C51002T, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SyncMOS/MoselVitelic {F,S,V}29C51004B, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SyncMOS/MoselVitelic {F,S,V}29C51004T, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SyncMOS/MoselVitelic {S,V}29C31004B, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SyncMOS/MoselVitelic {S,V}29C31004T, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for TI TMS29F002RB, 256 kB: probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for TI TMS29F002RT, 256 kB: probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W29C010(M)/W29C011A/W29EE011/W29EE012-old, 128 kB: Old Winbond W29* probe method disabled because the probing sequence puts the AMIC A49LF040A in a funky state. Use 'flashrom -c W29C010(M)/W29C011A/W29EE011/W29EE012-old' if you have a board with such a chip. Probing for Winbond W29C010(M)/W29C011A/W29EE011/W29EE012, 128 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W29C020(C)/W29C022, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W29C040/P, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W39L040, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W39V040A, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W39V040B, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W39V040C, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W39V080A, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49F002U/N, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W49F020, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W49V002A, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Flash image seems to be a legacy BIOS. Disabling coreboot-related checks. Reading old flash chip contents... done. Erasing and writing flash chip... Trying erase function 0... 0x000000-0x000fff:S, 0x001000-0x001fff:S, 0x002000-0x002fff:S, 0x003000-0x003fff:S, 0x004000-0x004fff:S, 0x005000-0x005fff:S, 0x006000-0x006fff:S, 0x007000-0x007fff:S, 0x008000-0x008fff:S, 0x009000-0x009fff:S, 0x00a000-0x00afff:S, 0x00b000-0x00bfff:S, 0x00c000-0x00cfff:S, 0x00d000-0x00dfff:S, 0x00e000-0x00efff:S, 0x00f000-0x00ffff:S, 0x010000-0x010fff:S, 0x011000-0x011fff:S, 0x012000-0x012fff:S, 0x013000-0x013fff:S, 0x014000-0x014fff:S, 0x015000-0x015fff:S, 0x016000-0x016fff:S, 0x017000-0x017fff:S, 0x018000-0x018fff:S, 0x019000-0x019fff:S, 0x01a000-0x01afff:S, 0x01b000-0x01bfff:S, 0x01c000-0x01cfff:S, 0x01d000-0x01dfff:S, 0x01e000-0x01efff:S, 0x01f000-0x01ffff:S, 0x020000-0x020fff:S, 0x021000-0x021fff:S, 0x022000-0x022fff:S, 0x023000-0x023fff:S, 0x024000-0x024fff:S, 0x025000-0x025fff:S, 0x026000-0x026fff:S, 0x027000-0x027fff:S, 0x028000-0x028fff:S, 0x029000-0x029fff:S, 0x02a000-0x02afff:S, 0x02b000-0x02bfff:S, 0x02c000-0x02cfff:S, 0x02d000-0x02dfff:S, 0x02e000-0x02efff:S, 0x02f000-0x02ffff:S, 0x030000-0x030fff:S, 0x031000-0x031fff:S, 0x032000-0x032fff:S, 0x033000-0x033fff:S, 0x034000-0x034fff:S, 0x035000-0x035fff:S, 0x036000-0x036fff:S, 0x037000-0x037fff:S, 0x038000-0x038fff:S, 0x039000-0x039fff:S, 0x03a000-0x03afff:S, 0x03b000-0x03bfff:S, 0x03c000-0x03cfff:S, 0x03d000-0x03dfff:S, 0x03e000-0x03efff:S, 0x03f000-0x03ffff:S, 0x040000-0x040fff:S, 0x041000-0x041fff:S, 0x042000-0x042fff:S, 0x043000-0x043fff:S, 0x044000-0x044fff:S, 0x045000-0x045fff:S, 0x046000-0x046fff:S, 0x047000-0x047fff:S, 0x048000-0x048fff:S, 0x049000-0x049fff:S, 0x04a000-0x04afff:S, 0x04b000-0x04bfff:S, 0x04c000-0x04cfff:S, 0x04d000-0x04dfff:S, 0x04e000-0x04efff:S, 0x04f000-0x04ffff:S, 0x050000-0x050fff:S, 0x051000-0x051fff:S, 0x052000-0x052fff:S, 0x053000-0x053fff:S, 0x054000-0x054fff:S, 0x055000-0x055fff:S, 0x056000-0x056fff:S, 0x057000-0x057fff:S, 0x058000-0x058fff:S, 0x059000-0x059fff:S, 0x05a000-0x05afff:S, 0x05b000-0x05bfff:S, 0x05c000-0x05cfff:S, 0x05d000-0x05dfff:S, 0x05e000-0x05efff:S, 0x05f000-0x05ffff:S, 0x060000-0x060fff:S, 0x061000-0x061fff:S, 0x062000-0x062fff:S, 0x063000-0x063fff:S, 0x064000-0x064fff:S, 0x065000-0x065fff:S, 0x066000-0x066fff:S, 0x067000-0x067fff:S, 0x068000-0x068fff:S, 0x069000-0x069fff:S, 0x06a000-0x06afff:S, 0x06b000-0x06bfff:S, 0x06c000-0x06cfff:S, 0x06d000-0x06dfff:S, 0x06e000-0x06efff:S, 0x06f000-0x06ffff:S, 0x070000-0x070fff:S, 0x071000-0x071fff:S, 0x072000-0x072fff:S, 0x073000-0x073fff:S, 0x074000-0x074fff:S, 0x075000-0x075fff:S, 0x076000-0x076fff:S, 0x077000-0x077fff:S, 0x078000-0x078fff:S, 0x079000-0x079fff:S, 0x07a000-0x07afff:S, 0x07b000-0x07bfff:S, 0x07c000-0x07cfff:S, 0x07d000-0x07dfff:S, 0x07e000-0x07efff:S, 0x07f000-0x07ffff:S Erase/write done. Verifying flash... VERIFIED. Restoring PCI config space for 00:01:0 reg 0x6d Restoring PCI config space for 00:01:0 reg 0x92 -------------- next part -------------- An HTML attachment was scrubbed... URL: From roysjosh at gmail.com Thu Nov 17 17:30:00 2011 From: roysjosh at gmail.com (Joshua Roys) Date: Thu, 17 Nov 2011 11:30:00 -0500 Subject: [flashrom] Asus A7NVM400 (A7NX8-VM400) In-Reply-To: References: <201111171412.pAHECO7v026468@mail2.student.tuwien.ac.at> Message-ID: <4EC53688.5040803@gmail.com> On 11/17/2011 11:23 AM, Svante Olofsson wrote: > I tried to write the backup.rom with flashrom -V -w backup.rom and that > seemed to work even if the rom was identical to the one already present. > To me everything looks quite good and I am considering writing the new > rom that I downloaded. What do you thing? Do you still want me to post > any more information with lspci -xxnnvvv, flashrom -V and superiotool > -deV ? > Yes, please send that information. The old version of flashrom failed because of a write protection that is in place on your system. As Stefan mentioned, newer flashrom versions will not write blocks that don't need to be written. See below: > Reading old flash chip contents... done. > Erasing and writing flash chip... Trying erase function 0... > 0x000000-0x000fff:S, 0x001000-0x001fff:S, 0x002000-0x002fff:S, [...] > 0x07e000-0x07efff:S, 0x07f000-0x07ffff:S > Erase/write done. > Verifying flash... VERIFIED. > Restoring PCI config space for 00:01:0 reg 0x6d > Restoring PCI config space for 00:01:0 reg 0x92 > The ":S" after the address ranges indicate that flashrom skipped that section. Thanks, Josh p.s. please use `lspci -vvvnnxxx' (as root) with 3 x's. Thanks. From svante at fyraess.com Thu Nov 17 17:53:30 2011 From: svante at fyraess.com (Svante Olofsson) Date: Thu, 17 Nov 2011 18:53:30 +0200 Subject: [flashrom] Asus A7NVM400 (A7NX8-VM400) In-Reply-To: <4EC53688.5040803@gmail.com> References: <201111171412.pAHECO7v026468@mail2.student.tuwien.ac.at> <4EC53688.5040803@gmail.com> Message-ID: I have attached the information.... I guess that I haven't changed the rom at all if the protection is in place :) The protection must be lifted programatically right? Nothing can be done with parameters in the bios setup? BR, --Svante -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- superiotool r3844 Probing for ALi Super I/O at 0x3f0... Failed. Returned data: id=0xffff, rev=0xff Probing for ALi Super I/O at 0x370... Failed. Returned data: id=0xffff, rev=0xff Probing for Fintek Super I/O at 0x2e... Failed. Returned data: vid=0xffff, id=0xffff Probing for Fintek Super I/O at 0x4e... Failed. Returned data: vid=0xffff, id=0xffff Probing for ITE Super I/O (init=standard) at 0x2e... Found ITE IT8712F (id=0x8712, rev=0x5) at 0x2e Register dump: idx 20 21 22 23 24 2b val 87 12 05 01 00 00 def 87 12 08 00 00 00 LDN 0x00 (Floppy) idx 30 60 61 70 74 f0 f1 val 01 03 f0 06 02 00 00 def 00 03 f0 06 02 00 00 LDN 0x01 (COM1) idx 30 60 61 70 f0 f1 f2 f3 val 01 03 f8 04 00 50 00 7f def 00 03 f8 04 00 50 00 7f LDN 0x02 (COM2) idx 30 60 61 70 f0 f1 f2 f3 val 01 02 f8 03 00 50 00 7f def 00 02 f8 03 00 50 00 7f LDN 0x03 (Parallel port) idx 30 60 61 62 63 70 74 f0 val 00 00 00 00 00 00 04 00 def 00 03 78 07 78 07 03 03 LDN 0x04 (Environment controller) idx 30 60 61 62 63 70 f0 f1 f2 f3 f4 f5 f6 val 01 0d 00 0c 00 09 00 00 00 00 a0 00 ff def 00 02 90 02 30 09 00 00 00 00 00 NA NA LDN 0x05 (Keyboard) idx 30 60 61 62 63 70 71 f0 val 01 00 60 00 64 01 02 04 def 01 00 60 00 64 01 02 08 LDN 0x06 (Mouse) idx 30 70 71 f0 val 01 0c 02 00 def 00 0c 02 00 LDN 0x07 (GPIO) idx 25 26 27 28 29 2a 2c 60 61 62 63 64 65 70 71 72 73 74 b0 b1 b2 b3 b4 b5 b8 b9 ba bb bc bd c0 c1 c2 c3 c4 c8 c9 ca cb cc e0 e1 e2 e3 e4 f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 fa fb fc fd val 2d 00 00 00 08 00 00 00 00 04 80 00 00 00 00 00 00 04 00 00 00 00 00 00 08 00 00 00 00 00 05 00 00 00 08 0d 00 00 00 08 00 00 00 00 00 00 00 00 00 00 0b 00 0d 08 02 2b 02 0e 00 def 01 00 00 40 00 00 00 00 00 00 00 00 00 00 00 00 c0 00 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00 40 00 01 00 00 40 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 NA 00 LDN 0x08 (MIDI port) idx 30 60 61 70 f0 val 00 00 00 00 00 def 00 03 00 0a 00 LDN 0x09 (Game port) idx 30 60 61 val 00 00 00 def 00 02 01 LDN 0x0a (Consumer IR) idx 30 60 61 70 f0 val 00 03 10 0b 06 def 00 03 10 0b 00 Environment controller (0x0d05) Probing for ITE Super I/O (init=it8761e) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=standard) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=legacy/it8661f) at 0x370... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=legacy/it8671f) at 0x370... Failed. Returned data: id=0xffff, rev=0xf Probing for NSC Super I/O at 0x2e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x4e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x15c... Failed. Returned data: port=0xff, port+1=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x2e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x2e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff -------------- next part -------------- 00:00.0 Host bridge [0600]: nVidia Corporation nForce2 IGP2 [10de:01e0] (rev a2) Subsystem: ASUSTeK Computer Inc. Device [1043:80c0] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR+ TAbort- Reset- FastB2B- PriDiscTmr- SecDiscTmr+ DiscTmrStat+ DiscTmrSERREn- Kernel modules: shpchp 00: de 10 6c 00 07 01 a0 40 a3 00 04 06 00 00 01 00 10: 00 00 00 00 00 00 00 00 00 01 01 40 c0 c0 80 a2 20: 70 f5 c0 fd f0 ff 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 03 06 40: 00 00 00 00 01 00 02 00 03 00 00 00 08 0b 07 00 50: 0c 0d fe 3f 0e 0f 00 00 77 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:09.0 IDE interface [0101]: nVidia Corporation nForce2 IDE [10de:0065] (rev a2) (prog-if 8a [Master SecP PriP]) Subsystem: ASUSTeK Computer Inc. Device [1043:80ad] Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- SERR- TAbort- SERR- TAbort- Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Kernel modules: shpchp 00: de 10 e8 01 07 01 20 02 a2 00 04 06 00 40 01 00 10: 00 00 00 00 00 00 00 00 00 02 02 40 d0 d0 20 22 20: d0 fd 20 fe 60 cd 50 ed 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0b 00 40: 01 00 00 00 00 00 f0 3f 20 00 00 00 00 00 00 00 50: 00 00 00 f0 00 f0 ff f3 ff ff ff ff ff ff ff ff 60: ff 40 ff 40 00 00 00 20 00 00 00 00 ff ff ff ff 70: ff ff ff ff 00 00 00 00 00 00 00 00 ff ff ff ff 80: ff ff ff ff 00 80 00 00 ab 01 00 00 ff ff ff ff 90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff a0: 1b 42 00 1f ff ff ff ff ff ff ff ff ff ff ff ff b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 01:06.0 RAID bus controller [0104]: VIA Technologies, Inc. VT6421 IDE RAID Controller [1106:3249] (rev 50) Subsystem: VIA Technologies, Inc. VT6421 IDE RAID Controller [1106:3249] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- SERR- TAbort- SERR- Capabilities: [4c] Power Management version 2 Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: cx8800 Kernel modules: cx8800 00: f1 14 00 88 16 01 90 02 05 00 00 04 10 40 80 00 10: 00 00 00 f9 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 70 00 02 94 30: 00 00 00 00 44 00 00 00 00 00 00 00 0a 01 14 37 40: 30 1f 1f 17 03 4c 00 00 00 00 00 00 01 00 22 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01:07.1 Multimedia controller [0480]: Conexant Systems, Inc. CX23880/1/2/3 PCI Video and Audio Decoder [Audio Port] [14f1:8811] (rev 05) Subsystem: Hauppauge computer works Inc. Device [0070:9402] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- References: <201111171412.pAHECO7v026468@mail2.student.tuwien.ac.at> <4EC53688.5040803@gmail.com> Message-ID: <4EC54891.8010003@gmail.com> On 11/17/2011 11:53 AM, Svante Olofsson wrote: > I have attached the information.... > > I guess that I haven't changed the rom at all if the protection is in > place :) The protection must be lifted programatically right? Nothing > can be done with parameters in the bios setup? > > BR, > --Svante > Please try the attached patch and reply with the output from `flashrom -Vw ...' Thanks, Josh -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: 0001-Board-enable-for-ASUS-A7N8X-VM-400.patch URL: From svante at fyraess.com Thu Nov 17 20:12:20 2011 From: svante at fyraess.com (Svante Olofsson) Date: Thu, 17 Nov 2011 21:12:20 +0200 Subject: [flashrom] Asus A7NVM400 (A7NX8-VM400) In-Reply-To: <4EC54891.8010003@gmail.com> References: <201111171412.pAHECO7v026468@mail2.student.tuwien.ac.at> <4EC53688.5040803@gmail.com> <4EC54891.8010003@gmail.com> Message-ID: Hi Joshua, I couldn't get the patch to compile (had also, strangely, to manually edit one part of the patch) I figured that: * - ASUS A7N8X-VM/400: NVIDIA nForce2 IGP2 + IT8712F */ static int it8712f_gpio03_raise(void) { return it87_gpio_set(3, 1); } Actually should be static int it8712f_gpio03_raise(void) { return it8712f_gpio_set(3, 1); } But when I ran it, I got the following: ... Disabling flash write protection for board "ASUS A7N8X-VM/400"... ERROR: Unsupported IT8712F GPIO line 03. FAILED! ... Maybe I have misunderstood something so I attached my board_enable.c and print.c :) BR, --Svante svante at stereo:/backup$ sudo flashrom -V -w backup.rom flashrom v0.9.4-r1395 on Linux 2.6.32-35-generic (i686), built with libpci 3.0.0, GCC 4.4.3, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 2 usecs, 278M loops per second, delay more than 10% too short (got 36% of expected delay), recalculating... 224M loops per second, delay more than 10% too short (got 30% of expected delay), recalculating... 287M loops per second, delay more than 10% too short (got 37% of expected delay), recalculating... 293M loops per second, delay more than 10% too short (got 38% of expected delay), recalculating... 282M loops per second, delay loop is unreliable, trying to continue 10 myus = 5 us, 100 myus = 36 us, 1000 myus = 353 us, 10000 myus = 9263 us, 8 myus = 5 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "Ssystem manufacturer" DMI string system-product-name: "System product name" DMI string system-version: "System version" DMI string baseboard-manufacturer: "ASUSTeK Computer INC." DMI string baseboard-product-name: "A7NVM400" DMI string baseboard-version: "Rev 2.xx" DMI string chassis-type: "Desktop" Found ITE Super I/O, ID 0x8712 on port 0x2e Found chipset "NVIDIA NForce2" with PCI ID 10de:0060. Enabling flash write... OK. This chipset supports the following protocols: Non-SPI. Super I/O ID 0x8712 is not on the list of flash capable controllers. Disabling flash write protection for board "ASUS A7N8X-VM/400"... ERROR: Unsupported IT8712F GPIO line 03. FAILED! Probing for AMD Am29F010A/B, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F002(N)BB, 256 kB: probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F002(N)BT, 256 kB: probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F016D, 2048 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F040B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F080B, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV001BB, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV001BT, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV002BB, 256 kB: probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV002BT, 256 kB: probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV004BB, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV004BT, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV008BB, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV008BT, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV040B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV081B, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC A29002B, 256 kB: probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC A29002T, 256 kB: probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC A29040B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC A49LF040A, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Atmel AT29C512, 64 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Atmel AT29C010A, 128 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Atmel AT29C020, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Atmel AT29C040A, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Atmel AT49BV512, 64 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Atmel AT49F020, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Atmel AT49F002(N), 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Atmel AT49F002(N)T, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Bright BM29F040, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for EMST F49B002UA, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Eon EN29F010, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Eon EN29F002(A)(N)B, 256 kB: probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Eon EN29F002(A)(N)T, 256 kB: probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F004BC, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F004TC, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F400BC, 512 kB: probe_m29f400bt: id1 0xff, id2 0xff Probing for Fujitsu MBM29F400TC, 512 kB: probe_m29f400bt: id1 0xff, id2 0xff Probing for Hyundai HY29F002T, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Hyundai HY29F002B, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Hyundai HY29F040A, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F001BN/BX-B, 128 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Intel 28F001BN/BX-T, 128 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Intel 28F002BC/BL/BV/BX-T, 256 kB: probe_82802ab: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F008S3/S5/SC, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F004B5/BE/BV/BX-B, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F004B5/BE/BV/BX-T, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F400BV/BX/CE/CV-B, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F400BV/BX/CE/CV-T, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F001B, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F001T, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F002B, 256 kB: probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F002T, 256 kB: probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F040, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29LV040, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for MoselVitelic V29C51000B, 64 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for MoselVitelic V29C51000T, 64 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for MoselVitelic V29C51400B, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for MoselVitelic V29C51400T, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for MoselVitelic V29LC51000, 64 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for MoselVitelic V29LC51001, 128 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for MoselVitelic V29LC51002, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for PMC Pm29F002T, 256 kB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm29F002B, 256 kB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm39LV010, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm39LV020, 256 kB: probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm39LV040, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Found PMC flash chip "Pm49FL004" (512 kB, LPC, FWH) at physical address 0xfff80000. Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST28SF040A, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST29EE010, 128 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST29LE010, 128 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST29EE020A, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST29LE020, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST39SF512, 64 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST39SF010A, 128 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST39SF020A, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST39SF040, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST39VF512, 64 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST39VF010, 128 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST39VF020, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST39VF040, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST39VF080, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF020, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST49LF020A, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST49LF040, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST49LF040B, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST49LF080A, 1024 kB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF160C, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29F002B, 256 kB: probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29F002T/NT, 256 kB: probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29F040B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29F400BB, 512 kB: probe_m29f400bt: id1 0xff, id2 0xff Probing for ST M29F400BT, 512 kB: probe_m29f400bt: id1 0xff, id2 0xff Probing for ST M29W010B, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29W040B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29W512B, 64 kB: probe_jedec_common: id1 0x3f, id2 0xae, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50LPW116, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SyncMOS/MoselVitelic {F,S,V}29C51001B, 128 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SyncMOS/MoselVitelic {F,S,V}29C51001T, 128 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SyncMOS/MoselVitelic {F,S,V}29C51002B, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SyncMOS/MoselVitelic {F,S,V}29C51002T, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SyncMOS/MoselVitelic {F,S,V}29C51004B, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SyncMOS/MoselVitelic {F,S,V}29C51004T, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SyncMOS/MoselVitelic {S,V}29C31004B, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SyncMOS/MoselVitelic {S,V}29C31004T, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for TI TMS29F002RB, 256 kB: probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for TI TMS29F002RT, 256 kB: probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W29C010(M)/W29C011A/W29EE011/W29EE012-old, 128 kB: Old Winbond W29* probe method disabled because the probing sequence puts the AMIC A49LF040A in a funky state. Use 'flashrom -c W29C010(M)/W29C011A/W29EE011/W29EE012-old' if you have a board with such a chip. Probing for Winbond W29C010(M)/W29C011A/W29EE011/W29EE012, 128 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W29C020(C)/W29C022, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W29C040/P, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W39L040, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W39V040A, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W39V040B, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W39V040C, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W39V080A, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49F002U/N, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W49F020, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W49V002A, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Flash image seems to be a legacy BIOS. Disabling coreboot-related checks. Reading old flash chip contents... done. Erasing and writing flash chip... Trying erase function 0... 0x000000-0x000fff:S, 0x001000-0x001fff:S, 0x002000-0x002fff:S, 0x003000-0x003fff:S, 0x004000-0x004fff:S, 0x005000-0x005fff:S, 0x006000-0x006fff:S, 0x007000-0x007fff:S, 0x008000-0x008fff:S, 0x009000-0x009fff:S, 0x00a000-0x00afff:S, 0x00b000-0x00bfff:S, 0x00c000-0x00cfff:S, 0x00d000-0x00dfff:S, 0x00e000-0x00efff:S, 0x00f000-0x00ffff:S, 0x010000-0x010fff:S, 0x011000-0x011fff:S, 0x012000-0x012fff:S, 0x013000-0x013fff:S, 0x014000-0x014fff:S, 0x015000-0x015fff:S, 0x016000-0x016fff:S, 0x017000-0x017fff:S, 0x018000-0x018fff:S, 0x019000-0x019fff:S, 0x01a000-0x01afff:S, 0x01b000-0x01bfff:S, 0x01c000-0x01cfff:S, 0x01d000-0x01dfff:S, 0x01e000-0x01efff:S, 0x01f000-0x01ffff:S, 0x020000-0x020fff:S, 0x021000-0x021fff:S, 0x022000-0x022fff:S, 0x023000-0x023fff:S, 0x024000-0x024fff:S, 0x025000-0x025fff:S, 0x026000-0x026fff:S, 0x027000-0x027fff:S, 0x028000-0x028fff:S, 0x029000-0x029fff:S, 0x02a000-0x02afff:S, 0x02b000-0x02bfff:S, 0x02c000-0x02cfff:S, 0x02d000-0x02dfff:S, 0x02e000-0x02efff:S, 0x02f000-0x02ffff:S, 0x030000-0x030fff:S, 0x031000-0x031fff:S, 0x032000-0x032fff:S, 0x033000-0x033fff:S, 0x034000-0x034fff:S, 0x035000-0x035fff:S, 0x036000-0x036fff:S, 0x037000-0x037fff:S, 0x038000-0x038fff:S, 0x039000-0x039fff:S, 0x03a000-0x03afff:S, 0x03b000-0x03bfff:S, 0x03c000-0x03cfff:S, 0x03d000-0x03dfff:S, 0x03e000-0x03efff:S, 0x03f000-0x03ffff:S, 0x040000-0x040fff:S, 0x041000-0x041fff:S, 0x042000-0x042fff:S, 0x043000-0x043fff:S, 0x044000-0x044fff:S, 0x045000-0x045fff:S, 0x046000-0x046fff:S, 0x047000-0x047fff:S, 0x048000-0x048fff:S, 0x049000-0x049fff:S, 0x04a000-0x04afff:S, 0x04b000-0x04bfff:S, 0x04c000-0x04cfff:S, 0x04d000-0x04dfff:S, 0x04e000-0x04efff:S, 0x04f000-0x04ffff:S, 0x050000-0x050fff:S, 0x051000-0x051fff:S, 0x052000-0x052fff:S, 0x053000-0x053fff:S, 0x054000-0x054fff:S, 0x055000-0x055fff:S, 0x056000-0x056fff:S, 0x057000-0x057fff:S, 0x058000-0x058fff:S, 0x059000-0x059fff:S, 0x05a000-0x05afff:S, 0x05b000-0x05bfff:S, 0x05c000-0x05cfff:S, 0x05d000-0x05dfff:S, 0x05e000-0x05efff:S, 0x05f000-0x05ffff:S, 0x060000-0x060fff:S, 0x061000-0x061fff:S, 0x062000-0x062fff:S, 0x063000-0x063fff:S, 0x064000-0x064fff:S, 0x065000-0x065fff:S, 0x066000-0x066fff:S, 0x067000-0x067fff:S, 0x068000-0x068fff:S, 0x069000-0x069fff:S, 0x06a000-0x06afff:S, 0x06b000-0x06bfff:S, 0x06c000-0x06cfff:S, 0x06d000-0x06dfff:S, 0x06e000-0x06efff:S, 0x06f000-0x06ffff:S, 0x070000-0x070fff:S, 0x071000-0x071fff:S, 0x072000-0x072fff:S, 0x073000-0x073fff:S, 0x074000-0x074fff:S, 0x075000-0x075fff:S, 0x076000-0x076fff:S, 0x077000-0x077fff:S, 0x078000-0x078fff:S, 0x079000-0x079fff:S, 0x07a000-0x07afff:S, 0x07b000-0x07bfff:S, 0x07c000-0x07cfff:S, 0x07d000-0x07dfff:S, 0x07e000-0x07efff:S, 0x07f000-0x07ffff:S Erase/write done. Verifying flash... VERIFIED. Restoring PCI config space for 00:01:0 reg 0x6d Restoring PCI config space for 00:01:0 reg 0x92 svante at stereo:/backup$ -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: board_enable.c Type: text/x-csrc Size: 74174 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: print.c Type: text/x-csrc Size: 51357 bytes Desc: not available URL: From roysjosh at gmail.com Thu Nov 17 21:22:26 2011 From: roysjosh at gmail.com (Joshua Roys) Date: Thu, 17 Nov 2011 15:22:26 -0500 Subject: [flashrom] Asus A7NVM400 (A7NX8-VM400) In-Reply-To: References: <201111171412.pAHECO7v026468@mail2.student.tuwien.ac.at> <4EC53688.5040803@gmail.com> <4EC54891.8010003@gmail.com> Message-ID: <4EC56D02.9010107@gmail.com> On 11/17/2011 02:12 PM, Svante Olofsson wrote: > Hi Joshua, > > I couldn't get the patch to compile (had also, strangely, to manually > edit one part of the patch) > Hello, Sorry- you'll need to apply that patch to the SVN version of flashrom. My patches depend on a fairly recent change. Alternatively, if you want to avoid checking out the svn copy, change: return it8712f_gpio_set(3, 1); to return it8712f_gpio_set(13, 1); Otherwise, apply these 2 patches to svn (and ignore the previous patch). Thanks, Josh -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: 0001-Board-enable-for-ASUS-A7N8X-VM-400.patch URL: -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: 0002-Fix-it87_gpio_set.patch URL: From roysjosh at gmail.com Thu Nov 17 21:27:02 2011 From: roysjosh at gmail.com (Joshua Roys) Date: Thu, 17 Nov 2011 15:27:02 -0500 Subject: [flashrom] Asus A7NVM400 (A7NX8-VM400) In-Reply-To: References: <201111171412.pAHECO7v026468@mail2.student.tuwien.ac.at> <4EC53688.5040803@gmail.com> <4EC54891.8010003@gmail.com> Message-ID: <4EC56E16.9070508@gmail.com> On 11/17/2011 02:12 PM, Svante Olofsson wrote: > Hi Joshua, > Hello again, Sent the last email a little too quickly. Ignore the 2nd patch in that email also (if you decide to use svn). I tried to fix a non-existent bug! Thanks, Josh From svante at fyraess.com Thu Nov 17 21:46:03 2011 From: svante at fyraess.com (Svante Olofsson) Date: Thu, 17 Nov 2011 22:46:03 +0200 Subject: [flashrom] Asus A7NVM400 (A7NX8-VM400) In-Reply-To: <4EC56D02.9010107@gmail.com> References: <201111171412.pAHECO7v026468@mail2.student.tuwien.ac.at> <4EC53688.5040803@gmail.com> <4EC54891.8010003@gmail.com> <4EC56D02.9010107@gmail.com> Message-ID: Hi, I applied the patches to SVN, and tried it out, but still no cigar I'm afraid... Is there anything else that I can provide you with? svante at stereo:/backup/flashrom$ sudo flashrom -V -w ../backup.rom flashrom v0.9.4-r1468 on Linux 2.6.32-35-generic (i686), built with libpci 3.0.0, GCC 4.4.3, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 723M loops per second, 10 myus = 11 us, 100 myus = 92 us, 1000 myus = 1194 us, 10000 myus = 9652 us, 4 myus = 5 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "Ssystem manufacturer" DMI string system-product-name: "System product name" DMI string system-version: "System version" DMI string baseboard-manufacturer: "ASUSTeK Computer INC." DMI string baseboard-product-name: "A7NVM400" DMI string baseboard-version: "Rev 2.xx" DMI string chassis-type: "Desktop" Found ITE Super I/O, ID 0x8712 on port 0x2e Found chipset "NVIDIA NForce2" with PCI ID 10de:0060. Enabling flash write... OK. Super I/O ID 0x8712 is not on the list of flash capable controllers. Disabling flash write protection for board "ASUS A7N8X-VM/400"... ERROR: IT8712 does not allow setting GPIO13. FAILED! This programmer supports the following protocols: Non-SPI. Probing for AMD Am29F010A/B, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F002(N)BB, 256 kB: probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F002(N)BT, 256 kB: probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F016D, 2048 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F040B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F080B, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV001BB, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV001BT, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV002BB, 256 kB: probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV002BT, 256 kB: probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV004BB, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV004BT, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV008BB, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV008BT, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV040B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV081B, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC A29002B, 256 kB: probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC A29002T, 256 kB: probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC A29040B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC A49LF040A, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Atmel AT29C512, 64 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Atmel AT29C010A, 128 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Atmel AT29C020, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Atmel AT29C040A, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Atmel AT49BV512, 64 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Atmel AT49F020, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Atmel AT49F002(N), 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Atmel AT49F002(N)T, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Atmel AT49LH002, 256 kB: probe_82802ab: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Catalyst CAT28F512, 64 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Bright BM29F040, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for EMST F49B002UA, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Eon EN29F010, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Eon EN29F002(A)(N)B, 256 kB: probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Eon EN29F002(A)(N)T, 256 kB: probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F004BC, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F004TC, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F400BC, 512 kB: probe_m29f400bt: id1 0xff, id2 0xff Probing for Fujitsu MBM29F400TC, 512 kB: probe_m29f400bt: id1 0xff, id2 0xff Probing for Hyundai HY29F002T, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Hyundai HY29F002B, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Hyundai HY29F040A, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F001BN/BX-B, 128 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Intel 28F001BN/BX-T, 128 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Intel 28F002BC/BL/BV/BX-T, 256 kB: probe_82802ab: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F008S3/S5/SC, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F004B5/BE/BV/BX-B, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F004B5/BE/BV/BX-T, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F400BV/BX/CE/CV-B, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F400BV/BX/CE/CV-T, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F001B, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F001T, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F002(N)B, 256 kB: probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F002(N)T, 256 kB: probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F040, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29LV040, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for MoselVitelic V29C51000B, 64 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for MoselVitelic V29C51000T, 64 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for MoselVitelic V29C51400B, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for MoselVitelic V29C51400T, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for MoselVitelic V29LC51000, 64 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for MoselVitelic V29LC51001, 128 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for MoselVitelic V29LC51002, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for PMC Pm29F002T, 256 kB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm29F002B, 256 kB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm39LV010, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm39LV020, 256 kB: probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm39LV040, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Found PMC flash chip "Pm49FL004" (512 kB, LPC, FWH) at physical address 0xfff80000. Probing for Sharp LH28F008BJT-BTLZ1, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST28SF040A, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST29EE010, 128 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST29LE010, 128 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST29EE020A, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST29LE020, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST39SF512, 64 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST39SF010A, 128 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST39SF020A, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST39SF040, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST39VF512, 64 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST39VF010, 128 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST39VF020, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST39VF040, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST39VF080, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF020, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST49LF020A, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST49LF040, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST49LF040B, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST49LF080A, 1024 kB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF160C, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29F002B, 256 kB: probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29F002T/NT, 256 kB: probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29F040B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29F400BB, 512 kB: probe_m29f400bt: id1 0xff, id2 0xff Probing for ST M29F400BT, 512 kB: probe_m29f400bt: id1 0xff, id2 0xff Probing for ST M29W010B, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29W040B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29W512B, 64 kB: probe_jedec_common: id1 0x3f, id2 0xae, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50LPW116, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SyncMOS/MoselVitelic {F,S,V}29C51001B, 128 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SyncMOS/MoselVitelic {F,S,V}29C51001T, 128 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SyncMOS/MoselVitelic {F,S,V}29C51002B, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SyncMOS/MoselVitelic {F,S,V}29C51002T, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SyncMOS/MoselVitelic {F,S,V}29C51004B, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SyncMOS/MoselVitelic {F,S,V}29C51004T, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SyncMOS/MoselVitelic {S,V}29C31004B, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SyncMOS/MoselVitelic {S,V}29C31004T, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for TI TMS29F002RB, 256 kB: probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for TI TMS29F002RT, 256 kB: probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W29C010(M)/W29C011A/W29EE011/W29EE012-old, 128 kB: Old Winbond W29* probe method disabled because the probing sequence puts the AMIC A49LF040A in a funky state. Use 'flashrom -c W29C010(M)/W29C011A/W29EE011/W29EE012-old' if you have a board with such a chip. Probing for Winbond W29C010(M)/W29C011A/W29EE011/W29EE012, 128 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W29C020(C)/W29C022, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W29C040/P, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W39L040, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W39V040A, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W39V040B, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W39V040C, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W39V080A, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49F002U/N, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W49F020, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W49V002A, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Found PMC flash chip "Pm49FL004" (512 kB, LPC, FWH). Flash image seems to be a legacy BIOS. Disabling coreboot-related checks. Reading old flash chip contents... done. Erasing and writing flash chip... Trying erase function 0... 0x000000-0x000fff:S, 0x001000-0x001fff:S, 0x002000-0x002fff:S, 0x003000-0x003fff:S, 0x004000-0x004fff:S, 0x005000-0x005fff:S, 0x006000-0x006fff:S, 0x007000-0x007fff:S, 0x008000-0x008fff:S, 0x009000-0x009fff:S, 0x00a000-0x00afff:S, 0x00b000-0x00bfff:S, 0x00c000-0x00cfff:S, 0x00d000-0x00dfff:S, 0x00e000-0x00efff:S, 0x00f000-0x00ffff:S, 0x010000-0x010fff:S, 0x011000-0x011fff:S, 0x012000-0x012fff:S, 0x013000-0x013fff:S, 0x014000-0x014fff:S, 0x015000-0x015fff:S, 0x016000-0x016fff:S, 0x017000-0x017fff:S, 0x018000-0x018fff:S, 0x019000-0x019fff:S, 0x01a000-0x01afff:S, 0x01b000-0x01bfff:S, 0x01c000-0x01cfff:S, 0x01d000-0x01dfff:S, 0x01e000-0x01efff:S, 0x01f000-0x01ffff:S, 0x020000-0x020fff:S, 0x021000-0x021fff:S, 0x022000-0x022fff:S, 0x023000-0x023fff:S, 0x024000-0x024fff:S, 0x025000-0x025fff:S, 0x026000-0x026fff:S, 0x027000-0x027fff:S, 0x028000-0x028fff:S, 0x029000-0x029fff:S, 0x02a000-0x02afff:S, 0x02b000-0x02bfff:S, 0x02c000-0x02cfff:S, 0x02d000-0x02dfff:S, 0x02e000-0x02efff:S, 0x02f000-0x02ffff:S, 0x030000-0x030fff:S, 0x031000-0x031fff:S, 0x032000-0x032fff:S, 0x033000-0x033fff:S, 0x034000-0x034fff:S, 0x035000-0x035fff:S, 0x036000-0x036fff:S, 0x037000-0x037fff:S, 0x038000-0x038fff:S, 0x039000-0x039fff:S, 0x03a000-0x03afff:S, 0x03b000-0x03bfff:S, 0x03c000-0x03cfff:S, 0x03d000-0x03dfff:S, 0x03e000-0x03efff:S, 0x03f000-0x03ffff:S, 0x040000-0x040fff:S, 0x041000-0x041fff:S, 0x042000-0x042fff:S, 0x043000-0x043fff:S, 0x044000-0x044fff:S, 0x045000-0x045fff:S, 0x046000-0x046fff:S, 0x047000-0x047fff:S, 0x048000-0x048fff:S, 0x049000-0x049fff:S, 0x04a000-0x04afff:S, 0x04b000-0x04bfff:S, 0x04c000-0x04cfff:S, 0x04d000-0x04dfff:S, 0x04e000-0x04efff:S, 0x04f000-0x04ffff:S, 0x050000-0x050fff:S, 0x051000-0x051fff:S, 0x052000-0x052fff:S, 0x053000-0x053fff:S, 0x054000-0x054fff:S, 0x055000-0x055fff:S, 0x056000-0x056fff:S, 0x057000-0x057fff:S, 0x058000-0x058fff:S, 0x059000-0x059fff:S, 0x05a000-0x05afff:S, 0x05b000-0x05bfff:S, 0x05c000-0x05cfff:S, 0x05d000-0x05dfff:S, 0x05e000-0x05efff:S, 0x05f000-0x05ffff:S, 0x060000-0x060fff:S, 0x061000-0x061fff:S, 0x062000-0x062fff:S, 0x063000-0x063fff:S, 0x064000-0x064fff:S, 0x065000-0x065fff:S, 0x066000-0x066fff:S, 0x067000-0x067fff:S, 0x068000-0x068fff:S, 0x069000-0x069fff:S, 0x06a000-0x06afff:S, 0x06b000-0x06bfff:S, 0x06c000-0x06cfff:S, 0x06d000-0x06dfff:S, 0x06e000-0x06efff:S, 0x06f000-0x06ffff:S, 0x070000-0x070fff:S, 0x071000-0x071fff:S, 0x072000-0x072fff:S, 0x073000-0x073fff:S, 0x074000-0x074fff:S, 0x075000-0x075fff:S, 0x076000-0x076fff:S, 0x077000-0x077fff:S, 0x078000-0x078fff:S, 0x079000-0x079fff:S, 0x07a000-0x07afff:S, 0x07b000-0x07bfff:S, 0x07c000-0x07cfff:S, 0x07d000-0x07dfff:S, 0x07e000-0x07efff:S, 0x07f000-0x07ffff:S Erase/write done. Verifying flash... VERIFIED. Restoring PCI config space for 00:01:0 reg 0x6d Restoring PCI config space for 00:01:0 reg 0x92 svante at stereo:/backup/flashrom$ 2011/11/17 Joshua Roys > On 11/17/2011 02:12 PM, Svante Olofsson wrote: > >> Hi Joshua, >> >> I couldn't get the patch to compile (had also, strangely, to manually >> edit one part of the patch) >> >> > Hello, > > Sorry- you'll need to apply that patch to the SVN version of flashrom. My > patches depend on a fairly recent change. Alternatively, if you want to > avoid checking out the svn copy, change: > return it8712f_gpio_set(3, 1); > to > return it8712f_gpio_set(13, 1); > > Otherwise, apply these 2 patches to svn (and ignore the previous patch). > > Thanks, > > Josh > > -------------- next part -------------- An HTML attachment was scrubbed... URL: From svante at fyraess.com Thu Nov 17 22:24:01 2011 From: svante at fyraess.com (Svante Olofsson) Date: Thu, 17 Nov 2011 23:24:01 +0200 Subject: [flashrom] Asus A7NVM400 (A7NX8-VM400) In-Reply-To: <4EC56E16.9070508@gmail.com> References: <201111171412.pAHECO7v026468@mail2.student.tuwien.ac.at> <4EC53688.5040803@gmail.com> <4EC54891.8010003@gmail.com> <4EC56E16.9070508@gmail.com> Message-ID: Hi, Yeah, that happens sometimes :) I tried it again and everything went fine with the backup.rom, ie. it did nothing, but it did it ok. Unfortunately, it failed on erase when I tried to write a newer rom that I have downloaded from Asus... Let me know if there is anything else that I can do... Thank you for the help so far anyway! svante at stereo:/backup$ sudo flashrom -V -w A7NVM400-ASUS-1004.009.rom flashrom v0.9.4-r1468 on Linux 2.6.32-35-generic (i686), built with libpci 3.0.0, GCC 4.4.3, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 740M loops per second, 10 myus = 11 us, 100 myus = 94 us, 1000 myus = 1185 us, 10000 myus = 10217 us, 4 myus = 5 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "Ssystem manufacturer" DMI string system-product-name: "System product name" DMI string system-version: "System version" DMI string baseboard-manufacturer: "ASUSTeK Computer INC." DMI string baseboard-product-name: "A7NVM400" DMI string baseboard-version: "Rev 2.xx" DMI string chassis-type: "Desktop" Found ITE Super I/O, ID 0x8712 on port 0x2e Found chipset "NVIDIA NForce2" with PCI ID 10de:0060. Enabling flash write... OK. Super I/O ID 0x8712 is not on the list of flash capable controllers. Disabling flash write protection for board "ASUS A7N8X-VM/400"... Using IT87 GPIO base 0x0480 OK. This programmer supports the following protocols: Non-SPI. Probing for AMD Am29F010A/B, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F002(N)BB, 256 kB: probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F002(N)BT, 256 kB: probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F016D, 2048 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F040B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F080B, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV001BB, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV001BT, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV002BB, 256 kB: probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV002BT, 256 kB: probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV004BB, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV004BT, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV008BB, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV008BT, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV040B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV081B, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC A29002B, 256 kB: probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC A29002T, 256 kB: probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC A29040B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC A49LF040A, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Atmel AT29C512, 64 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Atmel AT29C010A, 128 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Atmel AT29C020, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Atmel AT29C040A, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Atmel AT49BV512, 64 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Atmel AT49F020, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Atmel AT49F002(N), 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Atmel AT49F002(N)T, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Atmel AT49LH002, 256 kB: probe_82802ab: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Catalyst CAT28F512, 64 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Bright BM29F040, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for EMST F49B002UA, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Eon EN29F010, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Eon EN29F002(A)(N)B, 256 kB: probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Eon EN29F002(A)(N)T, 256 kB: probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F004BC, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F004TC, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F400BC, 512 kB: probe_m29f400bt: id1 0xff, id2 0xff Probing for Fujitsu MBM29F400TC, 512 kB: probe_m29f400bt: id1 0xff, id2 0xff Probing for Hyundai HY29F002T, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Hyundai HY29F002B, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Hyundai HY29F040A, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F001BN/BX-B, 128 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Intel 28F001BN/BX-T, 128 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Intel 28F002BC/BL/BV/BX-T, 256 kB: probe_82802ab: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F008S3/S5/SC, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F004B5/BE/BV/BX-B, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F004B5/BE/BV/BX-T, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F400BV/BX/CE/CV-B, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F400BV/BX/CE/CV-T, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F001B, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F001T, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F002(N)B, 256 kB: probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F002(N)T, 256 kB: probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F040, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29LV040, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for MoselVitelic V29C51000B, 64 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for MoselVitelic V29C51000T, 64 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for MoselVitelic V29C51400B, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for MoselVitelic V29C51400T, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for MoselVitelic V29LC51000, 64 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for MoselVitelic V29LC51001, 128 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for MoselVitelic V29LC51002, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for PMC Pm29F002T, 256 kB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm29F002B, 256 kB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm39LV010, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm39LV020, 256 kB: probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm39LV040, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Found PMC flash chip "Pm49FL004" (512 kB, LPC, FWH) at physical address 0xfff80000. Probing for Sharp LH28F008BJT-BTLZ1, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST28SF040A, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST29EE010, 128 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST29LE010, 128 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST29EE020A, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST29LE020, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST39SF512, 64 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST39SF010A, 128 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST39SF020A, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST39SF040, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST39VF512, 64 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST39VF010, 128 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST39VF020, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST39VF040, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST39VF080, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF020, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST49LF020A, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST49LF040, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST49LF040B, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST49LF080A, 1024 kB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF160C, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29F002B, 256 kB: probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29F002T/NT, 256 kB: probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29F040B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29F400BB, 512 kB: probe_m29f400bt: id1 0xff, id2 0xff Probing for ST M29F400BT, 512 kB: probe_m29f400bt: id1 0xff, id2 0xff Probing for ST M29W010B, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29W040B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29W512B, 64 kB: probe_jedec_common: id1 0x3f, id2 0xae, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50LPW116, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SyncMOS/MoselVitelic {F,S,V}29C51001B, 128 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SyncMOS/MoselVitelic {F,S,V}29C51001T, 128 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SyncMOS/MoselVitelic {F,S,V}29C51002B, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SyncMOS/MoselVitelic {F,S,V}29C51002T, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SyncMOS/MoselVitelic {F,S,V}29C51004B, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SyncMOS/MoselVitelic {F,S,V}29C51004T, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SyncMOS/MoselVitelic {S,V}29C31004B, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SyncMOS/MoselVitelic {S,V}29C31004T, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for TI TMS29F002RB, 256 kB: probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for TI TMS29F002RT, 256 kB: probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W29C010(M)/W29C011A/W29EE011/W29EE012-old, 128 kB: Old Winbond W29* probe method disabled because the probing sequence puts the AMIC A49LF040A in a funky state. Use 'flashrom -c W29C010(M)/W29C011A/W29EE011/W29EE012-old' if you have a board with such a chip. Probing for Winbond W29C010(M)/W29C011A/W29EE011/W29EE012, 128 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W29C020(C)/W29C022, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W29C040/P, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W39L040, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W39V040A, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W39V040B, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W39V040C, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W39V080A, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49F002U/N, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W49F020, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W49V002A, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Found PMC flash chip "Pm49FL004" (512 kB, LPC, FWH). Flash image seems to be a legacy BIOS. Disabling coreboot-related checks. Reading old flash chip contents... done. Erasing and writing flash chip... Trying erase function 0... 0x000000-0x000fff:EERASE FAILED at 0x00000008! Expected=0xff, Read=0x4c, failed byte count from 0x00000000-0x00000fff: 0xfdc ERASE FAILED! Reading current flash chip contents... done. Looking for another erase function. Trying erase function 1... 0x000000-0x00ffff:EERASE FAILED at 0x00000008! Expected=0xff, Read=0x4c, failed byte count from 0x00000000-0x0000ffff: 0xfed5 ERASE FAILED! Reading current flash chip contents... done. Looking for another erase function. Trying erase function 2... 0x000000-0x07ffff:EERASE FAILED at 0x00000008! Expected=0xff, Read=0x4c, failed byte count from 0x00000000-0x0007ffff: 0x687be ERASE FAILED! Looking for another erase function. No usable erase functions left. FAILED! Uh oh. Erase/write failed. Checking if anything changed. Good. It seems nothing was changed. Writing to the flash chip apparently didn't do anything. This means we have to add special support for your board, programmer or flash chip. Please report this on IRC at irc.freenode.net (channel #flashrom) or mail flashrom at flashrom.org! ------------------------------------------------------------------------------- You may now reboot or simply leave the machine running. Restoring PCI config space for 00:01:0 reg 0x6d Restoring PCI config space for 00:01:0 reg 0x92 svante at stereo:/backup$ 2011/11/17 Joshua Roys > On 11/17/2011 02:12 PM, Svante Olofsson wrote: > >> Hi Joshua, >> >> > Hello again, > > Sent the last email a little too quickly. Ignore the 2nd patch in that > email also (if you decide to use svn). I tried to fix a non-existent bug! > > Thanks, > > Josh > > -------------- next part -------------- An HTML attachment was scrubbed... URL: From roysjosh at gmail.com Thu Nov 17 22:43:45 2011 From: roysjosh at gmail.com (Joshua Roys) Date: Thu, 17 Nov 2011 16:43:45 -0500 Subject: [flashrom] Asus A7NVM400 (A7NX8-VM400) In-Reply-To: References: <201111171412.pAHECO7v026468@mail2.student.tuwien.ac.at> <4EC53688.5040803@gmail.com> <4EC54891.8010003@gmail.com> <4EC56E16.9070508@gmail.com> Message-ID: <4EC58011.9090305@gmail.com> On 11/17/2011 04:24 PM, Svante Olofsson wrote: > Hi, Hello again. Very sorry- today is not my day. Off by one bug. Please change 13 to 12. Thanks, Josh -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: 0001-Board-enable-for-ASUS-A7N8X-VM-400.patch URL: From svante at fyraess.com Thu Nov 17 23:11:27 2011 From: svante at fyraess.com (Svante Olofsson) Date: Fri, 18 Nov 2011 00:11:27 +0200 Subject: [flashrom] Asus A7NVM400 (A7NX8-VM400) In-Reply-To: <4EC58011.9090305@gmail.com> References: <201111171412.pAHECO7v026468@mail2.student.tuwien.ac.at> <4EC53688.5040803@gmail.com> <4EC54891.8010003@gmail.com> <4EC56E16.9070508@gmail.com> <4EC58011.9090305@gmail.com> Message-ID: Hi, Now I think it works! The rom read is the same as the one that I wrote, so the write seems to have been successful :) Do you think it is ok to reboot and see if it starts again? Thank you very much for your patients and time! Best regards, --Svante svante at stereo:/backup$ sudo flashrom -V -w A7NVM400-ASUS-1004.009.rom flashrom v0.9.4-r1468 on Linux 2.6.32-35-generic (i686), built with libpci 3.0.0, GCC 4.4.3, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 2 usecs, 751M loops per second, 10 myus = 11 us, 100 myus = 95 us, 1000 myus = 937 us, 10000 myus = 11899 us, 8 myus = 10 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "Ssystem manufacturer" DMI string system-product-name: "System product name" DMI string system-version: "System version" DMI string baseboard-manufacturer: "ASUSTeK Computer INC." DMI string baseboard-product-name: "A7NVM400" DMI string baseboard-version: "Rev 2.xx" DMI string chassis-type: "Desktop" Found ITE Super I/O, ID 0x8712 on port 0x2e Found chipset "NVIDIA NForce2" with PCI ID 10de:0060. Enabling flash write... OK. Super I/O ID 0x8712 is not on the list of flash capable controllers. Disabling flash write protection for board "ASUS A7N8X-VM/400"... Using IT87 GPIO base 0x0480 OK. This programmer supports the following protocols: Non-SPI. Probing for AMD Am29F010A/B, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F002(N)BB, 256 kB: probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F002(N)BT, 256 kB: probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F016D, 2048 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F040B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F080B, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV001BB, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV001BT, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV002BB, 256 kB: probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV002BT, 256 kB: probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV004BB, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV004BT, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV008BB, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV008BT, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV040B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV081B, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC A29002B, 256 kB: probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC A29002T, 256 kB: probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC A29040B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC A49LF040A, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Atmel AT29C512, 64 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Atmel AT29C010A, 128 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Atmel AT29C020, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Atmel AT29C040A, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Atmel AT49BV512, 64 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Atmel AT49F020, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Atmel AT49F002(N), 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Atmel AT49F002(N)T, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Atmel AT49LH002, 256 kB: probe_82802ab: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Catalyst CAT28F512, 64 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Bright BM29F040, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for EMST F49B002UA, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Eon EN29F010, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Eon EN29F002(A)(N)B, 256 kB: probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Eon EN29F002(A)(N)T, 256 kB: probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F004BC, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F004TC, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F400BC, 512 kB: probe_m29f400bt: id1 0xff, id2 0xff Probing for Fujitsu MBM29F400TC, 512 kB: probe_m29f400bt: id1 0xff, id2 0xff Probing for Hyundai HY29F002T, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Hyundai HY29F002B, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Hyundai HY29F040A, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F001BN/BX-B, 128 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Intel 28F001BN/BX-T, 128 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Intel 28F002BC/BL/BV/BX-T, 256 kB: probe_82802ab: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F008S3/S5/SC, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F004B5/BE/BV/BX-B, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F004B5/BE/BV/BX-T, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F400BV/BX/CE/CV-B, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F400BV/BX/CE/CV-T, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F001B, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F001T, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F002(N)B, 256 kB: probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F002(N)T, 256 kB: probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F040, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29LV040, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for MoselVitelic V29C51000B, 64 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for MoselVitelic V29C51000T, 64 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for MoselVitelic V29C51400B, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for MoselVitelic V29C51400T, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for MoselVitelic V29LC51000, 64 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for MoselVitelic V29LC51001, 128 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for MoselVitelic V29LC51002, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for PMC Pm29F002T, 256 kB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm29F002B, 256 kB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm39LV010, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm39LV020, 256 kB: probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm39LV040, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Found PMC flash chip "Pm49FL004" (512 kB, LPC, FWH) at physical address 0xfff80000. Probing for Sharp LH28F008BJT-BTLZ1, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST28SF040A, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST29EE010, 128 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST29LE010, 128 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST29EE020A, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST29LE020, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST39SF512, 64 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST39SF010A, 128 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST39SF020A, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST39SF040, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST39VF512, 64 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST39VF010, 128 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST39VF020, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST39VF040, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST39VF080, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF020, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST49LF020A, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST49LF040, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST49LF040B, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST49LF080A, 1024 kB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF160C, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29F002B, 256 kB: probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29F002T/NT, 256 kB: probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29F040B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29F400BB, 512 kB: probe_m29f400bt: id1 0xff, id2 0xff Probing for ST M29F400BT, 512 kB: probe_m29f400bt: id1 0xff, id2 0xff Probing for ST M29W010B, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29W040B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29W512B, 64 kB: probe_jedec_common: id1 0x3f, id2 0xae, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50LPW116, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SyncMOS/MoselVitelic {F,S,V}29C51001B, 128 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SyncMOS/MoselVitelic {F,S,V}29C51001T, 128 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SyncMOS/MoselVitelic {F,S,V}29C51002B, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SyncMOS/MoselVitelic {F,S,V}29C51002T, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SyncMOS/MoselVitelic {F,S,V}29C51004B, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SyncMOS/MoselVitelic {F,S,V}29C51004T, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SyncMOS/MoselVitelic {S,V}29C31004B, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SyncMOS/MoselVitelic {S,V}29C31004T, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for TI TMS29F002RB, 256 kB: probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for TI TMS29F002RT, 256 kB: probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W29C010(M)/W29C011A/W29EE011/W29EE012-old, 128 kB: Old Winbond W29* probe method disabled because the probing sequence puts the AMIC A49LF040A in a funky state. Use 'flashrom -c W29C010(M)/W29C011A/W29EE011/W29EE012-old' if you have a board with such a chip. Probing for Winbond W29C010(M)/W29C011A/W29EE011/W29EE012, 128 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W29C020(C)/W29C022, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W29C040/P, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W39L040, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W39V040A, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W39V040B, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W39V040C, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W39V080A, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49F002U/N, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W49F020, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W49V002A, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Found PMC flash chip "Pm49FL004" (512 kB, LPC, FWH). Flash image seems to be a legacy BIOS. Disabling coreboot-related checks. Reading old flash chip contents... done. Erasing and writing flash chip... Trying erase function 0... 0x000000-0x000fff:EW, 0x001000-0x001fff:EW, 0x002000-0x002fff:EW, 0x003000-0x003fff:EW, 0x004000-0x004fff:EW, 0x005000-0x005fff:EW, 0x006000-0x006fff:EW, 0x007000-0x007fff:EW, 0x008000-0x008fff:EW, 0x009000-0x009fff:EW, 0x00a000-0x00afff:EW, 0x00b000-0x00bfff:EW, 0x00c000-0x00cfff:EW, 0x00d000-0x00dfff:EW, 0x00e000-0x00efff:EW, 0x00f000-0x00ffff:EW, 0x010000-0x010fff:EW, 0x011000-0x011fff:EW, 0x012000-0x012fff:EW, 0x013000-0x013fff:EW, 0x014000-0x014fff:EW, 0x015000-0x015fff:EW, 0x016000-0x016fff:EW, 0x017000-0x017fff:EW, 0x018000-0x018fff:EW, 0x019000-0x019fff:EW, 0x01a000-0x01afff:EW, 0x01b000-0x01bfff:EW, 0x01c000-0x01cfff:EW, 0x01d000-0x01dfff:EW, 0x01e000-0x01efff:EW, 0x01f000-0x01ffff:EW, 0x020000-0x020fff:EW, 0x021000-0x021fff:EW, 0x022000-0x022fff:EW, 0x023000-0x023fff:EW, 0x024000-0x024fff:EW, 0x025000-0x025fff:EW, 0x026000-0x026fff:EW, 0x027000-0x027fff:EW, 0x028000-0x028fff:EW, 0x029000-0x029fff:EW, 0x02a000-0x02afff:EW, 0x02b000-0x02bfff:EW, 0x02c000-0x02cfff:EW, 0x02d000-0x02dfff:EW, 0x02e000-0x02efff:EW, 0x02f000-0x02ffff:EW, 0x030000-0x030fff:EW, 0x031000-0x031fff:EW, 0x032000-0x032fff:EW, 0x033000-0x033fff:EW, 0x034000-0x034fff:EW, 0x035000-0x035fff:EW, 0x036000-0x036fff:EW, 0x037000-0x037fff:EW, 0x038000-0x038fff:EW, 0x039000-0x039fff:EW, 0x03a000-0x03afff:EW, 0x03b000-0x03bfff:EW, 0x03c000-0x03cfff:EW, 0x03d000-0x03dfff:EW, 0x03e000-0x03efff:EW, 0x03f000-0x03ffff:S, 0x040000-0x040fff:EW, 0x041000-0x041fff:EW, 0x042000-0x042fff:S, 0x043000-0x043fff:S, 0x044000-0x044fff:S, 0x045000-0x045fff:S, 0x046000-0x046fff:S, 0x047000-0x047fff:S, 0x048000-0x048fff:S, 0x049000-0x049fff:S, 0x04a000-0x04afff:S, 0x04b000-0x04bfff:S, 0x04c000-0x04cfff:S, 0x04d000-0x04dfff:S, 0x04e000-0x04efff:S, 0x04f000-0x04ffff:S, 0x050000-0x050fff:S, 0x051000-0x051fff:S, 0x052000-0x052fff:S, 0x053000-0x053fff:S, 0x054000-0x054fff:S, 0x055000-0x055fff:S, 0x056000-0x056fff:EW, 0x057000-0x057fff:EW, 0x058000-0x058fff:EW, 0x059000-0x059fff:EW, 0x05a000-0x05afff:EW, 0x05b000-0x05bfff:S, 0x05c000-0x05cfff:S, 0x05d000-0x05dfff:S, 0x05e000-0x05efff:S, 0x05f000-0x05ffff:EW, 0x060000-0x060fff:S, 0x061000-0x061fff:S, 0x062000-0x062fff:S, 0x063000-0x063fff:S, 0x064000-0x064fff:S, 0x065000-0x065fff:S, 0x066000-0x066fff:S, 0x067000-0x067fff:S, 0x068000-0x068fff:S, 0x069000-0x069fff:S, 0x06a000-0x06afff:S, 0x06b000-0x06bfff:S, 0x06c000-0x06cfff:E, 0x06d000-0x06dfff:E, 0x06e000-0x06efff:E, 0x06f000-0x06ffff:S, 0x070000-0x070fff:EW, 0x071000-0x071fff:S, 0x072000-0x072fff:S, 0x073000-0x073fff:S, 0x074000-0x074fff:S, 0x075000-0x075fff:EW, 0x076000-0x076fff:EW, 0x077000-0x077fff:EW, 0x078000-0x078fff:EW, 0x079000-0x079fff:EW, 0x07a000-0x07afff:EW, 0x07b000-0x07bfff:EW, 0x07c000-0x07cfff:S, 0x07d000-0x07dfff:S, 0x07e000-0x07efff:S, 0x07f000-0x07ffff:EW Erase/write done. Verifying flash... VERIFIED. Restoring PCI config space for 00:01:0 reg 0x6d Restoring PCI config space for 00:01:0 reg 0x92 svante at stereo:/backup$ 2011/11/17 Joshua Roys > On 11/17/2011 04:24 PM, Svante Olofsson wrote: > >> Hi, >> > > Hello again. > > Very sorry- today is not my day. Off by one bug. Please change 13 to 12. > > Thanks, > > Josh > > -------------- next part -------------- An HTML attachment was scrubbed... URL: From svante at fyraess.com Fri Nov 18 09:43:53 2011 From: svante at fyraess.com (Svante Olofsson) Date: Fri, 18 Nov 2011 10:43:53 +0200 Subject: [flashrom] Asus A7NVM400 (A7NX8-VM400) In-Reply-To: References: <201111171412.pAHECO7v026468@mail2.student.tuwien.ac.at> <4EC53688.5040803@gmail.com> <4EC54891.8010003@gmail.com> <4EC56E16.9070508@gmail.com> <4EC58011.9090305@gmail.com> Message-ID: Hi Joshua, Thank you very much for the help! I can now verify that the patch works, the bios is updated and the system boots ;) Best regards, --Svante -------------- next part -------------- An HTML attachment was scrubbed... URL: From daninreallife86 at me.com Fri Nov 18 00:56:24 2011 From: daninreallife86 at me.com (Dan King) Date: Fri, 18 Nov 2011 00:56:24 +0100 Subject: [flashrom] LiveCD Message-ID: <17226CDA-E52E-4395-A35B-6F5C334B82E3@me.com> I tried to download the live cd and just wanted to let you guys know that only the MegaUpload link works all the rest have been taken down From urjaman at gmail.com Fri Nov 18 17:46:57 2011 From: urjaman at gmail.com (Urja Rannikko) Date: Fri, 18 Nov 2011 18:46:57 +0200 Subject: [flashrom] [patch] serprog: add proper serprog_map In-Reply-To: References: Message-ID: Add serprog_map so that chips are addressed properly. I did this for adding LPC support to my ATmega644 programmer. Signed-off-by: Urja Rannikko ----- That previous one was clearly too verbose, noticed it when I ran this without any -V. I put those messages down one level of verbosity. -- Urja Rannikko -------------- next part -------------- A non-text attachment was scrubbed... Name: serprog_proper_map_r2.patch Type: application/octet-stream Size: 1605 bytes Desc: not available URL: From urjaman at gmail.com Fri Nov 18 17:36:59 2011 From: urjaman at gmail.com (Urja Rannikko) Date: Fri, 18 Nov 2011 18:36:59 +0200 Subject: [flashrom] [patch] serprog: add proper serprog_map Message-ID: Add serprog_map so that chips are addressed properly. I did this for adding LPC support to my ATmega644 programmer. Signed-off-by: Urja Rannikko ------ Sorry if I interrupted you all out of nowhere :P, I was porting LPC code somebody (Mike Stirling, had to look that up) did for the AVR to my ATmega644 (FTDI-USB) programmer, and noticed that it forced a base address of 0xFFF80000 that is right only for 512K chips. I modified the code to only add the highest 8 bits that are not addressable in serprog protocol, and added this map function to have flashrom address stuff properly. This shouldnt affect non-serprog code at all, and it shouldnt matter to parallel, nor it would affect the lpc addr or 0xFFF80000-implementation, also my SPI W25Q80 doesnt mind being addressed in this way at all (detect and read tested). Further testing is recommended. Also sidenote: it might be useful to add an optional write_jedec_1-implementation into serprog. This thing is taking forever to write LPC. (LPC with a 12Mhz AVR isnt that fast anyways, but with USB ping-pong on every byte written...) -- Urja Rannikko -------------- next part -------------- A non-text attachment was scrubbed... Name: serprog_proper_map.patch Type: application/octet-stream Size: 1605 bytes Desc: not available URL: From bblaauw at home.nl Fri Nov 18 19:04:37 2011 From: bblaauw at home.nl (Bernd Blaauw) Date: Fri, 18 Nov 2011 19:04:37 +0100 Subject: [flashrom] LiveCD In-Reply-To: <17226CDA-E52E-4395-A35B-6F5C334B82E3@me.com> References: <17226CDA-E52E-4395-A35B-6F5C334B82E3@me.com> Message-ID: <4EC69E35.50001@home.nl> Op 18-11-2011 0:56, Dan King schreef: > I tried to download the live cd and just wanted to let you guys know that only the MegaUpload link works all the rest have been taken down PartedMagic might be the smallest Linux LiveCD with (recent) flashrom on it. Then again, so many distributions exist, maybe there's something even smaller to experiment with. The official liveCD you mention might be outdated, depends if newer versions were ever released. From fercerpav at gmail.com Fri Nov 18 19:15:43 2011 From: fercerpav at gmail.com (Paul Fertser) Date: Fri, 18 Nov 2011 22:15:43 +0400 Subject: [flashrom] [PATCH] ft2232_spi: fix arm-usb-ocd and arm-usb-ocd-h Message-ID: <201111181828.pAIISQ1O005771@home.pavel.comp> These devices have an additional output buffer which is activated only by pulling ADBUS4 low. This patch was real-life tested with arm-usb-ocd; arm-usb-ocd-h should be the same (as it shares the same documentation). Signed-off-by: Paul Fertser --- ft2232_spi.c | 4 ++++ 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/ft2232_spi.c b/ft2232_spi.c index 8d89ea1..6dcf855 100644 --- a/ft2232_spi.c +++ b/ft2232_spi.c @@ -202,6 +202,8 @@ int ft2232_spi_init(void) ft2232_vid = OLIMEX_VID; ft2232_type = OLIMEX_ARM_OCD_PID; ft2232_interface = INTERFACE_A; + cs_bits = 0x08; + pindir = 0x1b; } else if (!strcasecmp(arg, "arm-usb-tiny")) { ft2232_vid = OLIMEX_VID; ft2232_type = OLIMEX_ARM_TINY_PID; @@ -210,6 +212,8 @@ int ft2232_spi_init(void) ft2232_vid = OLIMEX_VID; ft2232_type = OLIMEX_ARM_OCD_H_PID; ft2232_interface = INTERFACE_A; + cs_bits = 0x08; + pindir = 0x1b; } else if (!strcasecmp(arg, "arm-usb-tiny-h")) { ft2232_vid = OLIMEX_VID; ft2232_type = OLIMEX_ARM_TINY_H_PID; -- 1.7.7 From marcosfrm at gmail.com Sat Nov 19 15:18:11 2011 From: marcosfrm at gmail.com (Marcos Felipe Rasia de Mello) Date: Sat, 19 Nov 2011 12:18:11 -0200 Subject: [flashrom] ASUS P5PE-VM Message-ID: ASUS P5PE-VM success report. http://www.asus.com/Motherboards/Intel_Socket_775/P5PEVM/ Logs attached. Marcos -------------- next part -------------- flashrom v0.9.4-r1451 on Linux 3.0.4-zero (i686), built with libpci 3.1.7, GCC 4.4.5, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 1800M loops per second, 10 myus = 10 us, 100 myus = 101 us, 1000 myus = 1000 us, 10000 myus = 10003 us, 4 myus = 5 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "System manufacturer" DMI string system-product-name: "System Product Name" DMI string system-version: "System Version" DMI string baseboard-manufacturer: "ASUSTeK Computer Inc." DMI string baseboard-product-name: "P5PE-VM" DMI string baseboard-version: "Rev 1.00" DMI string chassis-type: "Desktop" Found chipset "Intel ICH5/ICH5R" with PCI ID 8086:24d0. Enabling flash write... BIOS Lock Enable: disabled, BIOS Write Enable: disabled, BIOS_CNTL is 0x0 OK. This chipset supports the following protocols: FWH. Disabling flash write protection for board "ASUS P5PE-VM"... Intel ICH LPC bridge: Raising GPIO21. OK. Probing for Atmel AT49LH002, 256 kB: probe_82802ab: id1 0x2e, id2 0x82, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0xda, id2 0x50 Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0x2e, id2 0x82, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0xda, id2 0x50 Found Winbond flash chip "W39V040FC" (512 kB, FWH) at physical address 0xfff80000. Lockout bits: Hardware bootblock locking (#TBL) is not active. Hardware remaining chip locking (#WP) is not active.. Lock status of block at 0x00000000 is Full Access. Lock status of block at 0x00010000 is Full Access. Lock status of block at 0x00020000 is Full Access. Lock status of block at 0x00030000 is Full Access. Lock status of block at 0x00040000 is Full Access. Lock status of block at 0x00050000 is Full Access. Lock status of block at 0x00060000 is Full Access. Lock status of block at 0x00070000 is Full Access. Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 0xda, id2 0x50 Found Winbond flash chip "W39V040FC" (512 kB, FWH). === This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE The test status of this chip may have been updated in the latest development version of flashrom. If you are running the latest development version, please email a report to flashrom at flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -Vr, -Vw, -VE), and mention which mainboard or programmer you tested. Please mention your board in the subject line. Thanks for your help! No operations were specified. Restoring PCI config space for 00:1f:0 reg 0x4e -------------- next part -------------- flashrom v0.9.4-r1451 on Linux 3.0.4-zero (i686), built with libpci 3.1.7, GCC 4.4.5, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 1800M loops per second, 10 myus = 11 us, 100 myus = 101 us, 1000 myus = 1000 us, 10000 myus = 10002 us, 4 myus = 4 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "System manufacturer" DMI string system-product-name: "System Product Name" DMI string system-version: "System Version" DMI string baseboard-manufacturer: "ASUSTeK Computer Inc." DMI string baseboard-product-name: "P5PE-VM" DMI string baseboard-version: "Rev 1.00" DMI string chassis-type: "Desktop" Found chipset "Intel ICH5/ICH5R" with PCI ID 8086:24d0. Enabling flash write... BIOS Lock Enable: disabled, BIOS Write Enable: disabled, BIOS_CNTL is 0x0 OK. This chipset supports the following protocols: FWH. Disabling flash write protection for board "ASUS P5PE-VM"... Intel ICH LPC bridge: Raising GPIO21. OK. Probing for Atmel AT49LH002, 256 kB: probe_82802ab: id1 0x2e, id2 0x82, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0xda, id2 0x50 Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0x2e, id2 0x82, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0xda, id2 0x50 Found Winbond flash chip "W39V040FC" (512 kB, FWH) at physical address 0xfff80000. Lockout bits: Hardware bootblock locking (#TBL) is not active. Hardware remaining chip locking (#WP) is not active.. Lock status of block at 0x00000000 is Full Access. Lock status of block at 0x00010000 is Full Access. Lock status of block at 0x00020000 is Full Access. Lock status of block at 0x00030000 is Full Access. Lock status of block at 0x00040000 is Full Access. Lock status of block at 0x00050000 is Full Access. Lock status of block at 0x00060000 is Full Access. Lock status of block at 0x00070000 is Full Access. Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 0xda, id2 0x50 Found Winbond flash chip "W39V040FC" (512 kB, FWH). === This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE The test status of this chip may have been updated in the latest development version of flashrom. If you are running the latest development version, please email a report to flashrom at flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -Vr, -Vw, -VE), and mention which mainboard or programmer you tested. Please mention your board in the subject line. Thanks for your help! Reading flash... done. Restoring PCI config space for 00:1f:0 reg 0x4e -------------- next part -------------- flashrom v0.9.4-r1451 on Linux 3.0.4-zero (i686), built with libpci 3.1.7, GCC 4.4.5, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 1800M loops per second, 10 myus = 10 us, 100 myus = 100 us, 1000 myus = 1000 us, 10000 myus = 10003 us, 4 myus = 5 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "System manufacturer" DMI string system-product-name: "System Product Name" DMI string system-version: "System Version" DMI string baseboard-manufacturer: "ASUSTeK Computer Inc." DMI string baseboard-product-name: "P5PE-VM" DMI string baseboard-version: "Rev 1.00" DMI string chassis-type: "Desktop" Found chipset "Intel ICH5/ICH5R" with PCI ID 8086:24d0. Enabling flash write... BIOS Lock Enable: disabled, BIOS Write Enable: disabled, BIOS_CNTL is 0x0 OK. This chipset supports the following protocols: FWH. Disabling flash write protection for board "ASUS P5PE-VM"... Intel ICH LPC bridge: Raising GPIO21. OK. Probing for Atmel AT49LH002, 256 kB: probe_82802ab: id1 0x2e, id2 0x82, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0xda, id2 0x50 Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0x2e, id2 0x82, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0xda, id2 0x50 Found Winbond flash chip "W39V040FC" (512 kB, FWH) at physical address 0xfff80000. Lockout bits: Hardware bootblock locking (#TBL) is not active. Hardware remaining chip locking (#WP) is not active.. Lock status of block at 0x00000000 is Full Access. Lock status of block at 0x00010000 is Full Access. Lock status of block at 0x00020000 is Full Access. Lock status of block at 0x00030000 is Full Access. Lock status of block at 0x00040000 is Full Access. Lock status of block at 0x00050000 is Full Access. Lock status of block at 0x00060000 is Full Access. Lock status of block at 0x00070000 is Full Access. Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 0xda, id2 0x50 Found Winbond flash chip "W39V040FC" (512 kB, FWH). === This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE The test status of this chip may have been updated in the latest development version of flashrom. If you are running the latest development version, please email a report to flashrom at flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -Vr, -Vw, -VE), and mention which mainboard or programmer you tested. Please mention your board in the subject line. Thanks for your help! Erasing and writing flash chip... Trying erase function 0... 0x000000-0x00ffff:E, 0x010000-0x01ffff:E, 0x020000-0x02ffff:E, 0x030000-0x03ffff:E, 0x040000-0x04ffff:E, 0x050000-0x05ffff:E, 0x060000-0x06ffff:E, 0x070000-0x07ffff:E Erase/write done. Restoring PCI config space for 00:1f:0 reg 0x4e -------------- next part -------------- flashrom v0.9.4-r1451 on Linux 3.0.4-zero (i686), built with libpci 3.1.7, GCC 4.4.5, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 1800M loops per second, 10 myus = 10 us, 100 myus = 100 us, 1000 myus = 1000 us, 10000 myus = 10003 us, 4 myus = 5 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "System manufacturer" DMI string system-product-name: "System Product Name" DMI string system-version: "System Version" DMI string baseboard-manufacturer: "ASUSTeK Computer Inc." DMI string baseboard-product-name: "P5PE-VM" DMI string baseboard-version: "Rev 1.00" DMI string chassis-type: "Desktop" Found chipset "Intel ICH5/ICH5R" with PCI ID 8086:24d0. Enabling flash write... BIOS Lock Enable: disabled, BIOS Write Enable: disabled, BIOS_CNTL is 0x0 OK. This chipset supports the following protocols: FWH. Disabling flash write protection for board "ASUS P5PE-VM"... Intel ICH LPC bridge: Raising GPIO21. OK. Probing for Atmel AT49LH002, 256 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0xda, id2 0x50 Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0xda, id2 0x50 Found Winbond flash chip "W39V040FC" (512 kB, FWH) at physical address 0xfff80000. Lockout bits: Hardware bootblock locking (#TBL) is not active. Hardware remaining chip locking (#WP) is not active.. Lock status of block at 0x00000000 is Full Access. Lock status of block at 0x00010000 is Full Access. Lock status of block at 0x00020000 is Full Access. Lock status of block at 0x00030000 is Full Access. Lock status of block at 0x00040000 is Full Access. Lock status of block at 0x00050000 is Full Access. Lock status of block at 0x00060000 is Full Access. Lock status of block at 0x00070000 is Full Access. Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 0xda, id2 0x50 Found Winbond flash chip "W39V040FC" (512 kB, FWH). === This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE The test status of this chip may have been updated in the latest development version of flashrom. If you are running the latest development version, please email a report to flashrom at flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -Vr, -Vw, -VE), and mention which mainboard or programmer you tested. Please mention your board in the subject line. Thanks for your help! Flash image seems to be a legacy BIOS. Disabling coreboot-related checks. Reading old flash chip contents... done. Erasing and writing flash chip... Trying erase function 0... 0x000000-0x00ffff:W, 0x010000-0x01ffff:W, 0x020000-0x02ffff:W, 0x030000-0x03ffff:W, 0x040000-0x04ffff:W, 0x050000-0x05ffff:W, 0x060000-0x06ffff:W, 0x070000-0x07ffff:W Erase/write done. Verifying flash... VERIFIED. Restoring PCI config space for 00:1f:0 reg 0x4e From svn at flashrom.org Sat Nov 19 20:31:17 2011 From: svn at flashrom.org (repository service) Date: Sat, 19 Nov 2011 20:31:17 +0100 Subject: [flashrom] [commit] r1469 - trunk Message-ID: Author: stefanct Date: Sat Nov 19 20:31:17 2011 New Revision: 1469 URL: http://flashrom.org/trac/flashrom/changeset/1469 Log: Add board enable for ASUS A7N8X-VM/400 http://www.flashrom.org/pipermail/flashrom/2011-November/008274.html Signed-off-by: Joshua Roys Acked-by: Stefan Tauner Modified: trunk/board_enable.c trunk/print.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Wed Nov 16 23:08:11 2011 (r1468) +++ trunk/board_enable.c Sat Nov 19 20:31:17 2011 (r1469) @@ -2008,6 +2008,15 @@ /* * Suited for: + * - ASUS A7N8X-VM/400: NVIDIA nForce2 IGP2 + IT8712F + */ +static int it8712f_gpio12_raise(void) +{ + return it87_gpio_set(12, 1); +} + +/* + * Suited for: * - ASUS A7V600-X: VIA KT600 + VT8237 + IT8712F * - ASUS A7V8X-X: VIA KT400 + VT8235 + IT8712F */ @@ -2094,6 +2103,7 @@ {0x1039, 0x0741, 0x1849, 0x0741, 0x1039, 0x5513, 0x1849, 0x5513, "^K7S41GX$", NULL, NULL, P3, "ASRock", "K7S41GX", 0, OK, w836xx_memw_enable_2e}, {0x8086, 0x24D4, 0x1849, 0x24D0, 0x8086, 0x24D5, 0x1849, 0x9739, NULL, NULL, NULL, P3, "ASRock", "P4i65GV", 0, OK, intel_ich_gpio23_raise}, {0x8086, 0x2570, 0x1849, 0x2570, 0x8086, 0x24d3, 0x1849, 0x24d0, NULL, NULL, NULL, P3, "ASRock", "775i65G", 0, OK, intel_ich_gpio23_raise}, + {0x10DE, 0x0060, 0x1043, 0x80AD, 0x10DE, 0x01E0, 0x1043, 0x80C0, NULL, NULL, NULL, P3, "ASUS", "A7N8X-VM/400", 0, OK, it8712f_gpio12_raise}, {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3065, 0x1043, 0x80ED, NULL, NULL, NULL, P3, "ASUS", "A7V600-X", 0, OK, it8712f_gpio31_raise}, {0x1106, 0x3177, 0x1043, 0x80A1, 0x1106, 0x3205, 0x1043, 0x8118, NULL, NULL, NULL, P3, "ASUS", "A7V8X-MX SE", 0, OK, w836xx_memw_enable_2e}, {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x808C, NULL, NULL, NULL, P3, "ASUS", "A7V8X", 0, OK, it8703f_gpio51_raise}, Modified: trunk/print.c ============================================================================== --- trunk/print.c Wed Nov 16 23:08:11 2011 (r1468) +++ trunk/print.c Sat Nov 19 20:31:17 2011 (r1469) @@ -571,6 +571,7 @@ B("ASRock", "P4i65GV", 1, "http://www.asrock.com/mb/overview.asp?Model=P4i65GV", NULL), B("ASUS", "A7N8X Deluxe", 1, "http://www.asus.com/product.aspx?P_ID=wAsRYm41KTp78MFC", NULL), B("ASUS", "A7N8X-E Deluxe", 1, "http://www.asus.com/product.aspx?P_ID=TmQtPJv4jIxmL9C2", NULL), + B("ASUS", "A7N8X-VM/400", 1, "http://www.asus.com/Motherboards/AMD_Socket_A/A7N8XVM400/", NULL), B("ASUS", "A7V133", 1, "ftp://ftp.asus.com.tw/pub/ASUS/mb/socka/kt133a/a7v133/", NULL), B("ASUS", "A7V333", 1, "ftp://ftp.asus.com.tw/pub/asus/mb/socka/kt333/a7v333/", NULL), B("ASUS", "A7V400-MX", 1, "http://www.asus.com/product.aspx?P_ID=hORgEHRBDLMfwAwx", NULL), From stefan.tauner at student.tuwien.ac.at Sat Nov 19 20:32:20 2011 From: stefan.tauner at student.tuwien.ac.at (Stefan Tauner) Date: Sat, 19 Nov 2011 20:32:20 +0100 Subject: [flashrom] Asus A7NVM400 (A7NX8-VM400) In-Reply-To: <4EC58011.9090305@gmail.com> References: <201111171412.pAHECO7v026468@mail2.student.tuwien.ac.at> <4EC53688.5040803@gmail.com> <4EC54891.8010003@gmail.com> <4EC56E16.9070508@gmail.com> <4EC58011.9090305@gmail.com> Message-ID: <201111191932.pAJJWE5N012463@mail2.student.tuwien.ac.at> On Thu, 17 Nov 2011 16:43:45 -0500 Joshua Roys wrote: > On 11/17/2011 04:24 PM, Svante Olofsson wrote: > > Hi, > > Hello again. > > Very sorry- today is not my day. Off by one bug. Please change 13 to 12. > > Thanks, > > Josh > thanks! committed in r1469 -- Kind regards/Mit freundlichen Gr??en, Stefan Tauner From anders.arpteg at gmail.com Tue Nov 22 10:35:11 2011 From: anders.arpteg at gmail.com (anders.arpteg at gmail.com) Date: Tue, 22 Nov 2011 10:35:11 +0100 Subject: [flashrom] Asus M3N78-EM: flashrom -V Message-ID: flashrom v0.9.4-r1394 on Linux 3.0.0-13-generic (x86_64), built with libpci 3.1.7, GCC 4.6.1, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 1247M loops per second, 10 myus = 10 us, 100 myus = 104 us, 1000 myus = 1013 us, 10000 myus = 10045 us, 4 myus = 4 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "System manufacturer" DMI string system-product-name: "System Product Name" DMI string system-version: "System Version" DMI string baseboard-manufacturer: "ASUSTeK Computer INC." DMI string baseboard-product-name: "M3N78-EM" DMI string baseboard-version: "Rev X.0x" DMI string chassis-type: "Desktop" Found ITE Super I/O, ID 0x8712 on port 0x2e Found chipset "NVIDIA MCP78S" with PCI ID 10de:075c. This chipset is marked as untested. If you are using an up-to-date version of flashrom please email a report to flashrom at flashrom.org including a verbose (-V) log. Thank you! Enabling flash write... This chipset is not really supported yet. Guesswork... ISA/LPC bridge reg 0x8a contents: 0x40, bit 6 is 1, bit 5 is 0 Flash bus type is SPI SPI on this chipset is WIP. Please report any success or failure by mailing us the verbose output to flashrom at flashrom.org, thanks! Found SMBus device 10de:0752 at 00:01:1 MCP SPI BAR is at 0xfce80000 Mapping NVIDIA MCP6x SPI at 0xfce80000, unaligned size 0x544. SPI control is 0xc012, req=0, gnt=0 Please send the output of "flashrom -V" to flashrom at flashrom.org with your board name: flashrom -V as the subject to help us finish support for your chipset. Thanks. OK. This chipset supports the following protocols: SPI. Super I/O ID 0x8712 is not on the list of flash capable controllers. Probing for AMIC A25L05PT, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L05PU, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L10PT, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L10PU, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L20PT, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L20PU, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L40PT, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L40PU, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L80P, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L16PT, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L16PU, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L512, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L010, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L020, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L040, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L080, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L016, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L032, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25LQ032, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT25DF021, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT25DF041A, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT25DF081, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT25DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT25DF161, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT25DF321, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT25DF321A, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT25DF641, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT25DQ161, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT25F512B, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT25FS010, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT25FS040, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT26DF041, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT26DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT26DF161, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT26DF161A, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT26F004, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT45CS1282, 16896 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT45DB011D, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT45DB021D, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT45DB041D, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT45DB081D, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT45DB161D, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT45DB321C, 4224 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT45DB321D, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT45DB642D, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for EMST F25L008A, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B05, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B05T, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B10T, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B20T, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B40T, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B80T, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B16T, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B32T, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B64T, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25F05, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25F10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25F20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25F40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25F80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25F16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25F32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25Q40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25Q80(A), 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25Q32(A/B), 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25QH16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Macronix MX25L512, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Macronix MX25L1005, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Macronix MX25L2005, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Macronix MX25L4005, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Macronix MX25L8005, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Macronix MX25L1605, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Macronix MX25L1635D, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Macronix MX25L1635E, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Macronix MX25L3205, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Macronix MX25L3235D, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Macronix MX25L6405, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Macronix MX25L12805, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Numonyx M25PE10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Numonyx M25PE20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Numonyx M25PE40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Numonyx M25PE80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Numonyx M25PE16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for PMC Pm25LV010, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for PMC Pm25LV016B, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for PMC Pm25LV020, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for PMC Pm25LV040, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for PMC Pm25LV080B, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for PMC Pm25LV512, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Sanyo LF25FW203A, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Spansion S25FL004A, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Spansion S25FL008A, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Spansion S25FL016A, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Spansion S25FL032A, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Spansion S25FL064A, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for SST SST25VF010.REMS, 128 kB: probe_spi_rems: id1 0xef, id2 0x13 Probing for SST SST25VF016B, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for SST SST25VF032B, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for SST SST25VF064C, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for SST SST25VF040.REMS, 512 kB: probe_spi_rems: id1 0xef, id2 0x13 Probing for SST SST25VF040B, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for SST SST25LF040A.RES, 512 kB: probe_spi_res2: id1 0x13, id2 0x13 Probing for SST SST25VF040B.REMS, 512 kB: probe_spi_rems: id1 0xef, id2 0x13 Probing for SST SST25VF080B, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for ST M25P05-A, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for ST M25P05.RES, 64 kB: Ignoring RES in favour of RDID. Probing for ST M25P10-A, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for ST M25P10.RES, 128 kB: Ignoring RES in favour of RDID. Probing for ST M25P20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for ST M25P40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for ST M25P40-old, 512 kB: Ignoring RES in favour of RDID. Probing for ST M25P80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for ST M25P16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for ST M25P32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for ST M25P64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for ST M25P128, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for ST M25PX16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for ST M25PX32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for ST M25PX64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Winbond W25Q80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Winbond W25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Winbond W25Q32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Winbond W25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Winbond W25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Winbond W25X10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Winbond W25X20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Winbond W25X40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Winbond W25X80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Chip status register is 00 Found Winbond flash chip "W25X80" (1024 kB, SPI) at physical address 0xfff00000. Probing for Winbond W25X16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Winbond W25X32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Winbond W25X64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC unknown AMIC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel unknown Atmel SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon unknown Eon SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Macronix unknown Macronix SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for PMC unknown PMC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for SST unknown SST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for ST unknown ST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Sanyo unknown Sanyo SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Generic unknown SPI chip (RDID), 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Generic unknown SPI chip (REMS), 0 kB: probe_spi_rems: id1 0xef, id2 0x13 No operations were specified. -------------- next part -------------- An HTML attachment was scrubbed... URL: From stefan.tauner at student.tuwien.ac.at Tue Nov 22 20:09:47 2011 From: stefan.tauner at student.tuwien.ac.at (Stefan Tauner) Date: Tue, 22 Nov 2011 20:09:47 +0100 Subject: [flashrom] ASUS P5PE-VM In-Reply-To: References: Message-ID: <201111221909.pAMJ9kbh000791@mail2.student.tuwien.ac.at> On Sat, 19 Nov 2011 12:18:11 -0200 Marcos Felipe Rasia de Mello wrote: > ASUS P5PE-VM success report. > > http://www.asus.com/Motherboards/Intel_Socket_775/P5PEVM/ > > Logs attached. > > Marcos Hello Marcos, thanks for your report! I have marked the flash chip (W39V040FC) as fully tested and will commit that later together with other small changes. The mainboard was already known to work (since the board enable was added in r1100). -- Kind regards/Mit freundlichen Gr??en, Stefan Tauner From stefan.tauner at student.tuwien.ac.at Tue Nov 22 23:09:43 2011 From: stefan.tauner at student.tuwien.ac.at (Stefan Tauner) Date: Tue, 22 Nov 2011 23:09:43 +0100 Subject: [flashrom] [PATCH] Unsignify lengths and addresses in chip functions and structs In-Reply-To: <4EC0436B.2090800@gmx.net> References: <201109180042.p8I0gEYE024377@mail2.student.tuwien.ac.at> <1316390511-31596-1-git-send-email-stefan.tauner@student.tuwien.ac.at> <4EC0436B.2090800@gmx.net> Message-ID: <201111222209.pAMM9fHJ028916@mail2.student.tuwien.ac.at> On Sun, 13 Nov 2011 23:23:39 +0100 Carl-Daniel Hailfinger wrote: > Am 19.09.2011 02:01 schrieb Stefan Tauner: > > Push those changes forward where needed to prevent new sign > > conversion warnings where possible. > > Thanks for your patch. > > > > Signed-off-by: Stefan Tauner > > > > > > diff --git a/flash.h b/flash.h > > index 535c1b8..e7bfd4e 100644 > > --- a/flash.h > > +++ b/flash.h > > @@ -121,8 +121,10 @@ struct flashchip { > > > > int (*probe) (struct flashchip *flash); > > > > - /* Delay after "enter/exit ID mode" commands in microseconds. */ > > - int probe_timing; > > + /* Delay after "enter/exit ID mode" commands in microseconds. > > + * NB: negative values have special meanings, see TIMING_* below. > > + */ > > + signed int probe_timing; > > AFAICS the C standard defines that int is always signed. The only > exception is char which is implementation-defined. Please kill signed > here, but keep your comment. see other mail, unchanged in attached patch. > > > > /* > > * Erase blocks and associated erase function. Any chip erase function > > diff --git a/ft2232_spi.c b/ft2232_spi.c > > index 8ab89fa..8f00685 100644 > > --- a/ft2232_spi.c > > +++ b/ft2232_spi.c > > @@ -106,10 +106,10 @@ static const char *get_ft2232_vendorname(int ft2232_vid, int ft2232_type) > > } > > > > static int send_buf(struct ftdi_context *ftdic, const unsigned char *buf, > > - int size) > > + unsigned int size) > > { > > int r; > > - r = ftdi_write_data(ftdic, (unsigned char *) buf, size); > > + r = ftdi_write_data(ftdic, (unsigned char *) buf, (int)size); > > This cast is a sign that something is odd. Can you keep size as a signed > int? reverted here and below... > > > if (r < 0) { > > msg_perr("ftdi_write_data: %d, %s\n", r, > > ftdi_get_error_string(ftdic)); > > @@ -119,19 +119,19 @@ static int send_buf(struct ftdi_context *ftdic, const unsigned char *buf, > > } > > > > static int get_buf(struct ftdi_context *ftdic, const unsigned char *buf, > > - int size) > > + unsigned int size) > > { > > int r; > > > > while (size > 0) { > > - r = ftdi_read_data(ftdic, (unsigned char *) buf, size); > > + r = ftdi_read_data(ftdic, (unsigned char *) buf, (int)size); > > Same here. > > > > if (r < 0) { > > msg_perr("ftdi_read_data: %d, %s\n", r, > > ftdi_get_error_string(ftdic)); > > return 1; > > } > > - buf += r; > > - size -= r; > > + buf += (unsigned int)r; > > + size -= (unsigned int)r; > > ... > > > > } > > return 0; > > } > > @@ -332,9 +332,10 @@ static int ft2232_spi_send_command(unsigned int writecnt, unsigned int readcnt, > > struct ftdi_context *ftdic = &ftdic_context; > > static unsigned char *buf = NULL; > > /* failed is special. We use bitwise ops, but it is essentially bool. */ > > - int i = 0, ret = 0, failed = 0; > > - int bufsize; > > - static int oldbufsize = 0; > > + int ret = 0, failed = 0; > > + unsigned int i = 0; > > + unsigned int bufsize; > > + static unsigned int oldbufsize = 0; > > > > if (writecnt > 65536 || readcnt > 65536) > > return SPI_INVALID_LENGTH; > > get_buf and send_buf calls should be checked for size>=INT_MAX and the > cast should happen in the call, not in get_buf/send_buf. i am not sure this is what we want. mainly... because (the buffer handling in) ft2232_spi.c is slightly awful :) various "bufs" (well, 2), some of them static (ok, only the one in send_command, but still this is messier than expected for such a simple driver), the two ~equivalent failed/ret variables in send_command etc. make it a bit unreadable. we need to check for failure of the buffer methods anyway, so i dont see a reason to do the size checks in the caller(s). i have reverted the whole file now, because i am not sure how to proceed and wanted to publish what i have. not much changed, but i had to rebase it due to the addition of the opaque framework and hwseq. > [?] > With the above comments this is > Acked-by: Carl-Daniel Hailfinger should i commit the attached version? -- Kind regards/Mit freundlichen Gr??en, Stefan Tauner -------------- next part -------------- A non-text attachment was scrubbed... Name: 0001-Unsignify-lengths-and-addresses-in-chip-functions-an.patch Type: text/x-patch Size: 40770 bytes Desc: not available URL: From stefan.tauner at student.tuwien.ac.at Tue Nov 22 23:34:42 2011 From: stefan.tauner at student.tuwien.ac.at (Stefan Tauner) Date: Tue, 22 Nov 2011 23:34:42 +0100 Subject: [flashrom] flashrom v0.9.4-r1467 + SUPERMICOR X9SCL In-Reply-To: References: Message-ID: <201111222235.pAMMZRdU024940@mail2.student.tuwien.ac.at> On Tue, 15 Nov 2011 16:42:20 +0100 "Panny, Martin" wrote: > 0x5C: 0x03ff0030 (FREG2: Management Engine) > 0x00030000-0x003fffff is locked Hello Martin, thanks for your report! The problem is the locked ME region as quoted above. We are working on unlocking it, but intel does not provide us any documentation so please do not expect a solution soon. I have added the board to our list of (un)supported boards (with an appropriate note) and will commit that later together with other small changes. -- Kind regards/Mit freundlichen Gr??en, Stefan Tauner From c-d.hailfinger.devel.2006 at gmx.net Wed Nov 23 00:19:32 2011 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Wed, 23 Nov 2011 00:19:32 +0100 Subject: [flashrom] [PATCH] Unsignify lengths and addresses in chip functions and structs In-Reply-To: <201111222209.pAMM9fHJ028916@mail2.student.tuwien.ac.at> References: <201109180042.p8I0gEYE024377@mail2.student.tuwien.ac.at> <1316390511-31596-1-git-send-email-stefan.tauner@student.tuwien.ac.at> <4EC0436B.2090800@gmx.net> <201111222209.pAMM9fHJ028916@mail2.student.tuwien.ac.at> Message-ID: <4ECC2E04.6070704@gmx.net> Am 22.11.2011 23:09 schrieb Stefan Tauner: > (the buffer > handling in) ft2232_spi.c is slightly awful :) > various "bufs" (well, 2), some of them static (ok, only the one in > send_command, but still this is messier than expected for such a > simple driver), the two ~equivalent failed/ret variables in send_command > etc. make it a bit unreadable. Indeed, this file could use some cleanup. > we need to check for failure of the buffer methods anyway, so i dont > see a reason to do the size checks in the caller(s). > > i have reverted the whole file now, because i am not sure how to > proceed and wanted to publish what i have. not much changed, but i had > to rebase it due to the addition of the opaque framework and hwseq. > >> > [?] >> > With the above comments this is >> > Acked-by: Carl-Daniel Hailfinger > should i commit the attached version? Please do, the ack is still valid. I wonder whether we should enable the sign warnings once the cleanups and remaining conversions are in. The big problem might be platform (OS/library version) dependent changes which we don't know of, but OTOH we won't know until we try it. Regards, Carl-Daniel -- http://www.hailfinger.org/ From svn at flashrom.org Wed Nov 23 10:13:48 2011 From: svn at flashrom.org (repository service) Date: Wed, 23 Nov 2011 10:13:48 +0100 Subject: [flashrom] [commit] r1470 - trunk Message-ID: Author: stefanct Date: Wed Nov 23 10:13:48 2011 New Revision: 1470 URL: http://flashrom.org/trac/flashrom/changeset/1470 Log: Unsignify lengths and addresses in chip functions and structs Push those changes forward where needed to prevent new sign conversion warnings where possible. Signed-off-by: Stefan Tauner Acked-by: Carl-Daniel Hailfinger Modified: trunk/82802ab.c trunk/buspirate_spi.c trunk/chipdrivers.h trunk/dediprog.c trunk/dummyflasher.c trunk/flash.h trunk/flashrom.c trunk/ichspi.c trunk/it87spi.c trunk/jedec.c trunk/linux_spi.c trunk/m29f400bt.c trunk/opaque.c trunk/pm49fl00x.c trunk/programmer.h trunk/serprog.c trunk/spi.c trunk/spi25.c trunk/sst28sf040.c trunk/sst49lfxxxc.c trunk/w39.c trunk/wbsio_spi.c Modified: trunk/82802ab.c ============================================================================== --- trunk/82802ab.c Sat Nov 19 20:31:17 2011 (r1469) +++ trunk/82802ab.c Wed Nov 23 10:13:48 2011 (r1470) @@ -141,7 +141,7 @@ } /* chunksize is 1 */ -int write_82802ab(struct flashchip *flash, uint8_t *src, int start, int len) +int write_82802ab(struct flashchip *flash, uint8_t *src, unsigned int start, unsigned int len) { int i; chipaddr dst = flash->virtual_memory + start; Modified: trunk/buspirate_spi.c ============================================================================== --- trunk/buspirate_spi.c Sat Nov 19 20:31:17 2011 (r1469) +++ trunk/buspirate_spi.c Wed Nov 23 10:13:48 2011 (r1470) @@ -295,7 +295,8 @@ const unsigned char *writearr, unsigned char *readarr) { static unsigned char *buf = NULL; - int i = 0, ret = 0; + unsigned int i = 0; + int ret = 0; if (writecnt > 16 || readcnt > 16 || (readcnt + writecnt) > 16) return SPI_INVALID_LENGTH; Modified: trunk/chipdrivers.h ============================================================================== --- trunk/chipdrivers.h Sat Nov 19 20:31:17 2011 (r1469) +++ trunk/chipdrivers.h Wed Nov 23 10:13:48 2011 (r1470) @@ -41,9 +41,9 @@ int spi_block_erase_d8(struct flashchip *flash, unsigned int addr, unsigned int blocklen); int spi_block_erase_60(struct flashchip *flash, unsigned int addr, unsigned int blocklen); int spi_block_erase_c7(struct flashchip *flash, unsigned int addr, unsigned int blocklen); -int spi_chip_write_1(struct flashchip *flash, uint8_t *buf, int start, int len); -int spi_chip_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); -int spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len); +int spi_chip_write_1(struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len); +int spi_chip_write_256(struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len); +int spi_chip_read(struct flashchip *flash, uint8_t *buf, unsigned int start, int unsigned len); uint8_t spi_read_status_register(void); int spi_write_status_register(struct flashchip *flash, int status); void spi_prettyprint_status_register_bit(uint8_t status, int bit); @@ -51,17 +51,17 @@ void spi_prettyprint_status_register_welwip(uint8_t status); int spi_prettyprint_status_register(struct flashchip *flash); int spi_disable_blockprotect(struct flashchip *flash); -int spi_byte_program(int addr, uint8_t databyte); -int spi_nbyte_program(int addr, uint8_t *bytes, int len); -int spi_nbyte_read(int addr, uint8_t *bytes, int len); -int spi_read_chunked(struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize); -int spi_write_chunked(struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize); -int spi_aai_write(struct flashchip *flash, uint8_t *buf, int start, int len); +int spi_byte_program(unsigned int addr, uint8_t databyte); +int spi_nbyte_program(unsigned int addr, uint8_t *bytes, unsigned int len); +int spi_nbyte_read(unsigned int addr, uint8_t *bytes, unsigned int len); +int spi_read_chunked(struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len, unsigned int chunksize); +int spi_write_chunked(struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len, unsigned int chunksize); +int spi_aai_write(struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len); /* opaque.c */ int probe_opaque(struct flashchip *flash); -int read_opaque(struct flashchip *flash, uint8_t *buf, int start, int len); -int write_opaque(struct flashchip *flash, uint8_t *buf, int start, int len); +int read_opaque(struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len); +int write_opaque(struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len); int erase_opaque(struct flashchip *flash, unsigned int blockaddr, unsigned int blocklen); /* a25.c */ @@ -87,7 +87,7 @@ uint8_t wait_82802ab(struct flashchip *flash); int probe_82802ab(struct flashchip *flash); int erase_block_82802ab(struct flashchip *flash, unsigned int page, unsigned int pagesize); -int write_82802ab(struct flashchip *flash, uint8_t *buf, int start, int len); +int write_82802ab(struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len); void print_status_82802ab(uint8_t status); int unlock_82802ab(struct flashchip *flash); int unlock_28f004s5(struct flashchip *flash); @@ -100,8 +100,8 @@ int write_byte_program_jedec(chipaddr bios, uint8_t *src, chipaddr dst); int probe_jedec(struct flashchip *flash); -int write_jedec(struct flashchip *flash, uint8_t *buf, int start, int len); -int write_jedec_1(struct flashchip *flash, uint8_t *buf, int start, int len); +int write_jedec(struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len); +int write_jedec_1(struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len); int erase_sector_jedec(struct flashchip *flash, unsigned int page, unsigned int pagesize); int erase_block_jedec(struct flashchip *flash, unsigned int page, unsigned int blocksize); int erase_chip_block_jedec(struct flashchip *flash, unsigned int page, unsigned int blocksize); @@ -110,7 +110,7 @@ int probe_m29f400bt(struct flashchip *flash); int block_erase_m29f400bt(struct flashchip *flash, unsigned int start, unsigned int len); int block_erase_chip_m29f400bt(struct flashchip *flash, unsigned int start, unsigned int len); -int write_m29f400bt(struct flashchip *flash, uint8_t *buf, int start, int len); +int write_m29f400bt(struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len); void protect_m29f400bt(chipaddr bios); /* pm49fl00x.c */ @@ -120,7 +120,7 @@ /* sst28sf040.c */ int erase_chip_28sf040(struct flashchip *flash, unsigned int addr, unsigned int blocklen); int erase_sector_28sf040(struct flashchip *flash, unsigned int address, unsigned int sector_size); -int write_28sf040(struct flashchip *flash, uint8_t *buf, int start, int len); +int write_28sf040(struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len); int unprotect_28sf040(struct flashchip *flash); int protect_28sf040(struct flashchip *flash); Modified: trunk/dediprog.c ============================================================================== --- trunk/dediprog.c Sat Nov 19 20:31:17 2011 (r1469) +++ trunk/dediprog.c Wed Nov 23 10:13:48 2011 (r1470) @@ -206,13 +206,13 @@ * @return 0 on success, 1 on failure */ static int dediprog_spi_bulk_read(struct flashchip *flash, uint8_t *buf, - int start, int len) + unsigned int start, unsigned int len) { int ret; - int i; + unsigned int i; /* chunksize must be 512, other sizes will NOT work at all. */ - const int chunksize = 0x200; - const int count = len / chunksize; + const unsigned int chunksize = 0x200; + const unsigned int count = len / chunksize; const char count_and_chunk[] = {count & 0xff, (count >> 8) & 0xff, chunksize & 0xff, @@ -253,14 +253,14 @@ return 0; } -static int dediprog_spi_read(struct flashchip *flash, uint8_t *buf, int start, - int len) +static int dediprog_spi_read(struct flashchip *flash, uint8_t *buf, + unsigned int start, unsigned int len) { int ret; /* chunksize must be 512, other sizes will NOT work at all. */ - const int chunksize = 0x200; - int residue = start % chunksize ? chunksize - start % chunksize : 0; - int bulklen; + const unsigned int chunksize = 0x200; + unsigned int residue = start % chunksize ? chunksize - start % chunksize : 0; + unsigned int bulklen; dediprog_set_leds(PASS_OFF|BUSY_ON|ERROR_OFF); @@ -300,7 +300,7 @@ } static int dediprog_spi_write_256(struct flashchip *flash, uint8_t *buf, - int start, int len) + unsigned int start, unsigned int len) { int ret; Modified: trunk/dummyflasher.c ============================================================================== --- trunk/dummyflasher.c Sat Nov 19 20:31:17 2011 (r1469) +++ trunk/dummyflasher.c Wed Nov 23 10:13:48 2011 (r1470) @@ -46,24 +46,24 @@ }; static enum emu_chip emu_chip = EMULATE_NONE; static char *emu_persistent_image = NULL; -static int emu_chip_size = 0; +static unsigned int emu_chip_size = 0; #if EMULATE_SPI_CHIP -static int emu_max_byteprogram_size = 0; -static int emu_max_aai_size = 0; -static int emu_jedec_se_size = 0; -static int emu_jedec_be_52_size = 0; -static int emu_jedec_be_d8_size = 0; -static int emu_jedec_ce_60_size = 0; -static int emu_jedec_ce_c7_size = 0; +static unsigned int emu_max_byteprogram_size = 0; +static unsigned int emu_max_aai_size = 0; +static unsigned int emu_jedec_se_size = 0; +static unsigned int emu_jedec_be_52_size = 0; +static unsigned int emu_jedec_be_d8_size = 0; +static unsigned int emu_jedec_ce_60_size = 0; +static unsigned int emu_jedec_ce_c7_size = 0; #endif #endif -static int spi_write_256_chunksize = 256; +static unsigned int spi_write_256_chunksize = 256; static int dummy_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); static int dummy_spi_write_256(struct flashchip *flash, uint8_t *buf, - int start, int len); + unsigned int start, unsigned int len); static const struct spi_programmer spi_programmer_dummyflasher = { .type = SPI_CONTROLLER_DUMMY, @@ -320,8 +320,8 @@ static int emulate_spi_chip_response(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { - int offs; - static int aai_offs; + unsigned int offs; + static int unsigned aai_offs; static int aai_active = 0; if (writecnt == 0) { @@ -549,7 +549,7 @@ } static int dummy_spi_write_256(struct flashchip *flash, uint8_t *buf, - int start, int len) + unsigned int start, unsigned int len) { return spi_write_chunked(flash, buf, start, len, spi_write_256_chunksize); Modified: trunk/flash.h ============================================================================== --- trunk/flash.h Sat Nov 19 20:31:17 2011 (r1469) +++ trunk/flash.h Wed Nov 23 10:13:48 2011 (r1470) @@ -108,9 +108,9 @@ uint32_t model_id; /* Total chip size in kilobytes */ - int total_size; + unsigned int total_size; /* Chip page size in bytes */ - int page_size; + unsigned int page_size; int feature_bits; /* @@ -121,8 +121,10 @@ int (*probe) (struct flashchip *flash); - /* Delay after "enter/exit ID mode" commands in microseconds. */ - int probe_timing; + /* Delay after "enter/exit ID mode" commands in microseconds. + * NB: negative values have special meanings, see TIMING_* below. + */ + signed int probe_timing; /* * Erase blocks and associated erase function. Any chip erase function @@ -143,8 +145,8 @@ int (*printlock) (struct flashchip *flash); int (*unlock) (struct flashchip *flash); - int (*write) (struct flashchip *flash, uint8_t *buf, int start, int len); - int (*read) (struct flashchip *flash, uint8_t *buf, int start, int len); + int (*write) (struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len); + int (*read) (struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len); struct { uint16_t min; uint16_t max; @@ -202,7 +204,7 @@ extern const char flashrom_version[]; extern char *chip_to_probe; void map_flash_registers(struct flashchip *flash); -int read_memmapped(struct flashchip *flash, uint8_t *buf, int start, int len); +int read_memmapped(struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len); int erase_flash(struct flashchip *flash); int probe_flash(int startchip, struct flashchip *fill_flash, int force); int read_flash_to_file(struct flashchip *flash, const char *filename); @@ -210,8 +212,8 @@ int max(int a, int b); void tolower_string(char *str); char *extract_param(char **haystack, const char *needle, const char *delim); -int verify_range(struct flashchip *flash, uint8_t *cmpbuf, int start, int len, const char *message); -int need_erase(uint8_t *have, uint8_t *want, int len, enum write_granularity gran); +int verify_range(struct flashchip *flash, uint8_t *cmpbuf, unsigned int start, unsigned int len, const char *message); +int need_erase(uint8_t *have, uint8_t *want, unsigned int len, enum write_granularity gran); char *strcat_realloc(char *dest, const char *src); void print_version(void); void print_banner(void); Modified: trunk/flashrom.c ============================================================================== --- trunk/flashrom.c Sat Nov 19 20:31:17 2011 (r1469) +++ trunk/flashrom.c Wed Nov 23 10:13:48 2011 (r1470) @@ -412,7 +412,7 @@ flash->virtual_registers = (chipaddr)programmer_map_flash_region("flash chip registers", (0xFFFFFFFF - 0x400000 - size + 1), size); } -int read_memmapped(struct flashchip *flash, uint8_t *buf, int start, int len) +int read_memmapped(struct flashchip *flash, uint8_t *buf, unsigned int start, int unsigned len) { chip_readn(buf, flash->virtual_memory + start, len); @@ -535,7 +535,7 @@ } /* start is an offset to the base address of the flash chip */ -int check_erased_range(struct flashchip *flash, int start, int len) +int check_erased_range(struct flashchip *flash, unsigned int start, unsigned int len) { int ret; uint8_t *cmpbuf = malloc(len); @@ -558,10 +558,10 @@ * @message string to print in the "FAILED" message * @return 0 for success, -1 for failure */ -int verify_range(struct flashchip *flash, uint8_t *cmpbuf, int start, int len, +int verify_range(struct flashchip *flash, uint8_t *cmpbuf, unsigned int start, unsigned int len, const char *message) { - int i; + unsigned int i; uint8_t *readbuf = malloc(len); int ret = 0, failcount = 0; @@ -639,10 +639,10 @@ * @gran write granularity (enum, not count) * @return 0 if no erase is needed, 1 otherwise */ -int need_erase(uint8_t *have, uint8_t *want, int len, enum write_granularity gran) +int need_erase(uint8_t *have, uint8_t *want, unsigned int len, enum write_granularity gran) { int result = 0; - int i, j, limit; + unsigned int i, j, limit; switch (gran) { case write_gran_1bit: @@ -705,11 +705,13 @@ * in relation to the max write length of the programmer and the max write * length of the chip. */ -static int get_next_write(uint8_t *have, uint8_t *want, int len, - int *first_start, enum write_granularity gran) -{ - int need_write = 0, rel_start = 0, first_len = 0; - int i, limit, stride; +static unsigned int get_next_write(uint8_t *have, uint8_t *want, unsigned int len, + unsigned int *first_start, + enum write_granularity gran) +{ + int need_write = 0; + unsigned int rel_start = 0, first_len = 0; + unsigned int i, limit, stride; switch (gran) { case write_gran_1bit: @@ -1030,7 +1032,7 @@ int verify_flash(struct flashchip *flash, uint8_t *buf) { int ret; - int total_size = flash->total_size * 1024; + unsigned int total_size = flash->total_size * 1024; msg_cinfo("Verifying flash... "); @@ -1208,7 +1210,8 @@ unsigned int addr, unsigned int len)) { - int starthere = 0, lenhere = 0, ret = 0, skip = 1, writecount = 0; + unsigned int starthere = 0, lenhere = 0; + int ret = 0, skip = 1, writecount = 0; enum write_granularity gran = write_gran_256bytes; /* FIXME */ /* curcontents and newcontents are opaque to walk_eraseregions, and Modified: trunk/ichspi.c ============================================================================== --- trunk/ichspi.c Sat Nov 19 20:31:17 2011 (r1469) +++ trunk/ichspi.c Wed Nov 23 10:13:48 2011 (r1470) @@ -1278,7 +1278,8 @@ return 0; } -int ich_hwseq_read(struct flashchip *flash, uint8_t *buf, int addr, int len) +int ich_hwseq_read(struct flashchip *flash, uint8_t *buf, unsigned int addr, + unsigned int len) { uint16_t hsfc; uint16_t timeout = 100 * 60; @@ -1315,7 +1316,8 @@ return 0; } -int ich_hwseq_write(struct flashchip *flash, uint8_t *buf, int addr, int len) +int ich_hwseq_write(struct flashchip *flash, uint8_t *buf, unsigned int addr, + unsigned int len) { uint16_t hsfc; uint16_t timeout = 100 * 60; Modified: trunk/it87spi.c ============================================================================== --- trunk/it87spi.c Sat Nov 19 20:31:17 2011 (r1469) +++ trunk/it87spi.c Wed Nov 23 10:13:48 2011 (r1470) @@ -106,9 +106,9 @@ static int it8716f_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); static int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf, - int start, int len); + unsigned int start, unsigned int len); static int it8716f_spi_chip_write_256(struct flashchip *flash, uint8_t *buf, - int start, int len); + unsigned int start, unsigned int len); static const struct spi_programmer spi_programmer_it87xx = { .type = SPI_CONTROLLER_IT87XX, @@ -313,9 +313,10 @@ /* Page size is usually 256 bytes */ static int it8716f_spi_page_program(struct flashchip *flash, uint8_t *buf, - int start) + unsigned int start) { - int i, result; + unsigned int i; + int result; chipaddr bios = flash->virtual_memory; result = spi_write_enable(); @@ -340,7 +341,7 @@ * Need to read this big flash using firmware cycles 3 byte at a time. */ static int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf, - int start, int len) + unsigned int start, unsigned int len) { fast_spi = 0; @@ -358,7 +359,7 @@ } static int it8716f_spi_chip_write_256(struct flashchip *flash, uint8_t *buf, - int start, int len) + unsigned int start, unsigned int len) { /* * IT8716F only allows maximum of 512 kb SPI chip size for memory @@ -374,7 +375,7 @@ (flash->page_size > 256)) { spi_chip_write_1(flash, buf, start, len); } else { - int lenhere; + unsigned int lenhere; if (start % flash->page_size) { /* start to the end of the page or to start + len, Modified: trunk/jedec.c ============================================================================== --- trunk/jedec.c Sat Nov 19 20:31:17 2011 (r1469) +++ trunk/jedec.c Wed Nov 23 10:13:48 2011 (r1470) @@ -91,7 +91,7 @@ msg_cdbg("%s: excessive loops, i=0x%x\n", __func__, i); } -static int getaddrmask(struct flashchip *flash) +static unsigned int getaddrmask(struct flashchip *flash) { switch (flash->feature_bits & FEATURE_ADDR_MASK) { case FEATURE_ADDR_FULL: @@ -355,12 +355,12 @@ } /* chunksize is 1 */ -int write_jedec_1(struct flashchip *flash, uint8_t *src, int start, int len) +int write_jedec_1(struct flashchip *flash, uint8_t *src, unsigned int start, unsigned int len) { int i, failed = 0; chipaddr dst = flash->virtual_memory + start; chipaddr olddst; - int mask; + unsigned int mask; mask = getaddrmask(flash); @@ -376,14 +376,14 @@ return failed; } -int write_page_write_jedec_common(struct flashchip *flash, uint8_t *src, int start, int page_size) +int write_page_write_jedec_common(struct flashchip *flash, uint8_t *src, unsigned int start, unsigned int page_size) { int i, tried = 0, failed; uint8_t *s = src; chipaddr bios = flash->virtual_memory; chipaddr dst = bios + start; chipaddr d = dst; - int mask; + unsigned int mask; mask = getaddrmask(flash); @@ -424,15 +424,15 @@ * This function is a slightly modified copy of spi_write_chunked. * Each page is written separately in chunks with a maximum size of chunksize. */ -int write_jedec(struct flashchip *flash, uint8_t *buf, int start, int len) +int write_jedec(struct flashchip *flash, uint8_t *buf, unsigned int start, int unsigned len) { - int i, starthere, lenhere; + unsigned int i, starthere, lenhere; /* FIXME: page_size is the wrong variable. We need max_writechunk_size * in struct flashchip to do this properly. All chips using * write_jedec have page_size set to max_writechunk_size, so * we're OK for now. */ - int page_size = flash->page_size; + unsigned int page_size = flash->page_size; /* Warning: This loop has a very unusual condition and body. * The loop needs to go through each page with at least one affected @@ -461,7 +461,7 @@ int erase_chip_block_jedec(struct flashchip *flash, unsigned int addr, unsigned int blocksize) { - int mask; + unsigned int mask; mask = getaddrmask(flash); if ((addr != 0) || (blocksize != flash->total_size * 1024)) { @@ -474,7 +474,7 @@ int probe_jedec(struct flashchip *flash) { - int mask; + unsigned int mask; mask = getaddrmask(flash); return probe_jedec_common(flash, mask); @@ -482,7 +482,7 @@ int erase_sector_jedec(struct flashchip *flash, unsigned int page, unsigned int size) { - int mask; + unsigned int mask; mask = getaddrmask(flash); return erase_sector_jedec_common(flash, page, size, mask); @@ -490,7 +490,7 @@ int erase_block_jedec(struct flashchip *flash, unsigned int page, unsigned int size) { - int mask; + unsigned int mask; mask = getaddrmask(flash); return erase_block_jedec_common(flash, page, size, mask); @@ -498,7 +498,7 @@ int erase_chip_jedec(struct flashchip *flash) { - int mask; + unsigned int mask; mask = getaddrmask(flash); return erase_chip_jedec_common(flash, mask); Modified: trunk/linux_spi.c ============================================================================== --- trunk/linux_spi.c Sat Nov 19 20:31:17 2011 (r1469) +++ trunk/linux_spi.c Wed Nov 23 10:13:48 2011 (r1470) @@ -36,10 +36,10 @@ static int linux_spi_shutdown(void *data); static int linux_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *txbuf, unsigned char *rxbuf); -static int linux_spi_read(struct flashchip *flash, uint8_t *buf, int start, - int len); +static int linux_spi_read(struct flashchip *flash, uint8_t *buf, + unsigned int start, unsigned int len); static int linux_spi_write_256(struct flashchip *flash, uint8_t *buf, - int start, int len); + unsigned int start, unsigned int len); static const struct spi_programmer spi_programmer_linux = { .type = SPI_CONTROLLER_LINUX, @@ -131,14 +131,14 @@ return 0; } -static int linux_spi_read(struct flashchip *flash, uint8_t *buf, int start, - int len) +static int linux_spi_read(struct flashchip *flash, uint8_t *buf, + unsigned int start, unsigned int len) { - return spi_read_chunked(flash, buf, start, len, getpagesize()); + return spi_read_chunked(flash, buf, start, len, (unsigned)getpagesize()); } static int linux_spi_write_256(struct flashchip *flash, uint8_t *buf, - int start, int len) + unsigned int start, unsigned int len) { - return spi_write_chunked(flash, buf, start, len, getpagesize() - 4); + return spi_write_chunked(flash, buf, start, len, ((unsigned)getpagesize()) - 4); } Modified: trunk/m29f400bt.c ============================================================================== --- trunk/m29f400bt.c Sat Nov 19 20:31:17 2011 (r1469) +++ trunk/m29f400bt.c Wed Nov 23 10:13:48 2011 (r1470) @@ -28,7 +28,7 @@ functions. */ /* chunksize is 1 */ -int write_m29f400bt(struct flashchip *flash, uint8_t *src, int start, int len) +int write_m29f400bt(struct flashchip *flash, uint8_t *src, unsigned int start, unsigned int len) { int i; chipaddr bios = flash->virtual_memory; Modified: trunk/opaque.c ============================================================================== --- trunk/opaque.c Sat Nov 19 20:31:17 2011 (r1469) +++ trunk/opaque.c Wed Nov 23 10:13:48 2011 (r1470) @@ -53,7 +53,7 @@ return opaque_programmer->probe(flash); } -int read_opaque(struct flashchip *flash, uint8_t *buf, int start, int len) +int read_opaque(struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len) { if (!opaque_programmer->read) { msg_perr("%s called before register_opaque_programmer. " @@ -64,7 +64,7 @@ return opaque_programmer->read(flash, buf, start, len); } -int write_opaque(struct flashchip *flash, uint8_t *buf, int start, int len) +int write_opaque(struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len) { if (!opaque_programmer->write) { msg_perr("%s called before register_opaque_programmer. " Modified: trunk/pm49fl00x.c ============================================================================== --- trunk/pm49fl00x.c Sat Nov 19 20:31:17 2011 (r1469) +++ trunk/pm49fl00x.c Wed Nov 23 10:13:48 2011 (r1470) @@ -22,10 +22,10 @@ #include "flash.h" -static void write_lockbits_49fl00x(chipaddr bios, int size, - unsigned char bits, int block_size) +static void write_lockbits_49fl00x(chipaddr bios, unsigned int size, + unsigned char bits, unsigned int block_size) { - int i, left = size; + unsigned int i, left = size; for (i = 0; left >= block_size; i++, left -= block_size) { /* pm49fl002 */ Modified: trunk/programmer.h ============================================================================== --- trunk/programmer.h Sat Nov 19 20:31:17 2011 (r1469) +++ trunk/programmer.h Wed Nov 23 10:13:48 2011 (r1470) @@ -563,23 +563,23 @@ #define MAX_DATA_WRITE_UNLIMITED 256 struct spi_programmer { enum spi_controller type; - int max_data_read; - int max_data_write; + unsigned int max_data_read; + unsigned int max_data_write; int (*command)(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int (*multicommand)(struct spi_command *cmds); /* Optimized functions for this programmer */ - int (*read)(struct flashchip *flash, uint8_t *buf, int start, int len); - int (*write_256)(struct flashchip *flash, uint8_t *buf, int start, int len); + int (*read)(struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len); + int (*write_256)(struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len); }; extern const struct spi_programmer *spi_programmer; int default_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int default_spi_send_multicommand(struct spi_command *cmds); -int default_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); -int default_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); +int default_spi_read(struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len); +int default_spi_write_256(struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len); void register_spi_programmer(const struct spi_programmer *programmer); /* ichspi.c */ @@ -625,8 +625,8 @@ int max_data_write; /* Specific functions for this programmer */ int (*probe) (struct flashchip *flash); - int (*read) (struct flashchip *flash, uint8_t *buf, int start, int len); - int (*write) (struct flashchip *flash, uint8_t *buf, int start, int len); + int (*read) (struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len); + int (*write) (struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len); int (*erase) (struct flashchip *flash, unsigned int blockaddr, unsigned int blocklen); }; extern const struct opaque_programmer *opaque_programmer; Modified: trunk/serprog.c ============================================================================== --- trunk/serprog.c Sat Nov 19 20:31:17 2011 (r1469) +++ trunk/serprog.c Wed Nov 23 10:13:48 2011 (r1470) @@ -302,8 +302,8 @@ static int serprog_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); -static int serprog_spi_read(struct flashchip *flash, uint8_t *buf, int start, - int len); +static int serprog_spi_read(struct flashchip *flash, uint8_t *buf, + unsigned int start, unsigned int len); static struct spi_programmer spi_programmer_serprog = { .type = SPI_CONTROLLER_SERPROG, .max_data_read = MAX_DATA_READ_UNLIMITED, @@ -822,11 +822,10 @@ * the advantage that it is much faster for most chips, but breaks those with * non-contiguous address space (like AT45DB161D). When spi_read_chunked is * fixed this method can be removed. */ -static int serprog_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) +static int serprog_spi_read(struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len) { - int i; - int cur_len; - const int max_read = spi_programmer_serprog.max_data_read; + unsigned int i, cur_len; + const unsigned int max_read = spi_programmer_serprog.max_data_read; for (i = 0; i < len; i += cur_len) { int ret; cur_len = min(max_read, (len - i)); Modified: trunk/spi.c ============================================================================== --- trunk/spi.c Sat Nov 19 20:31:17 2011 (r1469) +++ trunk/spi.c Wed Nov 23 10:13:48 2011 (r1470) @@ -97,9 +97,9 @@ return result; } -int default_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) +int default_spi_read(struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len) { - int max_data = spi_programmer->max_data_read; + unsigned int max_data = spi_programmer->max_data_read; if (max_data == MAX_DATA_UNSPECIFIED) { msg_perr("%s called, but SPI read chunk size not defined " "on this hardware. Please report a bug at " @@ -109,9 +109,9 @@ return spi_read_chunked(flash, buf, start, len, max_data); } -int default_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) +int default_spi_write_256(struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len) { - int max_data = spi_programmer->max_data_write; + unsigned int max_data = spi_programmer->max_data_write; if (max_data == MAX_DATA_UNSPECIFIED) { msg_perr("%s called, but SPI write chunk size not defined " "on this hardware. Please report a bug at " @@ -121,9 +121,9 @@ return spi_write_chunked(flash, buf, start, len, max_data); } -int spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len) +int spi_chip_read(struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len) { - int addrbase = 0; + unsigned int addrbase = 0; if (!spi_programmer->read) { msg_perr("%s called, but SPI read is unsupported on this " "hardware. Please report a bug at " @@ -160,7 +160,7 @@ * .write_256 = spi_chip_write_1 */ /* real chunksize is up to 256, logical chunksize is 256 */ -int spi_chip_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) +int spi_chip_write_256(struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len) { if (!spi_programmer->write_256) { msg_perr("%s called, but SPI page write is unsupported on this " Modified: trunk/spi25.c ============================================================================== --- trunk/spi25.c Sat Nov 19 20:31:17 2011 (r1469) +++ trunk/spi25.c Wed Nov 23 10:13:48 2011 (r1470) @@ -840,7 +840,7 @@ return ret; } -int spi_byte_program(int addr, uint8_t databyte) +int spi_byte_program(unsigned int addr, uint8_t databyte) { int result; struct spi_command cmds[] = { @@ -875,7 +875,7 @@ return result; } -int spi_nbyte_program(int addr, uint8_t *bytes, int len) +int spi_nbyte_program(unsigned int addr, uint8_t *bytes, unsigned int len) { int result; /* FIXME: Switch to malloc based on len unless that kills speed. */ @@ -950,7 +950,7 @@ return 0; } -int spi_nbyte_read(int address, uint8_t *bytes, int len) +int spi_nbyte_read(unsigned int address, uint8_t *bytes, unsigned int len) { const unsigned char cmd[JEDEC_READ_OUTSIZE] = { JEDEC_READ, @@ -968,12 +968,11 @@ * FIXME: Use the chunk code from Michael Karcher instead. * Each page is read separately in chunks with a maximum size of chunksize. */ -int spi_read_chunked(struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize) +int spi_read_chunked(struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len, unsigned int chunksize) { int rc = 0; - int i, j, starthere, lenhere; - int page_size = flash->page_size; - int toread; + unsigned int i, j, starthere, lenhere, toread; + unsigned int page_size = flash->page_size; /* Warning: This loop has a very unusual condition and body. * The loop needs to go through each page with at least one affected @@ -1008,17 +1007,16 @@ * FIXME: Use the chunk code from Michael Karcher instead. * Each page is written separately in chunks with a maximum size of chunksize. */ -int spi_write_chunked(struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize) +int spi_write_chunked(struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len, unsigned int chunksize) { int rc = 0; - int i, j, starthere, lenhere; + unsigned int i, j, starthere, lenhere, towrite; /* FIXME: page_size is the wrong variable. We need max_writechunk_size * in struct flashchip to do this properly. All chips using * spi_chip_write_256 have page_size set to max_writechunk_size, so * we're OK for now. */ - int page_size = flash->page_size; - int towrite; + unsigned int page_size = flash->page_size; /* Warning: This loop has a very unusual condition and body. * The loop needs to go through each page with at least one affected @@ -1057,9 +1055,10 @@ * (e.g. due to size constraints in IT87* for over 512 kB) */ /* real chunksize is 1, logical chunksize is 1 */ -int spi_chip_write_1(struct flashchip *flash, uint8_t *buf, int start, int len) +int spi_chip_write_1(struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len) { - int i, result = 0; + unsigned int i; + int result = 0; for (i = start; i < start + len; i++) { result = spi_byte_program(i, buf[i - start]); @@ -1072,7 +1071,7 @@ return 0; } -int spi_aai_write(struct flashchip *flash, uint8_t *buf, int start, int len) +int spi_aai_write(struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len) { uint32_t pos = start; int result; Modified: trunk/sst28sf040.c ============================================================================== --- trunk/sst28sf040.c Sat Nov 19 20:31:17 2011 (r1469) +++ trunk/sst28sf040.c Wed Nov 23 10:13:48 2011 (r1470) @@ -76,7 +76,7 @@ } /* chunksize is 1 */ -int write_28sf040(struct flashchip *flash, uint8_t *src, int start, int len) +int write_28sf040(struct flashchip *flash, uint8_t *src, unsigned int start, unsigned int len) { int i; chipaddr bios = flash->virtual_memory; Modified: trunk/sst49lfxxxc.c ============================================================================== --- trunk/sst49lfxxxc.c Sat Nov 19 20:31:17 2011 (r1469) +++ trunk/sst49lfxxxc.c Wed Nov 23 10:13:48 2011 (r1470) @@ -35,7 +35,7 @@ static int write_lockbits_49lfxxxc(struct flashchip *flash, unsigned char bits) { chipaddr registers = flash->virtual_registers; - int i, left = flash->total_size * 1024; + unsigned int i, left = flash->total_size * 1024; unsigned long address; msg_cdbg("\nbios=0x%08lx\n", registers); Modified: trunk/w39.c ============================================================================== --- trunk/w39.c Sat Nov 19 20:31:17 2011 (r1469) +++ trunk/w39.c Wed Nov 23 10:13:48 2011 (r1470) @@ -21,7 +21,7 @@ #include "flash.h" -static int printlock_w39_fwh_block(struct flashchip *flash, int offset) +static int printlock_w39_fwh_block(struct flashchip *flash, unsigned int offset) { chipaddr wrprotect = flash->virtual_registers + offset + 2; uint8_t locking; @@ -59,7 +59,7 @@ return (locking & ((1 << 2) | (1 << 0))) ? -1 : 0; } -static int unlock_w39_fwh_block(struct flashchip *flash, int offset) +static int unlock_w39_fwh_block(struct flashchip *flash, unsigned int offset) { chipaddr wrprotect = flash->virtual_registers + offset + 2; uint8_t locking; @@ -80,7 +80,7 @@ return 0; } -static uint8_t w39_idmode_readb(struct flashchip *flash, int offset) +static uint8_t w39_idmode_readb(struct flashchip *flash, unsigned int offset) { chipaddr bios = flash->virtual_memory; uint8_t val; @@ -127,7 +127,7 @@ return 0; } -static int printlock_w39_common(struct flashchip *flash, int offset) +static int printlock_w39_common(struct flashchip *flash, unsigned int offset) { uint8_t lock; @@ -138,7 +138,7 @@ static int printlock_w39_fwh(struct flashchip *flash) { - int i, total_size = flash->total_size * 1024; + unsigned int i, total_size = flash->total_size * 1024; int ret = 0; /* Print lock status of the complete chip */ @@ -150,7 +150,7 @@ static int unlock_w39_fwh(struct flashchip *flash) { - int i, total_size = flash->total_size * 1024; + unsigned int i, total_size = flash->total_size * 1024; /* Unlock the complete chip */ for (i = 0; i < total_size; i += flash->page_size) Modified: trunk/wbsio_spi.c ============================================================================== --- trunk/wbsio_spi.c Sat Nov 19 20:31:17 2011 (r1469) +++ trunk/wbsio_spi.c Wed Nov 23 10:13:48 2011 (r1470) @@ -62,7 +62,7 @@ static int wbsio_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); -static int wbsio_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); +static int wbsio_spi_read(struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len); static const struct spi_programmer spi_programmer_wbsio = { .type = SPI_CONTROLLER_WBSIO, @@ -194,7 +194,7 @@ return 0; } -static int wbsio_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) +static int wbsio_spi_read(struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len) { return read_memmapped(flash, buf, start, len); } From stefan.tauner at student.tuwien.ac.at Wed Nov 23 10:14:41 2011 From: stefan.tauner at student.tuwien.ac.at (Stefan Tauner) Date: Wed, 23 Nov 2011 10:14:41 +0100 Subject: [flashrom] [PATCH] Unsignify lengths and addresses in chip functions and structs In-Reply-To: <4ECC2E04.6070704@gmx.net> References: <201109180042.p8I0gEYE024377@mail2.student.tuwien.ac.at> <1316390511-31596-1-git-send-email-stefan.tauner@student.tuwien.ac.at> <4EC0436B.2090800@gmx.net> <201111222209.pAMM9fHJ028916@mail2.student.tuwien.ac.at> <4ECC2E04.6070704@gmx.net> Message-ID: <201111230914.pAN9EcBb029388@mail2.student.tuwien.ac.at> On Wed, 23 Nov 2011 00:19:32 +0100 Carl-Daniel Hailfinger wrote: > Am 22.11.2011 23:09 schrieb Stefan Tauner: > > should i commit the attached version? > > Please do, the ack is still valid. thanks, r1470 > I wonder whether we should enable the sign warnings once the cleanups > and remaining conversions are in. The big problem might be platform > (OS/library version) dependent changes which we don't know of, but OTOH > we won't know until we try it. i have been playing around with -Wsign-conversion for this patch... and at least on my gcc version it is way over-sensitive, for example ichspi.c: In function ?ich7_run_opcode?: ichspi.c:742: warning: negative integer implicitly converted to unsigned type that is: temp32 = REGREAD32(ICH7_REG_SPIA) & ~0x00FFFFFF; together with -Werror -Wsign-conversion will probably explode somewhere even if we try hard to get it right on dev platforms. -- Kind regards/Mit freundlichen Gr??en, Stefan Tauner From bobmvg at gmail.com Thu Nov 24 18:03:55 2011 From: bobmvg at gmail.com (Vladimir Monchenko) Date: Thu, 24 Nov 2011 21:03:55 +0400 Subject: [flashrom] SST25LF040A Message-ID: <4ECE78FB.5020800@gmail.com> Hi. I have tested reading, erasing and writing with SPI flash SST25LF040A. All works OK. Report in attachment. Regards, Vladimir Monchenko. -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: flashrom.txt URL: From scheikl.g at aon.at Thu Nov 24 21:16:04 2011 From: scheikl.g at aon.at (Gerhard Scheikl) Date: Thu, 24 Nov 2011 21:16:04 +0100 Subject: [flashrom] P8P67 REV 3.1 - Intel P67 Message-ID: <2954701.tgQrO8RzSh@gerhardpc> description: Motherboard product: P8P67 REV 3.1 vendor: ASUSTeK Computer INC. physical id: 0 version: Rev 1.xx *-firmware description: BIOS vendor: American Megatrends Inc. physical id: 0 version: 1704 date: 06/08/2011 size: 64KiB capacity: 4032KiB capabilities: pci upgrade shadowing cdboot bootselect socketedrom edd int13floppy1200 int13floppy720 int13floppy2880 int5printscreen int9keyboard int14serial int17printer acpi usb biosbootspecification flashrom v0.9.4-r1394 on Linux 3.1.0-030100-meins (x86_64), built with libpci 3.1.7, GCC 4.6.1, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 3432M loops per second, 10 myus = 10 us, 100 myus = 123 us, 1000 myus = 982 us, 10000 myus = 9809 us, 4 myus = 4 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "System manufacturer" DMI string system-product-name: "System Product Name" DMI string system-version: "System Version" DMI string baseboard-manufacturer: "ASUSTeK Computer INC." DMI string baseboard-product-name: "P8P67 REV 3.1" DMI string baseboard-version: "Rev 1.xx" DMI string chassis-type: "Desktop" Found chipset "Intel P67" with PCI ID 8086:1c46. This chipset is marked as untested. If you are using an up-to-date version of flashrom please email a report to flashrom at flashrom.org including a verbose (-V) log. Thank you! Enabling flash write... 0xfff80000/0xffb80000 FWH IDSEL: 0x0 0xfff00000/0xffb00000 FWH IDSEL: 0x0 0xffe80000/0xffa80000 FWH IDSEL: 0x1 0xffe00000/0xffa00000 FWH IDSEL: 0x1 0xffd80000/0xff980000 FWH IDSEL: 0x2 0xffd00000/0xff900000 FWH IDSEL: 0x2 0xffc80000/0xff880000 FWH IDSEL: 0x3 0xffc00000/0xff800000 FWH IDSEL: 0x3 0xff700000/0xff300000 FWH IDSEL: 0x4 0xff600000/0xff200000 FWH IDSEL: 0x5 0xff500000/0xff100000 FWH IDSEL: 0x6 0xff400000/0xff000000 FWH IDSEL: 0x7 0xfff80000/0xffb80000 FWH decode enabled 0xfff00000/0xffb00000 FWH decode enabled 0xffe80000/0xffa80000 FWH decode enabled 0xffe00000/0xffa00000 FWH decode enabled 0xffd80000/0xff980000 FWH decode enabled 0xffd00000/0xff900000 FWH decode enabled 0xffc80000/0xff880000 FWH decode enabled 0xffc00000/0xff800000 FWH decode enabled 0xff700000/0xff300000 FWH decode disabled 0xff600000/0xff200000 FWH decode disabled 0xff500000/0xff100000 FWH decode disabled 0xff400000/0xff000000 FWH decode disabled Maximum FWH chip size: 0x100000 bytes BIOS Lock Enable: disabled, BIOS Write Enable: disabled, BIOS_CNTL is 0x0 Root Complex Register Block address = 0xfed1c000 GCS = 0xc04: BIOS Interface Lock-Down: disabled, BOOT BIOS Straps: 0x3 (LPC) Top Swap : not enabled SPIBAR = 0xfed1c000 + 0x3800 0x04: 0x6008 (HSFS) HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=1, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=0 0x06: 0x0000 (HSFC) HSFC: FGO=0, FCYCLE=0, FDBC=0, SME=0 0x08: 0x00001000 (FADDR) 0x50: 0x00000a0b (FRAP) BMWAG 0x00, BMRAG 0x00, BRWA 0x0a, BRRA 0x0b 0x54: 0x00000000 (FREG0: Flash Descriptor) 0x00000000-0x00000fff is read-only 0x58: 0x03ff0180 (FREG1: BIOS) 0x00180000-0x003fffff is read-write 0x5C: 0x017f0001 (FREG2: Management Engine) 0x00001000-0x0017ffff is locked 0x60: 0x00000fff (FREG3: Gigabit Ethernet) Gigabit Ethernet region is unused. 0x64: 0x00000fff (FREG4: Platform Data) Platform Data region is unused. 0x74: 0x00000000 (PR0) 0x78: 0x00000000 (PR1) 0x7C: 0x00000000 (PR2) 0x80: 0x00000000 (PR3) 0x84: 0x00000000 (PR4) 0x90: 0x84 (SSFS) SSFS: SCIP=0, FDONE=1, FCERR=0, AEL=0 0x91: 0xf80000 (SSFC) SSFC: SCGO=0, ACS=0, SPOP=0, COP=0, DBC=0, SME=0, SCF=0 0x94: 0x0006 (PREOP) 0x96: 0x043b (OPTYPE) 0x98: 0x05200302 (OPMENU) 0x9C: 0x0000019f (OPMENU+4) 0xA0: 0x00000000 (BBAR) 0xD0: 0x00000000 (FPB) Programming OPCODES... program_opcodes: preop=5006 optype=463b opmenu=05d80302c79f0190 done preop0=0x06, preop1=0x50 op[0]=0x02, 3, 0 op[1]=0x03, 2, 0 op[2]=0xd8, 3, 0 op[3]=0x05, 0, 0 op[4]=0x90, 2, 0 op[5]=0x01, 1, 0 op[6]=0x9f, 0, 0 op[7]=0xc7, 1, 0 SPI Read Configuration: prefetching disabled, caching enabled, OK. This chipset supports the following protocols: FWH, SPI. Probing for AMIC A25L05PT, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L05PU, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L10PT, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L10PU, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L20PT, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L20PU, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L40PT, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L40PU, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L80P, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L16PT, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L16PU, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L512, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L010, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L020, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L040, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L080, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L016, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L032, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25LQ032, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT25DF021, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT25DF041A, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT25DF081, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT25DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT25DF161, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT25DF321, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT25DF321A, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT25DF641, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT25DQ161, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT25F512B, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT25FS010, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT25FS040, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT26DF041, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT26DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT26DF161, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT26DF161A, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT26F004, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT45CS1282, 16896 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT45DB011D, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT45DB021D, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT45DB041D, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT45DB081D, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT45DB161D, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT45DB321C, 4224 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT45DB321D, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT45DB642D, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for EMST F25L008A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B05, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B05T, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B10T, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B20T, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B40T, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B80T, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B16T, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B32T, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B64T, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25F05, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25F10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25F20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25F40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25F80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25F16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25F32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25Q40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25Q80(A), 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25Q32(A/B), 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25QH16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0x4c, id2 0x57, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX25L512, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Macronix MX25L1005, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Macronix MX25L2005, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Macronix MX25L4005, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Macronix MX25L8005, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Macronix MX25L1605, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Macronix MX25L1635D, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Macronix MX25L1635E, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Macronix MX25L3205, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Chip status register is 00 Chip status register: Status Register Write Disable (SRWD) is not set Chip status register: Bit 6 is not set Chip status register: Bit 5 / Block Protect 3 (BP3) is not set Chip status register: Bit 4 / Block Protect 2 (BP2) is not set Chip status register: Bit 3 / Block Protect 1 (BP1) is not set Chip status register: Bit 2 / Block Protect 0 (BP0) is not set Chip status register: Write Enable Latch (WEL) is not set Chip status register: Write In Progress (WIP/BUSY) is not set Found Macronix flash chip "MX25L3205" (4096 kB, SPI) at physical address 0xffc00000. Probing for Macronix MX25L3235D, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Macronix MX25L6405, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Macronix MX25L12805, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Numonyx M25PE10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Numonyx M25PE20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Numonyx M25PE40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Numonyx M25PE80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Numonyx M25PE16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for PMC Pm25LV010, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for PMC Pm25LV016B, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for PMC Pm25LV020, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for PMC Pm25LV040, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for PMC Pm25LV080B, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for PMC Pm25LV512, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for Sanyo LF25FW203A, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0x4c, id2 0x57, id1 is normal flash content, id2 is normal flash content Probing for Spansion S25FL004A, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Spansion S25FL008A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Spansion S25FL016A, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Spansion S25FL032A, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Spansion S25FL064A, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for SST SST25VF010.REMS, 128 kB: probe_spi_rems: id1 0xc2, id2 0x15 Probing for SST SST25VF016B, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for SST SST25VF032B, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for SST SST25VF064C, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for SST SST25VF040.REMS, 512 kB: probe_spi_rems: id1 0xc2, id2 0x15 Probing for SST SST25VF040B, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for SST SST25LF040A.RES, 512 kB: program_opcodes: preop=5006 optype=462b opmenu=05ab0302c79f0190 on-the-fly OPCODE (0xAB) re-programmed, op-pos=2 probe_spi_res2: id1 0x15, id2 0x15 Probing for SST SST25VF040B.REMS, 512 kB: probe_spi_rems: id1 0xc2, id2 0x15 Probing for SST SST25VF080B, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0x6c, id2 0x52, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0x4c, id2 0x57, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0x4c, id2 0x57, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 kB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0x3a, id2 0xfb, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M25P05-A, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for ST M25P05.RES, 64 kB: Ignoring RES in favour of RDID. Probing for ST M25P10-A, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for ST M25P10.RES, 128 kB: Ignoring RES in favour of RDID. Probing for ST M25P20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for ST M25P40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for ST M25P40-old, 512 kB: Ignoring RES in favour of RDID. Probing for ST M25P80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for ST M25P16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for ST M25P32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for ST M25P64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for ST M25P128, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for ST M25PX16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for ST M25PX32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for ST M25PX64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0x4c, id2 0x57, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0x4c, id2 0x57, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 kB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0x3a, id2 0xfb, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0x4c, id2 0x57, id1 is normal flash content, id2 is normal flash content Probing for Winbond W25Q80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Winbond W25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Winbond W25Q32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Winbond W25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Winbond W25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Winbond W25X10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Winbond W25X20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Winbond W25X40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Winbond W25X80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Winbond W25X16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Winbond W25X32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Winbond W25X64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0x4c, id2 0x57, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for AMIC unknown AMIC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel unknown Atmel SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon unknown Eon SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Macronix unknown Macronix SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for PMC unknown PMC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for SST unknown SST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for ST unknown ST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Sanyo unknown Sanyo SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Generic unknown SPI chip (RDID), 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Generic unknown SPI chip (REMS), 0 kB: probe_spi_rems: id1 0xc2, id2 0x15 No operations were specified. Restoring MMIO space at 0x7f549377f8a0 Restoring MMIO space at 0x7f549377f89c Restoring MMIO space at 0x7f549377f898 Restoring MMIO space at 0x7f549377f896 Restoring MMIO space at 0x7f549377f894 Restoring PCI config space for 00:1f:0 reg 0xdc From c-d.hailfinger.devel.2006 at gmx.net Fri Nov 25 10:53:48 2011 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Fri, 25 Nov 2011 10:53:48 +0100 Subject: [flashrom] [PATCH] Speed up dediprog writes Message-ID: <4ECF65AC.7090803@gmx.net> Totally untested patch, may exhaust the write limit of your flash chip or cause other weirdnesses. Don't blame me. Yes, there is other dediprog stuff in that patch as well. Need to finish that, but right now I need testers. If it works, all chips which use spi_chip_write_256 should be written at native speed. Chips using spi_chip_write_1 or spi_chip_write_aai will still be slow. Signed-off-by: Carl-Daniel Hailfinger Index: flashrom-dediprog_unknown_commands/dediprog.c =================================================================== --- flashrom-dediprog_unknown_commands/dediprog.c (Revision 1470) +++ flashrom-dediprog_unknown_commands/dediprog.c (Arbeitskopie) @@ -30,6 +30,7 @@ static usb_dev_handle *dediprog_handle; static int dediprog_firmwareversion; static int dediprog_endpoint; +static int dediprog_firmwareversion; #if 0 /* Might be useful for other pieces of code as well. */ @@ -299,22 +300,109 @@ return 0; } +/* Bulk write interface, will read multiple page_size byte chunks aligned to page_size bytes. + * @start start address + * @len length + * @return 0 on success, 1 on failure + */ +static int dediprog_spi_bulk_write(struct flashchip *flash, uint8_t *buf, + unsigned int start, unsigned int len) +{ + int ret; + unsigned int i; + /* USB transfer size must be 512, other sizes will NOT work at all. + * chunksize is the real data size per USB bulk transfer. The remaining + * space in a USB bulk transfer must be filled with 0xff padding. + */ + const unsigned int chunksize = flash->page_size; + const unsigned int count = len / chunksize; + const char count_and_chunk[] = {count & 0xff, + (count >> 8) & 0xff, + chunksize & 0xff, + (chunksize >> 8) & 0xff}; + char usbbuf[512]; + + if ((start % chunksize) || (len % chunksize)) { + msg_perr("%s: Unaligned start=%i, len=%i! Please report a bug " + "at flashrom at flashrom.org\n", __func__, start, len); + return 1; + } + + /* No idea if the hardware can handle empty writes, so chicken out. */ + if (!len) + return 0; + /* Command Write SPI Bulk. No idea which write command is used on the + * SPI side. + */ + ret = usb_control_msg(dediprog_handle, 0x42, 0x30, start % 0x10000, + start / 0x10000, (char *)count_and_chunk, + sizeof(count_and_chunk), DEFAULT_TIMEOUT); + if (ret != sizeof(count_and_chunk)) { + msg_perr("Command Write SPI Bulk failed, %i %s!\n", ret, + usb_strerror()); + return 1; + } + + for (i = 0; i < count; i++) { + memset(usbbuf, 0xff, sizeof(usbbuf)); + memcpy(usbbuf, buf + i * chunksize, chunksize); + ret = usb_bulk_write(dediprog_handle, dediprog_endpoint, + usbbuf, 512, + DEFAULT_TIMEOUT); + if (ret != 512) { + msg_perr("SPI bulk write failed, expected %i, got %i " + "%s!\n", 512, ret, usb_strerror()); + return 1; + } + } + + return 0; +} + static int dediprog_spi_write_256(struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len) { int ret; + const unsigned int chunksize = flash->page_size; + unsigned int residue = start % chunksize ? chunksize - start % chunksize : 0; + unsigned int bulklen; dediprog_set_leds(PASS_OFF|BUSY_ON|ERROR_OFF); - /* No idea about the real limit. Maybe 12, maybe more, maybe less. */ - ret = spi_write_chunked(flash, buf, start, len, 12); + if (residue) { + msg_pdbg("Slow write for partial block from 0x%x, length 0x%x\n", + start, residue); + /* No idea about the real limit. Maybe 12, maybe more. */ + ret = spi_write_chunked(flash, buf, start, residue, 12); + if (ret) { + dediprog_set_leds(PASS_OFF|BUSY_OFF|ERROR_ON); + return ret; + } + } - if (ret) + /* Round down. */ + bulklen = (len - residue) / chunksize * chunksize; + ret = dediprog_spi_bulk_write(flash, buf + residue, start + residue, + bulklen); + if (ret) { dediprog_set_leds(PASS_OFF|BUSY_OFF|ERROR_ON); - else - dediprog_set_leds(PASS_ON|BUSY_OFF|ERROR_OFF); + return ret; + } - return ret; + len -= residue + bulklen; + if (len) { + msg_pdbg("Slow write for partial block from 0x%x, length 0x%x\n", + start, len); + ret = spi_write_chunked(flash, buf + residue + bulklen, + start + residue + bulklen, len, 12); + if (ret) { + dediprog_set_leds(PASS_OFF|BUSY_OFF|ERROR_ON); + return ret; + } + } + + dediprog_set_leds(PASS_ON|BUSY_OFF|ERROR_OFF); + return 0; } static int dediprog_spi_send_command(unsigned int writecnt, unsigned int readcnt, @@ -491,8 +579,80 @@ } return 0; } + +/* Start/stop blinking? + * Present in eng_detect_blink.log with firmware 3.1.8 + * Preceded by Command J + */ +static int dediprog_command_g(void) +{ + int ret; + + ret = usb_control_msg(dediprog_handle, 0x42, 0x07, 0x09, 0x03, NULL, 0x0, DEFAULT_TIMEOUT); + if (ret != 0x0) { + msg_perr("Command G failed (%s)!\n", usb_strerror()); + return 1; + } + return 0; +} + +/* Something. + * Present in all logs with firmware 5.1.5 + * Always preceded by Command Receive Device String + * Always followed by Command Set SPI Voltage nonzero + */ +static int dediprog_command_h(void) +{ + int ret; + + ret = usb_control_msg(dediprog_handle, 0x42, 0x07, 0x09, 0x05, NULL, 0x0, DEFAULT_TIMEOUT); + if (ret != 0x0) { + msg_perr("Command H failed (%s)!\n", usb_strerror()); + return 1; + } + return 0; +} #endif +/* Shutdown for firmware 5.x? + * Present in all logs with firmware 5.1.5 + * Often preceded by a SPI operation (Command Read SPI Bulk or Receive SPI) + * Always followed by Command Set SPI Voltage 0x0000 + */ +static int dediprog_command_i(void) +{ + int ret; + + ret = usb_control_msg(dediprog_handle, 0x42, 0x07, 0x09, 0x06, NULL, 0x0, DEFAULT_TIMEOUT); + if (ret != 0x0) { + msg_perr("Command I failed (%s)!\n", usb_strerror()); + return 1; + } + return 0; +} + +#if 0 +/* Start/stop blinking? + * Present in all logs with firmware 5.1.5 + * Always preceded by Command Receive Device String on 5.1.5 + * Always followed by Command Set SPI Voltage nonzero on 5.1.5 + * Present in eng_detect_blink.log with firmware 3.1.8 + * Preceded by Command B in eng_detect_blink.log + * Followed by Command G in eng_detect_blink.log + */ +static int dediprog_command_j(void) +{ + int ret; + + ret = usb_control_msg(dediprog_handle, 0x42, 0x07, 0x09, 0x07, NULL, 0x0, DEFAULT_TIMEOUT); + if (ret != 0x0) { + msg_perr("Command J failed (%s)!\n", usb_strerror()); + return 1; + } + return 0; +} +#endif + static int parse_voltage(char *voltage) { char *tmp = NULL; @@ -555,6 +715,11 @@ { msg_pspew("%s\n", __func__); + /* Shutdown on firmware 5.x */ + if (dediprog_firmwareversion == 5) + if (dediprog_command_i()) + return 1; + /* URB 28. Command Set SPI Voltage to 0. */ if (dediprog_set_spi_voltage(0x0)) return 1; -- http://www.hailfinger.org/ From thomas.kurkowski at gmx.de Fri Nov 25 10:01:31 2011 From: thomas.kurkowski at gmx.de (Thomas Kurkowski) Date: Fri, 25 Nov 2011 10:01:31 +0100 Subject: [flashrom] dediprog speedup Message-ID: <20111125090131.169110@gmx.net> http://paste.flashrom.org/view.php?id=919 -- Empfehlen Sie GMX DSL Ihren Freunden und Bekannten und wir belohnen Sie mit bis zu 50,- Euro! https://freundschaftswerbung.gmx.de From frigolit at frigolit.net Fri Nov 25 17:10:21 2011 From: frigolit at frigolit.net (Pontus Rodling) Date: Fri, 25 Nov 2011 17:10:21 +0100 Subject: [flashrom] Intel H57 chipset (untested) and W25Q64 flash -V output Message-ID: <4ECFBDED.1040701@frigolit.net> Hi! flashrom told me to send you guys this, so here it is. I'm getting a transaction error when trying to read the (fully supported according to the wiki) W25Q64 flash chip on a Intel H57 chipset which is marked as untested. I tried both using swseq and hwseq. Both results are attached. // Pontus Rodling -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: flashrom-intel_h57-swseq.txt URL: -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: flashrom-intel_h57-hwseq.txt URL: From david.hendricks at gmail.com Sat Nov 26 07:44:40 2011 From: david.hendricks at gmail.com (David Hendricks) Date: Fri, 25 Nov 2011 22:44:40 -0800 Subject: [flashrom] Intel H57 chipset (untested) and W25Q64 flash -V output In-Reply-To: <4ECFBDED.1040701@frigolit.net> References: <4ECFBDED.1040701@frigolit.net> Message-ID: On Fri, Nov 25, 2011 at 8:10 AM, Pontus Rodling wrote: > Hi! > flashrom told me to send you guys this, so here it is. > > I'm getting a transaction error when trying to read the (fully supported > according to the wiki) W25Q64 flash chip on a Intel H57 chipset which is > marked as untested. > I tried both using swseq and hwseq. Both results are attached. > Looks like the Management Engine region is totally locked (from both reads and writes), so it will fail whenever flashrom tries to read/write in that region; 0x5C: 0x05ff0001 (FREG2: Management Engine) 0x00001000-0x005fffff is locked We need to do some rather ugly stuff to hack around that. I have a very ugly hack that applies to the Chromium OS branch you can try: # clone chromium os branch of flashrom git clone http://git.chromium.org/chromiumos/third_party/flashrom.gitflashrom-cros && cd flashrom-cros # apply patch from https://gerrit.chromium.org/gerrit/#change,12117 git pull https://gerrit.chromium.org/gerrit/p/chromiumos/third_party/flashromrefs/changes/17/12117/1 With that patch, flashrom will fill in unreadable parts with 0xff bytes, and will not attempt to erase/write those parts. Verbose output will show "WD" (Write Denied) for regions that are unwriteable. -------------- next part -------------- An HTML attachment was scrubbed... URL: From stefan.tauner at student.tuwien.ac.at Sat Nov 26 23:42:44 2011 From: stefan.tauner at student.tuwien.ac.at (Stefan Tauner) Date: Sat, 26 Nov 2011 23:42:44 +0100 Subject: [flashrom] Intel H57 chipset (untested) and W25Q64 flash -V output In-Reply-To: <4ECFBDED.1040701@frigolit.net> References: <4ECFBDED.1040701@frigolit.net> Message-ID: <201111262242.pAQMgPsd019675@mail2.student.tuwien.ac.at> On Fri, 25 Nov 2011 17:10:21 +0100 Pontus Rodling wrote: > 0x5C: 0x05ff0001 (FREG2: Management Engine) > 0x00001000-0x005fffff is locked Hello Pontus, thanks for your report! The problem is the locked ME region as quoted above and mentioned by david before. We are working on unlocking it, but intel does not provide us any documentation so please do not expect a real solution soon. The workaround used in chromiumos' version of flashrom is to not touch the locked region at all. But since it contains another hunk of the firmware it might brick a board when one updates the bios, but not the ME region. We do not know if this might really be the case, but i would not want to try it without a safety net. I have added the board (MS-7613 (Iona-GL8E)) to our list of (un)supported boards (with an appropriate note) and will commit that later together with other small changes. -- Kind regards/Mit freundlichen Gr??en, Stefan Tauner From stefan.tauner at student.tuwien.ac.at Sat Nov 26 23:53:35 2011 From: stefan.tauner at student.tuwien.ac.at (Stefan Tauner) Date: Sat, 26 Nov 2011 23:53:35 +0100 Subject: [flashrom] P8P67 REV 3.1 - Intel P67 In-Reply-To: <2954701.tgQrO8RzSh@gerhardpc> References: <2954701.tgQrO8RzSh@gerhardpc> Message-ID: <201111262253.pAQMrHgO025645@mail2.student.tuwien.ac.at> On Thu, 24 Nov 2011 21:16:04 +0100 Gerhard Scheikl wrote: > 0x5C: 0x017f0001 (FREG2: Management Engine) > 0x00001000-0x0017ffff is locked Hello Gerhard, thanks for your report! In case you have not tried yet: that mainboard will not work with any version of flashrom so far. The problem is the locked ME region as quoted above. We are working on unlocking it, but intel does not provide us any documentation so please do not expect a solution soon. I have added the board to our list of (un)supported boards (with an appropriate note) and will commit that later together with other small changes. -- Kind regards/Mit freundlichen Gr??en, Stefan Tauner From stefan.tauner at student.tuwien.ac.at Sat Nov 26 23:56:53 2011 From: stefan.tauner at student.tuwien.ac.at (Stefan Tauner) Date: Sat, 26 Nov 2011 23:56:53 +0100 Subject: [flashrom] SST25LF040A In-Reply-To: <4ECE78FB.5020800@gmail.com> References: <4ECE78FB.5020800@gmail.com> Message-ID: <201111262256.pAQMuYkG027490@mail2.student.tuwien.ac.at> On Thu, 24 Nov 2011 21:03:55 +0400 Vladimir Monchenko wrote: > Hi. > > I have tested reading, erasing and writing with SPI flash SST25LF040A. > All works OK. > > Report in attachment. > > Regards, Vladimir Monchenko. Hello Vladimir, that chip has already been marked as fully tested (in r1431). Thanks for your report anyway! -- Kind regards/Mit freundlichen Gr??en, Stefan Tauner From stefan.tauner at student.tuwien.ac.at Sat Nov 26 23:53:35 2011 From: stefan.tauner at student.tuwien.ac.at (Stefan Tauner) Date: Sat, 26 Nov 2011 23:53:35 +0100 Subject: [flashrom] P8P67 REV 3.1 - Intel P67 In-Reply-To: <2954701.tgQrO8RzSh@gerhardpc> References: <2954701.tgQrO8RzSh@gerhardpc> Message-ID: <201111262253.pAQMrHgO025645@mail2.student.tuwien.ac.at> On Thu, 24 Nov 2011 21:16:04 +0100 Gerhard Scheikl wrote: > 0x5C: 0x017f0001 (FREG2: Management Engine) > 0x00001000-0x0017ffff is locked Hello Gerhard, thanks for your report! In case you have not tried yet: that mainboard will not work with any version of flashrom so far. The problem is the locked ME region as quoted above. We are working on unlocking it, but intel does not provide us any documentation so please do not expect a solution soon. I have added the board to our list of (un)supported boards (with an appropriate note) and will commit that later together with other small changes. -- Kind regards/Mit freundlichen Gr??en, Stefan Tauner From stefan.tauner at student.tuwien.ac.at Sun Nov 27 00:35:43 2011 From: stefan.tauner at student.tuwien.ac.at (Stefan Tauner) Date: Sun, 27 Nov 2011 00:35:43 +0100 Subject: [flashrom] [PATCH] ichspi.c: warn user when a protected region is detected In-Reply-To: <1319150349-24326-1-git-send-email-stefan.tauner@student.tuwien.ac.at> References: <1319150349-24326-1-git-send-email-stefan.tauner@student.tuwien.ac.at> Message-ID: <1322350543-6883-1-git-send-email-stefan.tauner@student.tuwien.ac.at> This includes the notorious read-only flash descriptors and locked ME regions. --- non-verbose sample output from my laptop: [?] Found chipset "Intel QS57". Enabling flash write... WARNING: SPI Configuration Lockdown activated. WARNING: Flash Descriptor region is not fully accessible and flashrom can not deal with this correctly yet. Intel does not provide us the necessary documention to support this. Please send a verbose log to flashrom at flashrom.org if this board is not listed on http://flashrom.org/Supported_hardware#Supported_mainboards yet. WARNING: Management Engine region is not fully accessible and flashrom can not deal with this correctly yet. Intel does not provide us the necessary documention to support this. Please send a verbose log to flashrom at flashrom.org if this board is not listed on http://flashrom.org/Supported_hardware#Supported_mainboards yet. OK. Found Winbond flash chip "W25X64" (8192 kB, SPI) at physical address 0xff800000. [?] Signed-off-by: Stefan Tauner --- ichspi.c | 9 +++++++++ 1 files changed, 9 insertions(+), 0 deletions(-) diff --git a/ichspi.c b/ichspi.c index 78cdb3b..4bd04d0 100644 --- a/ichspi.c +++ b/ichspi.c @@ -1447,6 +1447,15 @@ static void do_ich9_spi_frap(uint32_t frap, int i) msg_pdbg("0x%08x-0x%08x is %s\n", base, (limit | 0x0fff), access_names[rwperms]); + if (rwperms != 0x3) + msg_pinfo("WARNING: %s region is not fully accessible and " + "flashrom can\nnot deal with this correctly yet. " + "Intel does not provide us the necessary\n" + "documention to support this. Please send a verbose " + "log to\nflashrom at flashrom.org if this board is not " + "listed on\n" + "http://flashrom.org/Supported_hardware#Supported_mainboards " + "yet.\n", region_names[i]); } /* In contrast to FRAP and the master section of the descriptor the bits -- 1.7.1 From david.hendricks at gmail.com Sun Nov 27 20:48:51 2011 From: david.hendricks at gmail.com (David Hendricks) Date: Sun, 27 Nov 2011 11:48:51 -0800 Subject: [flashrom] [PATCH] ichspi.c: warn user when a protected region is detected In-Reply-To: <1322350543-6883-1-git-send-email-stefan.tauner@student.tuwien.ac.at> References: <1319150349-24326-1-git-send-email-stefan.tauner@student.tuwien.ac.at> <1322350543-6883-1-git-send-email-stefan.tauner@student.tuwien.ac.at> Message-ID: On Sat, Nov 26, 2011 at 3:35 PM, Stefan Tauner < stefan.tauner at student.tuwien.ac.at> wrote: > This includes the notorious read-only flash descriptors and locked ME > regions. > --- > non-verbose sample output from my laptop: > [?] > Found chipset "Intel QS57". Enabling flash write... WARNING: SPI > Configuration Lockdown activated. > WARNING: Flash Descriptor region is not fully accessible and flashrom can > not deal with this correctly yet. Intel does not provide us the necessary > documention to support this. To be fair, I think Intel documents it fine. I think what we've got to do is checking the flash descriptor override pin strap status (FDOPSS). If it is cleared then we can ignore the descriptor, otherwise if it is set then we need to avoid locked regions. It's really just a pain in the ass and, as you pointed out, may leave the BIOS/ME firmware blobs in an inconsistent or incompatible state. So the onus is on the user to ensure a safe upgrade path if only part of the ROM can be updated. It's probably worth displaying a warning and requiring "--force" or something in that scenario. -------------- next part -------------- An HTML attachment was scrubbed... URL: From stefan.tauner at student.tuwien.ac.at Sun Nov 27 22:27:16 2011 From: stefan.tauner at student.tuwien.ac.at (Stefan Tauner) Date: Sun, 27 Nov 2011 22:27:16 +0100 Subject: [flashrom] [PATCH] ichspi.c: warn user when a protected region is detected In-Reply-To: References: <1319150349-24326-1-git-send-email-stefan.tauner@student.tuwien.ac.at> <1322350543-6883-1-git-send-email-stefan.tauner@student.tuwien.ac.at> Message-ID: <201111272126.pARLQqhm027641@mail2.student.tuwien.ac.at> On Sun, 27 Nov 2011 11:48:51 -0800 David Hendricks wrote: > On Sat, Nov 26, 2011 at 3:35 PM, Stefan Tauner < > stefan.tauner at student.tuwien.ac.at> wrote: > > > This includes the notorious read-only flash descriptors and locked ME > > regions. > > --- > > non-verbose sample output from my laptop: > > [?] > > Found chipset "Intel QS57". Enabling flash write... WARNING: SPI > > Configuration Lockdown activated. > > WARNING: Flash Descriptor region is not fully accessible and flashrom can > > not deal with this correctly yet. Intel does not provide us the necessary > > documention to support this. > > > To be fair, I think Intel documents it fine. That depends on what 'it' is. The limitations and the influence of FDOPSS on that limitation are well defined in public documentation. But the unlocking process is not documented at all publicly. We know from different leaked documents and also from the fact that vendor tools exist, that unlocking can be done by software only and without touching the FDOPSS pin by sending the "HMRFPO Enable" command via HECI/MEI to the ME. The details are documented in the BIOS writer guide(s) (which are "restricted secret" level(?)) > I think what we've got to do > is checking the flash descriptor override pin strap status (FDOPSS). If it > is cleared then we can ignore the descriptor, otherwise if it is set then > we need to avoid locked regions. I would not call it 'ignoring'. We should be aware, that the limitation do not apply (we do print a message to the user already in that case), but we could and should use the regions where it makes sense (e.g. automatic creation of layout (file)s. > It's really just a pain in the ass and, as you pointed out, may leave the > BIOS/ME firmware blobs in an inconsistent or incompatible state. So the > onus is on the user to ensure a safe upgrade path if only part of the ROM > can be updated. It's probably worth displaying a warning and requiring > "--force" or something in that scenario. As a first step yes. IIRC i have sent a patch that does that when active PR protections are found(?), but i think it is not in/reviewed yet. I agree, we should set write_allowed = 0 (or whatever it was) and rephrase the warning to include that. -- Kind regards/Mit freundlichen Gr??en, Stefan Tauner From fuckner at deltacomputer.de Mon Nov 28 09:34:26 2011 From: fuckner at deltacomputer.de (Michael Fuckner) Date: Mon, 28 Nov 2011 09:34:26 +0100 Subject: [flashrom] Supermicro X8DTE-F Message-ID: <4ED34792.4040502@deltacomputer.de> Hi all, I have a lot of supermicro boards/ systems at hand and I first tried it this morning and it worked with X8DTE-F, so it will most likely also work with X8DT6 (same bios file). Do you also need flashrom -V or -z? I hope I have some time to test other boards available. Regards, Michael! test131:/media/flashrom # ./flashrom -w ~/x8dt61.830 flashrom v0.9.4-r1470 on Linux 3.1.0-1.2-default (x86_64), built with libpci 3.1.7, GCC 4.6.2, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. Found chipset "Intel ICH10R". Enabling flash write... OK. Found Macronix flash chip "MX25L3205" (4096 kB, SPI) at physical address 0xffc00000. Flash image seems to be a legacy BIOS. Disabling coreboot-related checks. Reading old flash chip contents... done. Erasing and writing flash chip... Erase/write done. Verifying flash... VERIFIED. test131:/media/flashrom # From fabio.capoeira at bol.com.br Tue Nov 29 00:22:08 2011 From: fabio.capoeira at bol.com.br (Fabio) Date: Mon, 28 Nov 2011 21:22:08 -0200 Subject: [flashrom] "Intel H61" with PCI ID 8086:1c5c. including a verbose (-V) log Message-ID: <20111128212208.5c7fca81@bol.com.br> [studio at myhost ~]$ sudo flashrom -V flashrom v0.9.4-r1395 on Linux 3.0-rt (i686), built with libpci 3.1.8, GCC 4.6.2, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 2868M loops per second, 10 myus = 9 us, 100 myus = 98 us, 1000 myus = 972 us, 10000 myus = 10144 us, 4 myus = 6 us, OK. Initializing internal programmer No coreboot table found. sh: dmidecode: comando n?o encontrado dmidecode execution unsuccessful - continuing without DMI info Found chipset "Intel H61" with PCI ID 8086:1c5c. This chipset is marked as untested. If you are using an up-to-date version of flashrom please email a report to flashrom at flashrom.org including a verbose (-V) log. Thank you! Enabling flash write... 0xfff80000/0xffb80000 FWH IDSEL: 0x0 0xfff00000/0xffb00000 FWH IDSEL: 0x0 0xffe80000/0xffa80000 FWH IDSEL: 0x1 0xffe00000/0xffa00000 FWH IDSEL: 0x1 0xffd80000/0xff980000 FWH IDSEL: 0x2 0xffd00000/0xff900000 FWH IDSEL: 0x2 0xffc80000/0xff880000 FWH IDSEL: 0x3 0xffc00000/0xff800000 FWH IDSEL: 0x3 0xff700000/0xff300000 FWH IDSEL: 0x4 0xff600000/0xff200000 FWH IDSEL: 0x5 0xff500000/0xff100000 FWH IDSEL: 0x6 0xff400000/0xff000000 FWH IDSEL: 0x7 0xfff80000/0xffb80000 FWH decode enabled 0xfff00000/0xffb00000 FWH decode enabled 0xffe80000/0xffa80000 FWH decode enabled 0xffe00000/0xffa00000 FWH decode enabled 0xffd80000/0xff980000 FWH decode disabled 0xffd00000/0xff900000 FWH decode disabled 0xffc80000/0xff880000 FWH decode disabled 0xffc00000/0xff800000 FWH decode disabled 0xff700000/0xff300000 FWH decode disabled 0xff600000/0xff200000 FWH decode disabled 0xff500000/0xff100000 FWH decode disabled 0xff400000/0xff000000 FWH decode disabled Maximum FWH chip size: 0x100000 bytes BIOS Lock Enable: disabled, BIOS Write Enable: disabled, BIOS_CNTL is 0x0 Root Complex Register Block address = 0xfed1c000 GCS = 0xc24: BIOS Interface Lock-Down: disabled, BOOT BIOS Straps: 0x3 (LPC) Top Swap : not enabled SPIBAR = 0xfed1c000 + 0x3800 0x04: 0x6008 (HSFS) HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=1, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=0 0x06: 0x0000 (HSFC) HSFC: FGO=0, FCYCLE=0, FDBC=0, SME=0 0x08: 0x00000000 (FADDR) 0x50: 0x0000ffff (FRAP) BMWAG 0x00, BMRAG 0x00, BRWA 0xff, BRRA 0xff 0x54: 0x00000000 (FREG0: Flash Descriptor) 0x00000000-0x00000fff is read-write 0x58: 0x03ff0200 (FREG1: BIOS) 0x00200000-0x003fffff is read-write 0x5C: 0x01ff0001 (FREG2: Management Engine) 0x00001000-0x001fffff is read-write 0x60: 0x00000fff (FREG3: Gigabit Ethernet) Gigabit Ethernet region is unused. 0x64: 0x00000fff (FREG4: Platform Data) Platform Data region is unused. 0x74: 0x00000000 (PR0) 0x78: 0x00000000 (PR1) 0x7C: 0x00000000 (PR2) 0x80: 0x00000000 (PR3) 0x84: 0x00000000 (PR4) 0x90: 0x84 (SSFS) SSFS: SCIP=0, FDONE=1, FCERR=0, AEL=0 0x91: 0xf84140 (SSFC) SSFC: SCGO=0, ACS=0, SPOP=0, COP=4, DBC=1, SME=0, SCF=0 0x94: 0x0006 (PREOP) 0x96: 0x043b (OPTYPE) 0x98: 0x05200302 (OPMENU) 0x9C: 0x0000019f (OPMENU+4) 0xA0: 0x00000000 (BBAR) 0xD0: 0x00000000 (FPB) Programming OPCODES... program_opcodes: preop=5006 optype=463b opmenu=05d80302c79f0190 done preop0=0x06, preop1=0x50 op[0]=0x02, 3, 0 op[1]=0x03, 2, 0 op[2]=0xd8, 3, 0 op[3]=0x05, 0, 0 op[4]=0x90, 2, 0 op[5]=0x01, 1, 0 op[6]=0x9f, 0, 0 op[7]=0xc7, 1, 0 SPI Read Configuration: prefetching disabled, caching enabled, OK. This chipset supports the following protocols: FWH, SPI. Probing for AMIC A25L05PT, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L05PU, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L10PT, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L10PU, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L20PT, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L20PU, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L40PT, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L40PU, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L80P, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L16PT, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L16PU, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L512, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L010, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L020, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L040, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L080, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L016, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L032, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25LQ032, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DF021, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DF041A, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DF081, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DF161, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DF321, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DF321A, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DF641, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DQ161, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25F512B, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25FS010, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25FS040, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT26DF041, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT26DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT26DF161, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT26DF161A, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT26F004, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45CS1282, 16896 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB011D, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB021D, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB041D, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB081D, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB161D, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB321C, 4224 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB321D, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB642D, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for EMST F25L008A, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B05, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B05T, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B10T, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B20T, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B40T, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B80T, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B16T, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B32T, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B64T, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25F05, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25F10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25F20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25F40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25F80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25F16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25F32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25Q40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25Q80(A), 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25Q32(A/B), 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25QH16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0x01, id2 0x25, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0xcd, id2 0xe1, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX25L512, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L1005, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L2005, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L4005, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L8005, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L1605, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L1635D, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L1635E, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L3205, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L3235D, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L6405, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L12805, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Numonyx M25PE10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Numonyx M25PE20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Numonyx M25PE40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Numonyx M25PE80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Numonyx M25PE16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for PMC Pm25LV010, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for PMC Pm25LV016B, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for PMC Pm25LV020, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for PMC Pm25LV040, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for PMC Pm25LV080B, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for PMC Pm25LV512, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0x84, id2 0xd2, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0x01, id2 0x25, id1 is normal flash content, id2 is normal flash content Probing for Sanyo LF25FW203A, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0xcd, id2 0xe1, id1 is normal flash content, id2 is normal flash content Probing for Spansion S25FL004A, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Spansion S25FL008A, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Spansion S25FL016A, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Spansion S25FL032A, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Spansion S25FL064A, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for SST SST25VF010.REMS, 128 kB: probe_spi_rems: id1 0xef, id2 0x15 Probing for SST SST25VF016B, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for SST SST25VF032B, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for SST SST25VF064C, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for SST SST25VF040.REMS, 512 kB: probe_spi_rems: id1 0xef, id2 0x15 Probing for SST SST25VF040B, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for SST SST25LF040A.RES, 512 kB: program_opcodes: preop=5006 optype=462b opmenu=05ab0302c79f0190 on-the-fly OPCODE (0xAB) re-programmed, op-pos=2 probe_spi_res2: id1 0x15, id2 0x15 Probing for SST SST25VF040B.REMS, 512 kB: probe_spi_rems: id1 0xef, id2 0x15 Probing for SST SST25VF080B, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0x84, id2 0xd2, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0x01, id2 0x25, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0x01, id2 0x25, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0xcd, id2 0xe1, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0xcd, id2 0xe1, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 kB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0x00, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M25P05-A, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P05.RES, 64 kB: Ignoring RES in favour of RDID. Probing for ST M25P10-A, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P10.RES, 128 kB: Ignoring RES in favour of RDID. Probing for ST M25P20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P40-old, 512 kB: Ignoring RES in favour of RDID. Probing for ST M25P80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P128, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25PX16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25PX32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25PX64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0x01, id2 0x25, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0x01, id2 0x25, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0xcd, id2 0xe1, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0xcd, id2 0xe1, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0x84, id2 0xd2, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 kB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0x00, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0x01, id2 0x25, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0xcd, id2 0xe1, id1 is normal flash content, id2 is normal flash content Probing for Winbond W25Q80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25Q32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Chip status register is 00 Found Winbond flash chip "W25Q32" (4096 kB, SPI) at physical address 0xffc00000. Probing for Winbond W25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25X10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25X20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25X40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25X80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25X16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25X32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25X64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0x01, id2 0x25, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0x01, id2 0x25, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0x01, id2 0x25, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0x84, id2 0xd2, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0xcd, id2 0xe1, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 0x01, id2 0x25, id1 is normal flash content, id2 is normal flash content Probing for AMIC unknown AMIC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel unknown Atmel SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon unknown Eon SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix unknown Macronix SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for PMC unknown PMC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for SST unknown SST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST unknown ST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Sanyo unknown Sanyo SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Generic unknown SPI chip (RDID), 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Generic unknown SPI chip (REMS), 0 kB: probe_spi_rems: id1 0xef, id2 0x15 No operations were specified. Restoring MMIO space at 0xb76fb8a0 Restoring MMIO space at 0xb76fb89c Restoring MMIO space at 0xb76fb898 Restoring MMIO space at 0xb76fb896 Restoring MMIO space at 0xb76fb894 Restoring PCI config space for 00:1f:0 reg 0xdc From stefan.tauner at student.tuwien.ac.at Tue Nov 29 10:56:12 2011 From: stefan.tauner at student.tuwien.ac.at (Stefan Tauner) Date: Tue, 29 Nov 2011 10:56:12 +0100 Subject: [flashrom] [PATCH] ft2232_spi: fix arm-usb-ocd and arm-usb-ocd-h In-Reply-To: <201111181828.pAIISQ1O005771@home.pavel.comp> References: <201111181828.pAIISQ1O005771@home.pavel.comp> Message-ID: <201111290955.pAT9th3g005487@mail2.student.tuwien.ac.at> On Fri, 18 Nov 2011 22:15:43 +0400 Paul Fertser wrote: > These devices have an additional output buffer which is activated only > by pulling ADBUS4 low. This patch was real-life tested with > arm-usb-ocd; arm-usb-ocd-h should be the same (as it shares the same > documentation). > > Signed-off-by: Paul Fertser Thanks for your patch Paul! As you have found out we are not that fast at integrating patches... sorry for that. I don't know much about the ft2232 programmers, but your patch looks ok in general and is signed off, so there is not much you can do further (but nag us). I have CCed the submitter of the original olimex patch (hello Pete) in case he wants to take a look and ack it. -- Kind regards/Mit freundlichen Gr??en, Stefan Tauner From vm_ at viem77.org Tue Nov 29 21:30:04 2011 From: vm_ at viem77.org (Eugene vm_) Date: Wed, 30 Nov 2011 00:30:04 +0400 Subject: [flashrom] Untested chipset' verbose log Message-ID: <4ED540CC.50303@viem77.org> Hello! Sending you verbose flashrom log for VIA VT82C686A/B, marked as untested. Feel free to request any additional hardware or software config information. Regards. -- Eugene 'vm_' Vdovenko -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: via_vt82c686a_b.log URL: From novoagansk at gmail.com Wed Nov 30 20:45:03 2011 From: novoagansk at gmail.com (Pavel Petrov) Date: Thu, 1 Dec 2011 01:45:03 +0600 Subject: [flashrom] P8H61 PRO Message-ID: flashrom --read /bios.rom -V flashrom v0.9.4-r1394 on Linux 3.0.0-14-generic-pae (i686), built with libpci 3.1.7, GCC 4.6.1, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 3351M loops per second, 10 myus = 10 us, 100 myus = 98 us, 1000 myus = 986 us, 10000 myus = 9984 us, 4 myus = 3 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "System manufacturer" DMI string system-product-name: "System Product Name" DMI string system-version: "System Version" DMI string baseboard-manufacturer: "ASUSTeK Computer INC." DMI string baseboard-product-name: "P8H61 PRO" DMI string baseboard-version: "Rev X.0x" DMI string chassis-type: "Desktop" Found chipset "Intel H61" with PCI ID 8086:1c5c. This chipset is marked as untested. If you are using an up-to-date version of flashrom please email a report to flashrom at flashrom.org including a verbose (-V) log. Thank you! Enabling flash write... 0xfff80000/0xffb80000 FWH IDSEL: 0x0 0xfff00000/0xffb00000 FWH IDSEL: 0x0 0xffe80000/0xffa80000 FWH IDSEL: 0x1 0xffe00000/0xffa00000 FWH IDSEL: 0x1 0xffd80000/0xff980000 FWH IDSEL: 0x2 0xffd00000/0xff900000 FWH IDSEL: 0x2 0xffc80000/0xff880000 FWH IDSEL: 0x3 0xffc00000/0xff800000 FWH IDSEL: 0x3 0xff700000/0xff300000 FWH IDSEL: 0x4 0xff600000/0xff200000 FWH IDSEL: 0x5 0xff500000/0xff100000 FWH IDSEL: 0x6 0xff400000/0xff000000 FWH IDSEL: 0x7 0xfff80000/0xffb80000 FWH decode enabled 0xfff00000/0xffb00000 FWH decode enabled 0xffe80000/0xffa80000 FWH decode enabled 0xffe00000/0xffa00000 FWH decode enabled 0xffd80000/0xff980000 FWH decode enabled 0xffd00000/0xff900000 FWH decode enabled 0xffc80000/0xff880000 FWH decode enabled 0xffc00000/0xff800000 FWH decode enabled 0xff700000/0xff300000 FWH decode disabled 0xff600000/0xff200000 FWH decode disabled 0xff500000/0xff100000 FWH decode disabled 0xff400000/0xff000000 FWH decode disabled Maximum FWH chip size: 0x100000 bytes BIOS Lock Enable: disabled, BIOS Write Enable: disabled, BIOS_CNTL is 0x0 Root Complex Register Block address = 0xfed1c000 GCS = 0xc04: BIOS Interface Lock-Down: disabled, BOOT BIOS Straps: 0x3 (LPC) Top Swap : not enabled SPIBAR = 0xfed1c000 + 0x3800 0x04: 0x6008 (HSFS) HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=1, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=0 0x06: 0x0000 (HSFC) HSFC: FGO=0, FCYCLE=0, FDBC=0, SME=0 0x08: 0x00001000 (FADDR) 0x50: 0x00000a0b (FRAP) BMWAG 0x00, BMRAG 0x00, BRWA 0x0a, BRRA 0x0b 0x54: 0x00000000 (FREG0: Flash Descriptor) 0x00000000-0x00000fff is read-only 0x58: 0x03ff0180 (FREG1: BIOS) 0x00180000-0x003fffff is read-write 0x5C: 0x017f0001 (FREG2: Management Engine) 0x00001000-0x0017ffff is locked 0x60: 0x00000fff (FREG3: Gigabit Ethernet) Gigabit Ethernet region is unused. 0x64: 0x00000fff (FREG4: Platform Data) Platform Data region is unused. 0x74: 0x00000000 (PR0) 0x78: 0x00000000 (PR1) 0x7C: 0x00000000 (PR2) 0x80: 0x00000000 (PR3) 0x84: 0x00000000 (PR4) 0x90: 0x84 (SSFS) SSFS: SCIP=0, FDONE=1, FCERR=0, AEL=0 0x91: 0xf80000 (SSFC) SSFC: SCGO=0, ACS=0, SPOP=0, COP=0, DBC=0, SME=0, SCF=0 0x94: 0x0006 (PREOP) 0x96: 0x043b (OPTYPE) 0x98: 0x05200302 (OPMENU) 0x9C: 0x0000019f (OPMENU+4) 0xA0: 0x00000000 (BBAR) 0xD0: 0x00000000 (FPB) Programming OPCODES... program_opcodes: preop=5006 optype=463b opmenu=05d80302c79f0190 done preop0=0x06, preop1=0x50 op[0]=0x02, 3, 0 op[1]=0x03, 2, 0 op[2]=0xd8, 3, 0 op[3]=0x05, 0, 0 op[4]=0x90, 2, 0 op[5]=0x01, 1, 0 op[6]=0x9f, 0, 0 op[7]=0xc7, 1, 0 SPI Read Configuration: prefetching disabled, caching enabled, OK. This chipset supports the following protocols: FWH, SPI. Probing for AMIC A25L05PT, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L05PU, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L10PT, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L10PU, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L20PT, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L20PU, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L40PT, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L40PU, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L80P, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L16PT, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L16PU, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L512, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L010, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L020, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L040, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L080, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L016, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L032, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25LQ032, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DF021, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DF041A, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DF081, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DF161, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DF321, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DF321A, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DF641, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DQ161, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25F512B, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25FS010, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25FS040, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT26DF041, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT26DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT26DF161, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT26DF161A, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT26F004, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45CS1282, 16896 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB011D, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB021D, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB041D, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB081D, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB161D, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB321C, 4224 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB321D, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB642D, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for EMST F25L008A, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B05, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B05T, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B10T, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B20T, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B40T, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B80T, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B16T, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B32T, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B64T, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25F05, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25F10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25F20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25F40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25F80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25F16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25F32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25Q40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25Q80(A), 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25Q32(A/B), 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25QH16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0xf7, id2 0xf0, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX25L512, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L1005, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L2005, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L4005, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L8005, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L1605, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L1635D, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L1635E, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L3205, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L3235D, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L6405, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L12805, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Numonyx M25PE10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Numonyx M25PE20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Numonyx M25PE40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Numonyx M25PE80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Numonyx M25PE16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for PMC Pm25LV010, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for PMC Pm25LV016B, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for PMC Pm25LV020, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for PMC Pm25LV040, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for PMC Pm25LV080B, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for PMC Pm25LV512, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for Sanyo LF25FW203A, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0xf7, id2 0xf0, id1 is normal flash content, id2 is normal flash content Probing for Spansion S25FL004A, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Spansion S25FL008A, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Spansion S25FL016A, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Spansion S25FL032A, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Spansion S25FL064A, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for SST SST25VF010.REMS, 128 kB: probe_spi_rems: id1 0xef, id2 0x15 Probing for SST SST25VF016B, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for SST SST25VF032B, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for SST SST25VF064C, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for SST SST25VF040.REMS, 512 kB: probe_spi_rems: id1 0xef, id2 0x15 Probing for SST SST25VF040B, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for SST SST25LF040A.RES, 512 kB: program_opcodes: preop=5006 optype=462b opmenu=05ab0302c79f0190 on-the-fly OPCODE (0xAB) re-programmed, op-pos=2 probe_spi_res2: id1 0x15, id2 0x15 Probing for SST SST25VF040B.REMS, 512 kB: probe_spi_rems: id1 0xef, id2 0x15 Probing for SST SST25VF080B, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0x3b, id2 0x18, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0xf7, id2 0xf0, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0xf7, id2 0xf0, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 kB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0x4d, id2 0x65, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M25P05-A, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P05.RES, 64 kB: Ignoring RES in favour of RDID. Probing for ST M25P10-A, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P10.RES, 128 kB: Ignoring RES in favour of RDID. Probing for ST M25P20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P40-old, 512 kB: Ignoring RES in favour of RDID. Probing for ST M25P80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P128, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25PX16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25PX32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25PX64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0xf7, id2 0xf0, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0xf7, id2 0xf0, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 kB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0x4d, id2 0x65, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0xf7, id2 0xf0, id1 is normal flash content, id2 is normal flash content Probing for Winbond W25Q80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25Q32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Chip status register is 00 Found Winbond flash chip "W25Q32" (4096 kB, SPI) at physical address 0xffc00000. Probing for Winbond W25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25X10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25X20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25X40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25X80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25X16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25X32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25X64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0xf7, id2 0xf0, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for AMIC unknown AMIC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel unknown Atmel SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon unknown Eon SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix unknown Macronix SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for PMC unknown PMC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for SST unknown SST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST unknown ST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Sanyo unknown Sanyo SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Generic unknown SPI chip (RDID), 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Generic unknown SPI chip (REMS), 0 kB: probe_spi_rems: id1 0xef, id2 0x15 Reading flash... Transaction error! SSFS: SCIP=0, FDONE=1, FCERR=1, AEL=0 SSFC: SCGO=0, ACS=0, SPOP=0, COP=1, DBC=63, SME=0, SCF=0 Running OPCODE 0x03 failed at address 0x001000 (payload length was 64). Read operation failed! FAILED. Restoring MMIO space at 0xb77d48a0 Restoring MMIO space at 0xb77d489c Restoring MMIO space at 0xb77d4898 Restoring MMIO space at 0xb77d4896 Restoring MMIO space at 0xb77d4894 Restoring PCI config space for 00:1f:0 reg 0xdc -------------- next part -------------- An HTML attachment was scrubbed... URL: From stefan.tauner at student.tuwien.ac.at Wed Nov 30 23:30:32 2011 From: stefan.tauner at student.tuwien.ac.at (Stefan Tauner) Date: Wed, 30 Nov 2011 23:30:32 +0100 Subject: [flashrom] P8H61 PRO In-Reply-To: References: Message-ID: <201111302230.pAUMTwrS020929@mail2.student.tuwien.ac.at> On Thu, 1 Dec 2011 01:45:03 +0600 Pavel Petrov wrote: > 0x5C: 0x017f0001 (FREG2: Management Engine) > 0x00001000-0x0017ffff is locked Hello Pavel, thanks for your report! The problem is the locked ME region as quoted above. We are working on unlocking it, but intel does not provide us any documentation so please do not expect a solution soon. I have added the board to our list of (un)supported boards (with an appropriate note) and will commit that later together with other small changes. -- Kind regards/Mit freundlichen Gr??en, Stefan Tauner From stefan.tauner at student.tuwien.ac.at Wed Nov 30 23:37:13 2011 From: stefan.tauner at student.tuwien.ac.at (Stefan Tauner) Date: Wed, 30 Nov 2011 23:37:13 +0100 Subject: [flashrom] "Intel H61" with PCI ID 8086:1c5c. including a verbose (-V) log In-Reply-To: <20111128212208.5c7fca81@bol.com.br> References: <20111128212208.5c7fca81@bol.com.br> Message-ID: <201111302236.pAUMac3k028133@mail2.student.tuwien.ac.at> Hello Fabio! From what i can tell from your log, the board will most probably be fully supported by flashrom. Have you tried reading and or writing? Which mainboard is it? -- Kind regards/Mit freundlichen Gr??en, Stefan Tauner