[flashrom] Asrock E350M1 - flashrom erase failed

[Stefan Tauner]

On Wed, 03 Jul 2013 19:31:16 +0200
Reiner Luett <diffusae at yahoo.se> wrote:

> On 03.07.2013 11:43, Stefan Tauner wrote:
> > On Wed, 03 Jul 2013 00:29:03 +0200
> > Reiner Luett <diffusae at yahoo.se> wrote:
> > 
> >> I can use it with spispeed 33.
> > 
> > JFYI, you did use 16.5MHz actually because my patch was incomplete and
> > always sets 16.5MHz although saying otherwise.
> 
> I couldn't see this while flashing the chip. I only have this
> information in the log file:
> 
> Setting SPI clock to 33 MHz (0x1) and disabling fast reads... done
> (0x0cc08303) fastReadEnable=0, SpiArbEnable=0, SpiAccessMacRomEn=1,
> SpiHostAccessRomEn=1, ArbWaitCount=4, SpiBridgeDisable=1, DropOneClkOnRd=0
> NormSpeed is 16.5 MHz
> 
> But it seem to write perfectly now.

The output printed after NormSpeed was and is correct, as was all the
outer text output, but under the hood it did always set 16.5MHz instead
of what the user requested.

> 
> > I have prepared a corrected patch, but it is rebased on another
> > AMD-related patch (i.e. IMC shutdown) and hence is not applicable as is
> > so I do not post it here. If anyone wants to give it a shot, please say
> > so.
> 
> Yes for sure, I like to try. But where could I see the correct write speed?

You would need to checkout my github repository. The two patches you
need are inside the flashrom_next branch:
https://github.com/stefanct/flashrom/tree/flashrom_next

> BTW: Do you have the IMC firmware for the Asrock E350M1 or maybe know,
> who I need to contact at AMD to obtain it?

No idea. If it is not included with the default build of coreboot it is
probably not mandatory. I remember that there was some work done
regarding writing an open source firmware for it. You better ask
coreboot at coreboot.org or on IRC.

-- 
Kind regards/Mit freundlichen Grüßen, Stefan Tauner