[flashrom] Larger SPI NOR flash parts

David Hendricks david.hendricks at gmail.com
Tue Apr 18 06:54:40 CEST 2017


Hi Alex,
Getting 4-byte address support in is something I'm interested in as well.
In fact I have parts coming in the mail this week :-)

On Mon, Apr 17, 2017 at 6:43 PM, Alex Henderson <
ahenderson at aparnasystems.com> wrote:

> Hi there:
>
>                I just started experimenting with flashrom using a Dediprog
> SF600 this weekend. I noticed that there’s no support for any of the 256Mb
> or 512Mb SPI NOR parts (4 byte addressing an issue?).
>

The Dediprog SF600 has commands for 4-byte addressing, but I was not able
to get them working in the time I had to play with it. We can probably also
ask Dediprog if they have an updated command spec, maybe there was a
problem in the one I was looking at.


> Is there a newer version than 0.9.9 that I should try? I did find that the
> Google fork for chromeOS has a number of these parts (W25Q256, N25Q256,
> SST_25F256).
>

Yes, but the systems those went in treated them as 16MB parts. The firmware
(coreboot) is small so there wasn't really need for the extra space.

               I would be happy to try an unreleased version & report
> results. I can also test with an FTDI232 based programmer. The boards I can
> test with currently have various versions of 25q512, 25q256, 25q128 and
> 25q32. Functionality with the smaller parts looks good.
>

Great! We've got some pending patches for you to try, then...

For the chromiumos branch, try this patch series:
https://chromium-review.googlesource.com/c/323359/ (Click "Download" and
then you can just checkout the full thing).
For upstream, try this: https://mail.coreboot.org/pipe
rmail/flashrom/2016-April/014579.html

The thing to keep in mind is that there are at least three ways in which
4-byte addressing is handled, and the method depends on the chip:
- The chip uses the same instructions for 3-byte and 4-byte operations, but
has a status/control register bit that extends the address to 4-bytes.
("Mode 1" in my patch)
- The chip has separate instructions for operations using 3-byte and 4-byte
addresses. ("Mode 2" in my patch)
- The chip only supports 4-byte instructions; 3-byte instructions are not
even implemented (The style that Tim's patch addressed)

For chromiumos:
1. Clone the flashrom repo: https://chromium.googles
ource.com/chromiumos/third_party/flashrom/
2. cd to the newly created directory (e.g. cd flashrom/)
3. Checkout the patch series:
        a. Go to https://chromium-review.googlesource.com/c/323359
        b. Click "Download"
        c. Copy these the "Checkout" command and paste it into your
terminal.
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/flashrom/attachments/20170417/8e4673b1/attachment.html>


More information about the flashrom mailing list