Looks good to me. Is there any reason not to ACK this? It seems like a useful optimization, at least.<div><br></div><div>I think there may have been a small misunderstanding with the snippet Carl-Daniel posted earlier. The note about usage model at the end of the section might help alleviate fears of doing multiple writes without doing an erase operation first. Here is the full section from the ICH7 datasheet from April '07:</div>
<div><br></div><div><div><div><i>5.25.4.3 Multiple Page Write Usage Model</i></div><div><i> The system BIOS and Intel® Active Management Technology firmware usage models</i></div><div><i> require that the serial flash device support multiple writes (minimum of 512 writes) to</i></div>
<div><i> a page (256 bytes) without requiring a preceding erase command. BIOS commonly</i></div><div><i> uses capabilities such as counters that are typically implemented by using byte writes</i></div><div>
<i> to ‘increment’ the bits within a page that have been designated as the counter. The</i></div><div><i> Intel AMT firmware usage model requires the capability for multiple data updates within</i></div><div>
<i> any given page. These data updates occur via byte writes without executing a</i></div><div><i> preceding erase to the given page. Both the BIOS and Intel AMT firmware multiple</i></div><div><i> page write usage models apply to sequential and non-sequential data writes.</i></div>
<div><i><b>Note: </b>This usage model requirement is based on any given bit only being written once from a</i></div><div><i> ‘1’ to a ‘0’ without requiring the preceding erase. An erase would be required to change</i></div>
<div><i> bits back to the ‘1’ state.</i></div><div><br></div><br><div class="gmail_quote">On Thu, Feb 11, 2010 at 6:31 AM, Carl-Daniel Hailfinger <span dir="ltr"><<a href="mailto:c-d.hailfinger.devel.2006@gmx.net">c-d.hailfinger.devel.2006@gmx.net</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex;">This patch is 5 months old and it would be awesome if someone could<br>
review it.<br>
We need this if we ever want to support partial writes.<br>
<div class="im"><br>
On 22.12.2009 02:38, Carl-Daniel Hailfinger wrote:<br>
> On 23.11.2009 15:33, Carl-Daniel Hailfinger wrote:<br>
><br>
>> On 19.11.2009 17:51, Carl-Daniel Hailfinger wrote:<br>
>><br>
>><br>
>>> To summarize: Write granularity is chip specific. The following write<br>
>>> granularities exist according to my datasheet survey:<br>
>>> - 1 bit. Each bit can be cleared individually.<br>
>>> - 1 byte. A byte can be written once. Further writes to an already<br>
>>> written byte cause the contents to be either undefined or to stay unchanged.<br>
>>> - 128 bytes. If less than 128 bytes are written, the rest will be<br>
>>> erased. Each write to a 128-byte region will trigger an automatic erase<br>
>>> before anything is written. Very uncommon behaviour.<br>
>>> - 256 bytes. If less than 256 bytes are written, the contents of the<br>
>>> unwritten bytes are undefined.<br>
>>><br>
>>><br>
>> New patch. Handle 1-bit, 1-byte and 256-byte write granularity.<br>
>><br>
</div><div class="im">>> Signed-off-by: Carl-Daniel Hailfinger <<a href="mailto:c-d.hailfinger.devel.2006@gmx.net">c-d.hailfinger.devel.2006@gmx.net</a>><br>
>><br>
>><br>
><br>
> Ping?<br>
> This is <a href="http://patchwork.coreboot.org/patch/582/" target="_blank">http://patchwork.coreboot.org/patch/582/</a> in case you want to<br>
> look at the patch again.<br>
><br>
<br>
Regards,<br>
Carl-Daniel<br>
<br>
--<br>
</div>Developer quote of the year:<br>
<div><div></div><div class="h5">"We are juggling too many chainsaws and flaming arrows and tigers."<br>
<br>
<br>
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