I tested the changes on my system. The system is a CurtisWright Raptor board with a single PowerPC 7457 processor. It has a daughter-board from TechnoBox 5575 PCI-over-PMC SATA adapter. The daughter-board has onboard BIOS (AMD flash chip) and EEPROM.<br>
<br>I was able to read, write and erase both chips using satasii programmer.<br><br>I did encounter an issue when my rootfs is mounted over NFS. When writing data back onto flash, the data came back in reverse endianness from the original. This was only an issue with NFS-mounted rootfs. When I tested the same procedure with the rootfs mounted from the internal SATA drive, everything was consistent.<br>
<br>My test procedure was as follows:<br><br>1. Run flashrom to detect the flah chips<br> flashrom -p satasii<br>2. Got the contents of the flash chips and diff-ed the hexdump of the contents against a known good image which came back with no differences<br>
flashrom -p satasii -r current_contents.img<br>3. Erased the contents of flash. Dumped the contents of the flash after erase and verified that it is all zeros (0)<br> flashrom -p satasii -E<br>4. Flashed the contents of the known good image<br>
flashrom -p satasii -w original.img<br>5. Dumped the new contents and verified the hexdump against the known good image again<br><br>Log of the steps and their result:<br><br>vsm:~# ./flashrom -p satasii<br>flashrom v0.9.1-r985<br>
Found "Silicon Image SiI 3512 [SATALink/SATARaid] SATA Ctrl" (1095:3512, BDF 00:0a.0).<br>===<br>This PCI device is UNTESTED. Please report the 'flashrom -p xxxx' output <br>to <a href="mailto:flashrom@flashrom.org">flashrom@flashrom.org</a> if it works for you. Thank you for your help!<br>
===<br>Mapping SATA SIL registers at 0xf0000000, unaligned size 0x100.<br>Warning: Flash seems unconnected.<br>Calibrating delay loop... OK.<br>Found chip "AMD Am29LV040B" (512 KB, Parallel) at physical address 0xfff80000.<br>
===<br>This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE<br>Please email a report to <a href="mailto:flashrom@flashrom.org">flashrom@flashrom.org</a> if any of the above operations<br>work correctly for you with this flash part. Please include the flashrom<br>
output with the additional -V option for all operations you tested (-V, -rV,<br>-wV, -EV), and mention which mainboard or programmer you tested.<br>Thanks for your help!<br>===<br>No operations were specified.<br>vsm:~# ./flashrom -p satasii -r current_contents.img<br>
flashrom v0.9.1-r985<br>Found "Silicon Image SiI 3512 [SATALink/SATARaid] SATA Ctrl" (1095:3512, BDF 00:0a.0).<br>===<br>This PCI device is UNTESTED. Please report the 'flashrom -p xxxx' output <br>to <a href="mailto:flashrom@flashrom.org">flashrom@flashrom.org</a> if it works for you. Thank you for your help!<br>
===<br>Mapping SATA SIL registers at 0xf0000000, unaligned size 0x100.<br>Warning: Flash seems unconnected.<br>Calibrating delay loop... OK.<br>Found chip "AMD Am29LV040B" (512 KB, Parallel) at physical address 0xfff80000.<br>
===<br>This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE<br>Please email a report to <a href="mailto:flashrom@flashrom.org">flashrom@flashrom.org</a> if any of the above operations<br>work correctly for you with this flash part. Please include the flashrom<br>
output with the additional -V option for all operations you tested (-V, -rV,<br>-wV, -EV), and mention which mainboard or programmer you tested.<br>Thanks for your help!<br>===<br>Reading flash... done.<br>vsm:~# hexdump current_contents.img > current_contents.hex <br>
vsm:~# diff sii.hex current_contents.hex <br>vsm:~# ./flashrom -p satasii -E<br>flashrom v0.9.1-r985<br>Found "Silicon Image SiI 3512 [SATALink/SATARaid] SATA Ctrl" (1095:3512, BDF 00:0a.0).<br>===<br>This PCI device is UNTESTED. Please report the 'flashrom -p xxxx' output <br>
to <a href="mailto:flashrom@flashrom.org">flashrom@flashrom.org</a> if it works for you. Thank you for your help!<br>===<br>Mapping SATA SIL registers at 0xf0000000, unaligned size 0x100.<br>Warning: Flash seems unconnected.<br>
Calibrating delay loop... OK.<br>Found chip "AMD Am29LV040B" (512 KB, Parallel) at physical address 0xfff80000.<br>===<br>This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE<br>Please email a report to <a href="mailto:flashrom@flashrom.org">flashrom@flashrom.org</a> if any of the above operations<br>
work correctly for you with this flash part. Please include the flashrom<br>output with the additional -V option for all operations you tested (-V, -rV,<br>-wV, -EV), and mention which mainboard or programmer you tested.<br>
Thanks for your help!<br>===<br>Erasing flash chip... SUCCESS.<br>vsm:~# ./flashrom -p satasii -r empty.img<br>flashrom v0.9.1-r985<br>Found "Silicon Image SiI 3512 [SATALink/SATARaid] SATA Ctrl" (1095:3512, BDF 00:0a.0).<br>
===<br>This PCI device is UNTESTED. Please report the 'flashrom -p xxxx' output <br>to <a href="mailto:flashrom@flashrom.org">flashrom@flashrom.org</a> if it works for you. Thank you for your help!<br>===<br>Mapping SATA SIL registers at 0xf0000000, unaligned size 0x100.<br>
Warning: Flash seems unconnected.<br>Calibrating delay loop... OK.<br>Found chip "AMD Am29LV040B" (512 KB, Parallel) at physical address 0xfff80000.<br>===<br>This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE<br>
Please email a report to <a href="mailto:flashrom@flashrom.org">flashrom@flashrom.org</a> if any of the above operations<br>work correctly for you with this flash part. Please include the flashrom<br>output with the additional -V option for all operations you tested (-V, -rV,<br>
-wV, -EV), and mention which mainboard or programmer you tested.<br>Thanks for your help!<br>===<br>Reading flash... done.<br>vsm:~# hexdump empty.img <br>0000000 ffff ffff ffff ffff ffff ffff ffff ffff<br>*<br>0080000<br>
vsm:~# ./flashrom -p satasii -w sii. <br>sii.dump sii.hex <br>vsm:~# ./flashrom -p satasii -w sii.dump <br>flashrom v0.9.1-r985<br>Found "Silicon Image SiI 3512 [SATALink/SATARaid] SATA Ctrl" (1095:3512, BDF 00:0a.0).<br>
===<br>This PCI device is UNTESTED. Please report the 'flashrom -p xxxx' output <br>to <a href="mailto:flashrom@flashrom.org">flashrom@flashrom.org</a> if it works for you. Thank you for your help!<br>===<br>Mapping SATA SIL registers at 0xf0000000, unaligned size 0x100.<br>
Warning: Flash seems unconnected.<br>Calibrating delay loop... OK.<br>Found chip "AMD Am29LV040B" (512 KB, Parallel) at physical address 0xfff80000.<br>===<br>This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE<br>
Please email a report to <a href="mailto:flashrom@flashrom.org">flashrom@flashrom.org</a> if any of the above operations<br>work correctly for you with this flash part. Please include the flashrom<br>output with the additional -V option for all operations you tested (-V, -rV,<br>
-wV, -EV), and mention which mainboard or programmer you tested.<br>Thanks for your help!<br>===<br>Flash image seems to be a legacy BIOS. Disabling checks.<br>Writing flash chip... Erasing flash chip... SUCCESS.<br>Programming page: DONE!ss: 0x0007f000<br>
COMPLETE.<br>Verifying flash... VERIFIED. <br>vsm:~# ./flashrom -p satasii -r new.img <br>flashrom v0.9.1-r985<br>Found "Silicon Image SiI 3512 [SATALink/SATARaid] SATA Ctrl" (1095:3512, BDF 00:0a.0).<br>
===<br>This PCI device is UNTESTED. Please report the 'flashrom -p xxxx' output <br>to <a href="mailto:flashrom@flashrom.org">flashrom@flashrom.org</a> if it works for you. Thank you for your help!<br>===<br>Mapping SATA SIL registers at 0xf0000000, unaligned size 0x100.<br>
Warning: Flash seems unconnected.<br>Calibrating delay loop... OK.<br>Found chip "AMD Am29LV040B" (512 KB, Parallel) at physical address 0xfff80000.<br>===<br>This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE<br>
Please email a report to <a href="mailto:flashrom@flashrom.org">flashrom@flashrom.org</a> if any of the above operations<br>work correctly for you with this flash part. Please include the flashrom<br>output with the additional -V option for all operations you tested (-V, -rV,<br>
-wV, -EV), and mention which mainboard or programmer you tested.<br>Thanks for your help!<br>===<br>Reading flash... done.<br>vsm:~# hexdump new.img > new.hex <br>vsm:~# diff new.hex sii.hex <br><br>All these steps were completed successfully<br>
<br>Thank you everyone for your help<br><br>Acked-by: Misha Manulis <<a href="mailto:misha@manulis.com">misha@manulis.com</a>><br><br><div class="gmail_quote">On Fri, Mar 26, 2010 at 9:42 AM, Carl-Daniel Hailfinger <span dir="ltr"><<a href="mailto:c-d.hailfinger.devel.2006@gmx.net">c-d.hailfinger.devel.2006@gmx.net</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="border-left: 1px solid rgb(204, 204, 204); margin: 0pt 0pt 0pt 0.8ex; padding-left: 1ex;"><div><div></div><div class="h5">On 26.03.2010 05:13, Carl-Daniel Hailfinger wrote:<br>
> Misha Manulis asked for satasii support on PPC and on IRC we gave him<br>
> some hints to hack up something that works for ppc only and satasii<br>
> only. His patch can be found here: <a href="http://coreboot.pastebin.com/fuLk1FCA" target="_blank">http://coreboot.pastebin.com/fuLk1FCA</a><br>
><br>
> Here is a patch which does everything The Right Way (TM) and uses proper<br>
> abstraction for satasii and compiles all x86 specific stuff only on x86.<br>
><br>
> Huge thanks go to Segher Boessenkool who provided valuable info about<br>
> all the endianness trickery (especially preprocessor macros) and tested<br>
> 8 iterations of the code on Linux/PPC.<br>
><br>
> On 26.03.2010 01:51, Carl-Daniel Hailfinger wrote:<br>
><br>
>> flashrom is very x86 centric. It does work on other architectures if you<br>
>> get it to compile. Try to fix the all errors on ppc for a<br>
>> full build.<br>
>><br>
>> Should work in theory with a default build if you exclude nic3com.<br>
>> Will pretty sure break compilation on Alpha.<br>
>><br>
>><br>
><br>
> This one should compile on ppc, I even expect it to work for satasii on ppc.<br>
> AFAICS all programmer drivers except nic3com should work.<br>
> Compile with<br>
> make distclean<br>
> make NIC3COM=no<br>
><br>
><br>
> Known bugs:<br>
><br>
> x86 is broken by this patch because the Makefile excludes the x86<br>
> specific internal files. If you want to test this patch on x86 (to make<br>
> sure I didn't break everything), change<br>
> #PROGRAMMER_OBJS += it87spi.o ichspi.o sb600spi.o wbsio_spi.o<br>
> to<br>
> PROGRAMMER_OBJS += it87spi.o ichspi.o sb600spi.o wbsio_spi.o<br>
><br>
> boards_ok and boards_bad has no x86 guard yet and will end up in<br>
> flashrom -L output.<br>
><br>
<br>
</div></div>Misha Manulis tested the patch and it didn't work. I found a typo which<br>
truncated all 16 bit and 32 bit LE write accesses to 8 bit.<br>
<br>
New version, should work fine with the x86/nic3com exceptions mentioned<br>
above.<br>
<div><div></div><div class="h5"><br>
Signed-off-by: Carl-Daniel Hailfinger <<a href="mailto:c-d.hailfinger.devel.2006@gmx.net">c-d.hailfinger.devel.2006@gmx.net</a>><br>
<br>
Index: flashrom-ioport_x86_only/hwaccess.c<br>
===================================================================<br>
--- flashrom-ioport_x86_only/hwaccess.c (Revision 984)<br>
+++ flashrom-ioport_x86_only/hwaccess.c (Arbeitskopie)<br>
@@ -26,6 +26,8 @@<br>
#include <errno.h><br>
#include "flash.h"<br>
<br>
+#if defined(__i386__) || defined(__x86_64__)<br>
+<br>
#if defined(__FreeBSD__) || defined(__DragonFly__)<br>
int io_fd;<br>
#endif<br>
@@ -54,6 +56,22 @@<br>
#endif<br>
}<br>
<br>
+#elif defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__)<br>
+<br>
+void get_io_perms(void)<br>
+{<br>
+}<br>
+<br>
+void release_io_perms(void)<br>
+{<br>
+}<br>
+<br>
+#else<br>
+<br>
+#error Unknown architecture<br>
+<br>
+#endif<br>
+<br>
#ifdef __DJGPP__<br>
<br>
extern unsigned short segFS;<br>
@@ -122,3 +140,33 @@<br>
return *(volatile uint32_t *) addr;<br>
}<br>
#endif<br>
+<br>
+void mmio_le_writeb(uint8_t val, void *addr)<br>
+{<br>
+ mmio_writeb(cpu_to_le8(val), addr);<br>
+}<br>
+<br>
+void mmio_le_writew(uint16_t val, void *addr)<br>
+{<br>
</div></div>+ mmio_writew(cpu_to_le16(val), addr);<br>
<div class="im">+}<br>
+<br>
+void mmio_le_writel(uint32_t val, void *addr)<br>
+{<br>
</div>+ mmio_writel(cpu_to_le32(val), addr);<br>
<div><div></div><div class="h5">+}<br>
+<br>
+uint8_t mmio_le_readb(void *addr)<br>
+{<br>
+ return le_to_cpu8(mmio_readb(addr));<br>
+}<br>
+<br>
+uint16_t mmio_le_readw(void *addr)<br>
+{<br>
+ return le_to_cpu16(mmio_readw(addr));<br>
+}<br>
+<br>
+uint32_t mmio_le_readl(void *addr)<br>
+{<br>
+ return le_to_cpu32(mmio_readl(addr));<br>
+}<br>
Index: flashrom-ioport_x86_only/flash.h<br>
===================================================================<br>
--- flashrom-ioport_x86_only/flash.h (Revision 984)<br>
+++ flashrom-ioport_x86_only/flash.h (Arbeitskopie)<br>
@@ -59,8 +59,10 @@<br>
PROGRAMMER_ATAHPT,<br>
#endif<br>
#if INTERNAL_SUPPORT == 1<br>
+#if defined(__i386__) || defined(__x86_64__)<br>
PROGRAMMER_IT87SPI,<br>
#endif<br>
+#endif<br>
#if FT2232_SPI_SUPPORT == 1<br>
PROGRAMMER_FT2232SPI,<br>
#endif<br>
@@ -402,6 +404,12 @@<br>
uint8_t mmio_readb(void *addr);<br>
uint16_t mmio_readw(void *addr);<br>
uint32_t mmio_readl(void *addr);<br>
+void mmio_le_writeb(uint8_t val, void *addr);<br>
+void mmio_le_writew(uint16_t val, void *addr);<br>
+void mmio_le_writel(uint32_t val, void *addr);<br>
+uint8_t mmio_le_readb(void *addr);<br>
+uint16_t mmio_le_readw(void *addr);<br>
+uint32_t mmio_le_readl(void *addr);<br>
<br>
/* programmer.c */<br>
int noop_shutdown(void);<br>
@@ -585,6 +593,7 @@<br>
enum spi_controller {<br>
SPI_CONTROLLER_NONE,<br>
#if INTERNAL_SUPPORT == 1<br>
+#if defined(__i386__) || defined(__x86_64__)<br>
SPI_CONTROLLER_ICH7,<br>
SPI_CONTROLLER_ICH9,<br>
SPI_CONTROLLER_IT87XX,<br>
@@ -592,6 +601,7 @@<br>
SPI_CONTROLLER_VIA,<br>
SPI_CONTROLLER_WBSIO,<br>
#endif<br>
+#endif<br>
#if FT2232_SPI_SUPPORT == 1<br>
SPI_CONTROLLER_FT2232,<br>
#endif<br>
Index: flashrom-ioport_x86_only/spi25.c<br>
===================================================================<br>
--- flashrom-ioport_x86_only/spi25.c (Revision 984)<br>
+++ flashrom-ioport_x86_only/spi25.c (Arbeitskopie)<br>
@@ -172,12 +172,14 @@<br>
/* only some SPI chipsets support 4 bytes commands */<br>
switch (spi_controller) {<br>
#if INTERNAL_SUPPORT == 1<br>
+#if defined(__i386__) || defined(__x86_64__)<br>
case SPI_CONTROLLER_ICH7:<br>
case SPI_CONTROLLER_ICH9:<br>
case SPI_CONTROLLER_VIA:<br>
case SPI_CONTROLLER_SB600:<br>
case SPI_CONTROLLER_WBSIO:<br>
#endif<br>
+#endif<br>
#if FT2232_SPI_SUPPORT == 1<br>
case SPI_CONTROLLER_FT2232:<br>
#endif<br>
@@ -950,11 +952,13 @@<br>
<br>
switch (spi_controller) {<br>
#if INTERNAL_SUPPORT == 1<br>
+#if defined(__i386__) || defined(__x86_64__)<br>
case SPI_CONTROLLER_WBSIO:<br>
msg_cerr("%s: impossible with Winbond SPI masters,"<br>
" degrading to byte program\n", __func__);<br>
return spi_chip_write_1(flash, buf);<br>
#endif<br>
+#endif<br>
default:<br>
break;<br>
}<br>
Index: flashrom-ioport_x86_only/hwaccess.h<br>
===================================================================<br>
--- flashrom-ioport_x86_only/hwaccess.h (Revision 984)<br>
+++ flashrom-ioport_x86_only/hwaccess.h (Arbeitskopie)<br>
@@ -24,13 +24,88 @@<br>
#ifndef __HWACCESS_H__<br>
#define __HWACCESS_H__ 1<br>
<br>
+#if defined (__i386__) || defined (__x86_64__)<br>
#if defined(__GLIBC__)<br>
#include <sys/io.h><br>
#endif<br>
+#endif<br>
+<br>
#if NEED_PCI == 1<br>
#include <pci/pci.h><br>
#endif<br>
<br>
+#define ___constant_swab8(x) ((uint8_t)( \<br>
+ (((uint8_t)(x) & (uint8_t)0xffU))))<br>
+<br>
+#define ___constant_swab16(x) ((uint16_t)( \<br>
+ (((uint16_t)(x) & (uint16_t)0x00ffU) << 8) | \<br>
+ (((uint16_t)(x) & (uint16_t)0xff00U) >> 8)))<br>
+<br>
+#define ___constant_swab32(x) ((uint32_t)( \<br>
+ (((uint32_t)(x) & (uint32_t)0x000000ffUL) << 24) | \<br>
+ (((uint32_t)(x) & (uint32_t)0x0000ff00UL) << 8) | \<br>
+ (((uint32_t)(x) & (uint32_t)0x00ff0000UL) >> 8) | \<br>
+ (((uint32_t)(x) & (uint32_t)0xff000000UL) >> 24)))<br>
+<br>
+#define ___constant_swab64(x) ((uint64_t)( \<br>
+ (((uint64_t)(x) & (uint64_t)0x00000000000000ffULL) << 56) | \<br>
+ (((uint64_t)(x) & (uint64_t)0x000000000000ff00ULL) << 40) | \<br>
+ (((uint64_t)(x) & (uint64_t)0x0000000000ff0000ULL) << 24) | \<br>
+ (((uint64_t)(x) & (uint64_t)0x00000000ff000000ULL) << 8) | \<br>
+ (((uint64_t)(x) & (uint64_t)0x000000ff00000000ULL) >> 8) | \<br>
+ (((uint64_t)(x) & (uint64_t)0x0000ff0000000000ULL) >> 24) | \<br>
+ (((uint64_t)(x) & (uint64_t)0x00ff000000000000ULL) >> 40) | \<br>
+ (((uint64_t)(x) & (uint64_t)0xff00000000000000ULL) >> 56)))<br>
+<br>
+#if defined (_BIG_ENDIAN) || defined (__BIG_ENDIAN__)<br>
+<br>
+#define cpu_to_le(bits) \<br>
+static inline uint##bits##_t cpu_to_le##bits(uint##bits##_t val) \<br>
+{ \<br>
+ return ___constant_swab##bits(val); \<br>
+}<br>
+<br>
+cpu_to_le(8)<br>
+cpu_to_le(16)<br>
+cpu_to_le(32)<br>
+cpu_to_le(64)<br>
+<br>
+#define cpu_to_be8<br>
+#define cpu_to_be16<br>
+#define cpu_to_be32<br>
+#define cpu_to_be64<br>
+<br>
+#else<br>
+<br>
+#define cpu_to_be(bits) \<br>
+static inline uint##bits##_t cpu_to_be##bits(uint##bits##_t val) \<br>
+{ \<br>
+ return ___constant_swab##bits(val); \<br>
+}<br>
+<br>
+cpu_to_be(8)<br>
+cpu_to_be(16)<br>
+cpu_to_be(32)<br>
+cpu_to_be(64)<br>
+<br>
+#define cpu_to_le8<br>
+#define cpu_to_le16<br>
+#define cpu_to_le32<br>
+#define cpu_to_le64<br>
+<br>
+#endif<br>
+<br>
+#define be_to_cpu8 cpu_to_be8<br>
+#define be_to_cpu16 cpu_to_be16<br>
+#define be_to_cpu32 cpu_to_be32<br>
+#define be_to_cpu64 cpu_to_be64<br>
+#define le_to_cpu8 cpu_to_le8<br>
+#define le_to_cpu16 cpu_to_le16<br>
+#define le_to_cpu32 cpu_to_le32<br>
+#define le_to_cpu64 cpu_to_le64<br>
+<br>
+#if defined (__i386__) || defined (__x86_64__)<br>
+<br>
/* for iopl and outb under Solaris */<br>
#if defined (__sun) && (defined(__i386) || defined(__amd64))<br>
#include <strings.h><br>
@@ -162,4 +237,11 @@<br>
int freebsd_wrmsr(int addr, msr_t msr);<br>
#endif<br>
<br>
+#elif defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__)<br>
+/* Port I/O is not available on PowerPC. */<br>
+<br>
+#else<br>
+#error Unknown architecture<br>
+#endif<br>
+<br>
#endif /* !__HWACCESS_H__ */<br>
Index: flashrom-ioport_x86_only/physmap.c<br>
===================================================================<br>
--- flashrom-ioport_x86_only/physmap.c (Revision 984)<br>
+++ flashrom-ioport_x86_only/physmap.c (Arbeitskopie)<br>
@@ -238,6 +238,8 @@<br>
return physmap_common(descr, phys_addr, len, PHYSMAP_MAYFAIL, PHYSMAP_RO);<br>
}<br>
<br>
+#if defined(__i386__) || defined(__x86_64__)<br>
+<br>
#ifdef __linux__<br>
/*<br>
* Reading and writing to MSRs, however requires instructions rdmsr/wrmsr,<br>
@@ -455,4 +457,6 @@<br>
#endif<br>
#endif<br>
#endif<br>
-<br>
+#else<br>
+/* Does MSR exist on non-x86 architectures? */<br>
+#endif<br>
Index: flashrom-ioport_x86_only/spi.c<br>
===================================================================<br>
--- flashrom-ioport_x86_only/spi.c (Revision 984)<br>
+++ flashrom-ioport_x86_only/spi.c (Arbeitskopie)<br>
@@ -42,6 +42,7 @@<br>
},<br>
<br>
#if INTERNAL_SUPPORT == 1<br>
+#if defined(__i386__) || defined(__x86_64__)<br>
{ /* SPI_CONTROLLER_ICH7 */<br>
.command = ich_spi_send_command,<br>
.multicommand = ich_spi_send_multicommand,<br>
@@ -84,6 +85,7 @@<br>
.write_256 = wbsio_spi_write_1,<br>
},<br>
#endif<br>
+#endif<br>
<br>
#if FT2232_SPI_SUPPORT == 1<br>
{ /* SPI_CONTROLLER_FT2232 */<br>
Index: flashrom-ioport_x86_only/nic3com.c<br>
===================================================================<br>
--- flashrom-ioport_x86_only/nic3com.c (Revision 984)<br>
+++ flashrom-ioport_x86_only/nic3com.c (Arbeitskopie)<br>
@@ -23,6 +23,8 @@<br>
#include <sys/types.h><br>
#include "flash.h"<br>
<br>
+#if defined(__i386__) || defined(__x86_64__)<br>
+<br>
#define BIOS_ROM_ADDR 0x04<br>
#define BIOS_ROM_DATA 0x08<br>
#define INT_STATUS 0x0e<br>
@@ -112,3 +114,7 @@<br>
OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR);<br>
return INB(io_base_addr + BIOS_ROM_DATA);<br>
}<br>
+<br>
+#else<br>
+#error Unknown architecture<br>
+#endif<br>
Index: flashrom-ioport_x86_only/Makefile<br>
===================================================================<br>
--- flashrom-ioport_x86_only/Makefile (Revision 984)<br>
+++ flashrom-ioport_x86_only/Makefile (Arbeitskopie)<br>
@@ -121,7 +121,8 @@<br>
<br>
ifeq ($(CONFIG_INTERNAL), yes)<br>
FEATURE_CFLAGS += -D'INTERNAL_SUPPORT=1'<br>
-PROGRAMMER_OBJS += chipset_enable.o board_enable.o cbtable.o dmi.o it87spi.o ichspi.o sb600spi.o wbsio_spi.o internal.o<br>
+PROGRAMMER_OBJS += chipset_enable.o board_enable.o cbtable.o dmi.o internal.o<br>
+#PROGRAMMER_OBJS += it87spi.o ichspi.o sb600spi.o wbsio_spi.o<br>
NEED_PCI := yes<br>
endif<br>
<br>
@@ -253,7 +254,7 @@<br>
rm -f .dependencies .features .libdeps<br>
<br>
dep:<br>
- @$(CC) $(CPPFLAGS) $(SVNDEF) -MM *.c > .dependencies<br>
+ @$(CC) $(CPPFLAGS) $(SVNDEF) -MM $(OBJS:.o=.c) > .dependencies<br>
<br>
strip: $(PROGRAM)<br>
$(STRIP) $(STRIP_ARGS) $(PROGRAM)<br>
Index: flashrom-ioport_x86_only/satasii.c<br>
===================================================================<br>
--- flashrom-ioport_x86_only/satasii.c (Revision 984)<br>
+++ flashrom-ioport_x86_only/satasii.c (Arbeitskopie)<br>
@@ -62,7 +62,7 @@<br>
sii_bar = physmap("SATA SIL registers", addr, 0x100) + reg_offset;<br>
<br>
/* Check if ROM cycle are OK. */<br>
- if ((id != 0x0680) && (!(mmio_readl(sii_bar) & (1 << 26))))<br>
+ if ((id != 0x0680) && (!(mmio_le_readl(sii_bar) & (1 << 26))))<br>
msg_pinfo("Warning: Flash seems unconnected.\n");<br>
<br>
buses_supported = CHIP_BUSTYPE_PARALLEL;<br>
@@ -82,32 +82,32 @@<br>
{<br>
uint32_t ctrl_reg, data_reg;<br>
<br>
- while ((ctrl_reg = mmio_readl(sii_bar)) & (1 << 25)) ;<br>
+ while ((ctrl_reg = mmio_le_readl(sii_bar)) & (1 << 25)) ;<br>
<br>
/* Mask out unused/reserved bits, set writes and start transaction. */<br>
ctrl_reg &= 0xfcf80000;<br>
ctrl_reg |= (1 << 25) | (0 << 24) | ((uint32_t) addr & 0x7ffff);<br>
<br>
- data_reg = (mmio_readl((sii_bar + 4)) & ~0xff) | val;<br>
- mmio_writel(data_reg, (sii_bar + 4));<br>
- mmio_writel(ctrl_reg, sii_bar);<br>
+ data_reg = (mmio_le_readl((sii_bar + 4)) & ~0xff) | val;<br>
+ mmio_le_writel(data_reg, (sii_bar + 4));<br>
+ mmio_le_writel(ctrl_reg, sii_bar);<br>
<br>
- while (mmio_readl(sii_bar) & (1 << 25)) ;<br>
+ while (mmio_le_readl(sii_bar) & (1 << 25)) ;<br>
}<br>
<br>
uint8_t satasii_chip_readb(const chipaddr addr)<br>
{<br>
uint32_t ctrl_reg;<br>
<br>
- while ((ctrl_reg = mmio_readl(sii_bar)) & (1 << 25)) ;<br>
+ while ((ctrl_reg = mmio_le_readl(sii_bar)) & (1 << 25)) ;<br>
<br>
/* Mask out unused/reserved bits, set reads and start transaction. */<br>
ctrl_reg &= 0xfcf80000;<br>
ctrl_reg |= (1 << 25) | (1 << 24) | ((uint32_t) addr & 0x7ffff);<br>
<br>
- mmio_writel(ctrl_reg, sii_bar);<br>
+ mmio_le_writel(ctrl_reg, sii_bar);<br>
<br>
- while (mmio_readl(sii_bar) & (1 << 25)) ;<br>
+ while (mmio_le_readl(sii_bar) & (1 << 25)) ;<br>
<br>
- return (mmio_readl(sii_bar + 4)) & 0xff;<br>
+ return (mmio_le_readl(sii_bar + 4)) & 0xff;<br>
}<br>
Index: flashrom-ioport_x86_only/chipset_enable.c<br>
===================================================================<br>
--- flashrom-ioport_x86_only/chipset_enable.c (Revision 984)<br>
+++ flashrom-ioport_x86_only/chipset_enable.c (Arbeitskopie)<br>
@@ -34,6 +34,8 @@<br>
#include <fcntl.h><br>
#include "flash.h"<br>
<br>
+#if defined(__i386__) || defined(__x86_64__)<br>
+<br>
extern int ichspi_lock;<br>
<br>
static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name)<br>
@@ -1285,8 +1287,11 @@<br>
return 0;<br>
}<br>
<br>
+#endif<br>
+<br>
/* Please keep this list alphabetically sorted by vendor/device. */<br>
const struct penable chipset_enables[] = {<br>
+#if defined(__i386__) || defined(__x86_64__)<br>
{0x10B9, 0x1533, OK, "ALi", "M1533", enable_flash_ali_m1533},<br>
{0x1022, 0x7440, OK, "AMD", "AMD-768", enable_flash_amd8111},<br>
{0x1022, 0x7468, OK, "AMD", "AMD8111", enable_flash_amd8111},<br>
@@ -1417,7 +1422,7 @@<br>
{0x1106, 0x0596, OK, "VIA", "VT82C596", enable_flash_amd8111},<br>
{0x1106, 0x0586, OK, "VIA", "VT82C586A/B", enable_flash_amd8111},<br>
{0x1106, 0x0686, NT, "VIA", "VT82C686A/B", enable_flash_amd8111},<br>
-<br>
+#endif<br>
{},<br>
};<br>
<br>
Index: flashrom-ioport_x86_only/flashrom.c<br>
===================================================================<br>
--- flashrom-ioport_x86_only/flashrom.c (Revision 984)<br>
+++ flashrom-ioport_x86_only/flashrom.c (Arbeitskopie)<br>
@@ -233,6 +233,7 @@<br>
#endif<br>
<br>
#if INTERNAL_SUPPORT == 1<br>
+#if defined(__i386__) || defined(__x86_64__)<br>
{<br>
.name = "it87spi",<br>
.init = it87spi_init,<br>
@@ -250,6 +251,7 @@<br>
.delay = internal_delay,<br>
},<br>
#endif<br>
+#endif<br>
<br>
#if FT2232_SPI_SUPPORT == 1<br>
{<br>
Index: flashrom-ioport_x86_only/internal.c<br>
===================================================================<br>
--- flashrom-ioport_x86_only/internal.c (Revision 984)<br>
+++ flashrom-ioport_x86_only/internal.c (Arbeitskopie)<br>
@@ -99,9 +99,11 @@<br>
#endif<br>
<br>
#if INTERNAL_SUPPORT == 1<br>
-struct superio superio = {};<br>
int force_boardenable = 0;<br>
<br>
+#if defined(__i386__) || defined(__x86_64__)<br>
+struct superio superio = {};<br>
+<br>
void probe_superio(void)<br>
{<br>
superio = probe_superio_ite();<br>
@@ -111,8 +113,9 @@<br>
superio = probe_superio_winbond();<br>
#endif<br>
}<br>
+#endif<br>
<br>
-int is_laptop;<br>
+int is_laptop = 0;<br>
<br>
int internal_init(void)<br>
{<br>
@@ -149,10 +152,13 @@<br>
* mainboard specific flash enable sequence.<br>
*/<br>
coreboot_init();<br>
+<br>
+#if defined(__i386__) || defined(__x86_64__)<br>
dmi_init();<br>
<br>
/* Probe for the Super I/O chip and fill global struct superio. */<br>
probe_superio();<br>
+#endif<br>
<br>
/* Warn if a laptop is detected. */<br>
if (is_laptop)<br>
@@ -173,8 +179,10 @@<br>
"will most likely fail.\n");<br>
}<br>
<br>
+#if defined(__i386__) || defined(__x86_64__)<br>
/* Probe for IT87* LPC->SPI translation unconditionally. */<br>
it87xx_probe_spi_flash(NULL);<br>
+#endif<br>
<br>
board_flash_enable(lb_vendor, lb_part);<br>
<br>
Index: flashrom-ioport_x86_only/board_enable.c<br>
===================================================================<br>
--- flashrom-ioport_x86_only/board_enable.c (Revision 984)<br>
+++ flashrom-ioport_x86_only/board_enable.c (Arbeitskopie)<br>
@@ -28,6 +28,7 @@<br>
#include <fcntl.h><br>
#include "flash.h"<br>
<br>
+#if defined(__i386__) || defined(__x86_64__)<br>
/*<br>
* Helper functions for many Winbond Super I/Os of the W836xx range.<br>
*/<br>
@@ -1299,6 +1300,8 @@<br>
return it8712f_gpio_set(32, 1);<br>
}<br>
<br>
+#endif<br>
+<br>
/**<br>
* Below is the list of boards which need a special "board enable" code in<br>
* flashrom before their ROM chip can be accessed/written to.<br>
@@ -1342,6 +1345,7 @@<br>
struct board_pciid_enable board_pciid_enables[] = {<br>
<br>
/* first pci-id set [4], second pci-id set [4], dmi identifier coreboot id [2], vendor name board name max_rom_... OK? flash enable */<br>
+#if defined(__i386__) || defined(__x86_64__)<br>
{0x10DE, 0x0547, 0x147B, 0x1C2F, 0x10DE, 0x0548, 0x147B, 0x1C2F, NULL, NULL, NULL, "Abit", "AN-M2", 0, NT, nvidia_mcp_gpio2_raise},<br>
{0x8086, 0x2926, 0x147b, 0x1084, 0x11ab, 0x4364, 0x147b, 0x1084, NULL, NULL, NULL, "Abit", "IP35", 0, OK, intel_ich_gpio16_raise},<br>
{0x8086, 0x2930, 0x147b, 0x1083, 0x10ec, 0x8167, 0x147b, 0x1083, NULL, NULL, NULL, "Abit", "IP35 Pro", 0, OK, intel_ich_gpio16_raise},<br>
@@ -1407,7 +1411,7 @@<br>
{0x1106, 0x3123, 0x1106, 0x3123, 0x1106, 0x3059, 0x1106, 0x4161, NULL, NULL, NULL, "Termtek", "TK-3370 (Rev:2.5B)", 0, OK, w836xx_memw_enable_4e},<br>
{0x1106, 0x3177, 0x1106, 0xAA01, 0x1106, 0x3123, 0x1106, 0xAA01, NULL, NULL, NULL, "VIA", "EPIA M/MII/...", 0, OK, via_vt823x_gpio15_raise},<br>
{0x1106, 0x0259, 0x1106, 0x3227, 0x1106, 0x3065, 0x1106, 0x3149, NULL, NULL, NULL, "VIA", "EPIA-N/NL", 0, OK, via_vt823x_gpio9_raise},<br>
-<br>
+#endif<br>
{ 0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL, NULL, NULL, NULL, 0, NT, NULL}, /* end marker */<br>
};<br>
<br>
<br>
<br>
--<br>
<a href="http://www.hailfinger.org/" target="_blank">http://www.hailfinger.org/</a><br>
<br>
</div></div></blockquote></div><br>