I also applied the patch and tested. See the attached log.<br><br><div class="gmail_quote">On Thu, Jun 17, 2010 at 4:37 AM, Carl-Daniel Hailfinger <span dir="ltr"><<a href="mailto:c-d.hailfinger.devel.2006@gmx.net">c-d.hailfinger.devel.2006@gmx.net</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin: 0pt 0pt 0pt 0.8ex; border-left: 1px solid rgb(204, 204, 204); padding-left: 1ex;">Add Nvidia nForce MCP61/MCP65/MCP67/MCP78S/MCP73/MCP79 SPI flashing support.<br>
Fix a few problems in the previously unused SPI bitbanging core.<br>
<br>
This code is untested and may fry your flash chip, explode mysteriously<br>
and abduct your dog.<br>
Do NOT try to read/write/erase with this code until we know that it<br>
behaves correctly.<br>
<br>
Logs from "flashrom -V" on all newer Nvidia nForce chipsets appreciated.<br>
<br>
Huge thanks go to Michael Karcher for reverse engineering the interface<br>
and to Johannes Sjolund for testing multiple iterations of my patch on<br>
his hardware until it worked.<br>
<br>
Signed-off-by: Carl-Daniel Hailfinger <<a href="mailto:c-d.hailfinger.devel.2006@gmx.net">c-d.hailfinger.devel.2006@gmx.net</a>><br>
<br>
Johannes, you can also find this patch near the top at<br>
<a href="http://patchwork.coreboot.org/project/flashrom/list/" target="_blank">http://patchwork.coreboot.org/project/flashrom/list/</a> in case your mailer<br>
corrupts the patch. It applies against latest clean svn.<br>
<br>
Index: flashrom-bitbang_spi_nvidia_mcp/flash.h<br>
===================================================================<br>
--- flashrom-bitbang_spi_nvidia_mcp/flash.h (Revision 1049)<br>
+++ flashrom-bitbang_spi_nvidia_mcp/flash.h (Arbeitskopie)<br>
@@ -128,13 +128,16 @@<br>
void programmer_delay(int usecs);<br>
<br>
enum bitbang_spi_master {<br>
+#if CONFIG_INTERNAL == 1<br>
+#if defined(__i386__) || defined(__x86_64__)<br>
+ BITBANG_SPI_MASTER_MCP,<br>
+#endif<br>
+#endif<br>
BITBANG_SPI_INVALID /* This must always be the last entry. */<br>
};<br>
<br>
extern const int bitbang_spi_master_count;<br>
<br>
-extern enum bitbang_spi_master bitbang_spi_master;<br>
-<br>
struct bitbang_spi_master_entry {<br>
void (*set_cs) (int val);<br>
void (*set_sck) (int val);<br>
@@ -529,10 +532,22 @@<br>
int ft2232_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len);<br>
int ft2232_spi_write_256(struct flashchip *flash, uint8_t *buf);<br>
<br>
+/* mcp6x_spi.c */<br>
+#if CONFIG_INTERNAL == 1<br>
+#if defined(__i386__) || defined(__x86_64__)<br>
+extern void *mcp6x_spibar;<br>
+int mcp6x_spi_init(void);<br>
+void mcp6x_bitbang_set_cs(int val);<br>
+void mcp6x_bitbang_set_sck(int val);<br>
+void mcp6x_bitbang_set_mosi(int val);<br>
+int mcp6x_bitbang_get_miso(void);<br>
+#endif<br>
+#endif<br>
+<br>
/* bitbang_spi.c */<br>
extern int bitbang_spi_half_period;<br>
extern const struct bitbang_spi_master_entry bitbang_spi_master_table[];
<br>
-int bitbang_spi_init(void);<br>
+int bitbang_spi_init(enum bitbang_spi_master master);<br>
int bitbang_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr);<br>
int bitbang_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len);<br>
int bitbang_spi_write_256(struct flashchip *flash, uint8_t *buf);<br>
@@ -635,6 +650,7 @@<br>
SPI_CONTROLLER_SB600,<br>
SPI_CONTROLLER_VIA,<br>
SPI_CONTROLLER_WBSIO,<br>
+ SPI_CONTROLLER_MCP6X_BITBANG,<br>
#endif<br>
#endif<br>
#if CONFIG_FT2232_SPI == 1<br>
Index: flashrom-bitbang_spi_nvidia_mcp/spi25.c<br>
===================================================================<br>
--- flashrom-bitbang_spi_nvidia_mcp/spi25.c (Revision 1049)<br>
+++ flashrom-bitbang_spi_nvidia_mcp/spi25.c (Arbeitskopie)<br>
@@ -178,6 +178,7 @@<br>
case SPI_CONTROLLER_VIA:<br>
case SPI_CONTROLLER_SB600:<br>
case SPI_CONTROLLER_WBSIO:<br>
+ case SPI_CONTROLLER_MCP6X_BITBANG:<br>
#endif<br>
#endif<br>
#if CONFIG_FT2232_SPI == 1<br>
Index: flashrom-bitbang_spi_nvidia_mcp/hwaccess.h<br>
===================================================================<br>
--- flashrom-bitbang_spi_nvidia_mcp/hwaccess.h (Revision 1049)<br>
+++ flashrom-bitbang_spi_nvidia_mcp/hwaccess.h (Arbeitskopie)<br>
@@ -169,6 +169,10 @@<br>
#define __DARWIN__<br>
#endif<br>
<br>
+/* Clarification about OUTB/OUTW/OUTL argument order:<br>
+ * OUT[BWL](val, port)<br>
+ */<br>
+<br>
#if defined(__FreeBSD__) || defined(__DragonFly__)<br>
#include <machine/cpufunc.h><br>
#define off64_t off_t<br>
Index: flashrom-bitbang_spi_nvidia_mcp/bitbang_spi.c<br>
===================================================================<br>
--- flashrom-bitbang_spi_nvidia_mcp/bitbang_spi.c (Revision 1049)<br>
+++ flashrom-bitbang_spi_nvidia_mcp/bitbang_spi.c (Arbeitskopie)<br>
@@ -26,17 +26,29 @@<br>
#include "chipdrivers.h"<br>
#include "spi.h"<br>
<br>
-/* Length of half a clock period in usecs */<br>
-int bitbang_spi_half_period = 0;<br>
+/* Length of half a clock period in usecs. Default to 1 (500 kHz). */<br>
+int bitbang_spi_half_period = 1;<br>
<br>
enum bitbang_spi_master bitbang_spi_master = BITBANG_SPI_INVALID;<br>
<br>
const struct bitbang_spi_master_entry bitbang_spi_master_table[] = {<br>
+#if CONFIG_INTERNAL == 1<br>
+#if defined(__i386__) || defined(__x86_64__)<br>
+ {<br>
+ .set_cs = mcp6x_bitbang_set_cs,<br>
+ .set_sck = mcp6x_bitbang_set_sck,<br>
+ .set_mosi = mcp6x_bitbang_set_mosi,<br>
+ .get_miso = mcp6x_bitbang_get_miso,<br>
+ },<br>
+#endif<br>
+#endif<br>
+<br>
{}, /* This entry corresponds to BITBANG_SPI_INVALID. */<br>
};<br>
<br>
const int bitbang_spi_master_count = ARRAY_SIZE(bitbang_spi_master_table);<br>
<br>
+/* Note that CS# is active low, so val=0 means the chip is active. */<br>
void bitbang_spi_set_cs(int val)<br>
{<br>
bitbang_spi_master_table[bitbang_spi_master].set_cs(val);<br>
@@ -57,10 +69,18 @@<br>
return bitbang_spi_master_table[bitbang_spi_master].get_miso();<br>
}<br>
<br>
-int bitbang_spi_init(void)<br>
+int bitbang_spi_init(enum bitbang_spi_master master)<br>
{<br>
+ bitbang_spi_master = master;<br>
+<br>
+ if (bitbang_spi_master == BITBANG_SPI_INVALID) {<br>
+ msg_perr("Invalid bitbang SPI master. \n
"<br>
+ "Please report a bug at <a href="mailto:flashrom@flashrom.org">flashrom@flashrom.org</a>\n");<br>
+ return 1;<br>
+ }<br>
bitbang_spi_set_cs(1);<br>
bitbang_spi_set_sck(0);<br>
+ bitbang_spi_set_mosi(0);<br>
buses_supported = CHIP_BUSTYPE_SPI;<br>
return 0;<br>
}<br>
@@ -87,6 +107,7 @@<br>
{<br>
static unsigned char *bufout = NULL;<br>
static unsigned char *bufin = NULL;<br>
+ unsigned char *tmp;<br>
static int oldbufsize = 0;<br>
int bufsize;<br>
int i;<br>
@@ -98,20 +119,34 @@<br>
bufsize = max(writecnt + readcnt, 260);<br>
/* Never shrink. realloc() calls are expensive. */<br>
if (bufsize > oldbufsize) {<br>
- bufout = realloc(bufout, bufsize);<br>
- if (!bufout) {<br>
+ tmp = realloc(bufout, bufsize);<br>
+ if (!tmp) {<br>
msg_perr("Out of memory!\n");<br>
+ if (bufout)<br>
+ free(bufout);
<br>
+ bufout = NULL;<br>
if (bufin)<br>
free(bufin);<br>
+ bufin = NULL;<br>
+ oldbufsize = 0;<br>
exit(1);<br>
- }<br>
- bufin = realloc(bufout, bufsize);<br>
- if (!bufin) {<br>
+ } else<br>
+ bufout = tmp;<br>
+<br>
+ tmp = realloc(bufin, bufsize);<br>
+ if (!tmp) {<br>
msg_perr("Out of memory!\n");<br>
+ if (bufin)<br>
+ free(bufin);<br>
+ bufin = NULL;<br>
if (bufout)<br>
free(bufout);<br>
+ bufout = NULL;<br>
+ oldbufsize = 0;<br>
exit(1);<br>
- }<br>
+ } else<br>
+ bufin = tmp;<br>
+<br>
oldbufsize = bufsize;<br>
}<br>
<br>
@@ -135,8 +170,13 @@<br>
<br>
int bitbang_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len)<br>
{<br>
- /* Maximum read length is unlimited, use 64k bytes. */<br>
- return spi_read_chunked(flash, buf, start, len, 64 * 1024);<br>
+ /* Maximum read length is unlimited in theory.<br>
+ * The current implementation can handle reads of up to 65536 bytes.<br>
+ * Please note that you need two buffers of 2n+4 bytes each for a read<br>
+ * of n bytes, resulting in a total memory requirement of 4n+8 bytes.<br>
+ * To conserve memory, read in chunks of 256 bytes.<br>
+ */<br>
+ return spi_read_chunked(flash, buf, start, len, 256);<br>
}<br>
<br>
int bitbang_spi_write_256(struct flashchip *flash, uint8_t *buf)<br>
Index: flashrom-bitbang_spi_nvidia_mcp/spi.c<br>
===================================================================<br>
--- flashrom-bitbang_spi_nvidia_mcp/spi.c (Revision 1049)<br>
+++ flashrom-bitbang_spi_nvidia_mcp/spi.c (Arbeitskopie)<br>
@@ -83,6 +83,13 @@<br>
.read = wbsio_spi_read,<br>
.write_256 = wbsio_spi_write_1,<br>
},<br>
+<br>
+ { /* SPI_CONTROLLER_MCP6X_BITBANG */<br>
+ .command = bitbang_spi_send_command,<br>
+ .multicommand = default_spi_send_multicommand,<br>
+ .read = bitbang_spi_read,<br>
+ .write_256 = bitbang_spi_write_256,<br>
+ },<br>
#endif<br>
#endif<br>
<br>
Index: flashrom-bitbang_spi_nvidia_mcp/Makefile<br>
===================================================================<br>
--- flashrom-bitbang_spi_nvidia_mcp/Makefile (Revision 1049)<br>
+++ flashrom-bitbang_spi_nvidia_mcp/Makefile (Arbeitskopie)<br>
@@ -107,8 +107,12 @@<br>
# Always enable serprog for now. Needs to be disabled on Windows.<br>
CONFIG_SERPROG ?= yes<br>
<br>
-# Bitbanging SPI infrastructure is not used yet.<br>
+# Bitbanging SPI infrastructure, default off unless needed.<br>
+ifeq ($(CONFIG_INTERNAL), yes)<br>
+CONFIG_BITBANG_SPI = yes<br>
+else<br>
CONFIG_BITBANG_SPI ?= no<br>
+endif<br>
<br>
# Always enable 3Com NICs for now.<br>
CONFIG_NIC3COM ?= yes<br>
@@ -151,7 +155,7 @@<br>
FEATURE_CFLAGS += -D'CONFIG_INTERNAL=1'<br>
PROGRAMMER_OBJS += processor_enable.o chipset_enable.o board_enable.o cbtable.o dmi.o internal.o<br>
# FIXME: The PROGRAMMER_OBJS below should only be included on x86.<br>
-PROGRAMMER_OBJS += it87spi.o ichspi.o sb600spi.o wbsio_spi.o<br>
+PROGRAMMER_OBJS += it87spi.o ichspi.o sb600spi.o wbsio_spi.o mcp6x_spi.o
<br>
NEED_PCI := yes<br>
endif<br>
<br>
Index: flashrom-bitbang_spi_nvidia_mcp/chipset_enable.c<br>
===================================================================<br>
--- flashrom-bitbang_spi_nvidia_mcp/chipset_enable.c (Revision 1049)<br>
+++ flashrom-bitbang_spi_nvidia_mcp/chipset_enable.c (Arbeitskopie)<br>
@@ -1092,10 +1092,8 @@<br>
{<br>
int ret = 0;<br>
uint8_t val;<br>
- uint16_t status;<br>
char *busname;<br>
- uint32_t mcp_spibaraddr;<br>
- void *mcp_spibar;<br>
+ uint32_t mcp6x_spibaraddr;<br>
struct pci_dev *smbusdev;<br>
<br>
msg_pinfo("This chipset is not really supported yet. Guesswork...\n");<br>
@@ -1144,40 +1142,33 @@<br>
smbusdev->bus, smbusdev->dev, smbusdev->func);<br>
<br>
/* Locate the BAR where the SPI interface lives. */<br>
- mcp_spibaraddr = pci_read_long(smbusdev, 0x74);<br>
- msg_pdbg("SPI BAR is at 0x%08x, ", mcp_spibaraddr);<br>
+ mcp6x_spibaraddr = pci_read_long(smbusdev, 0x74);<br>
+ msg_pdbg("SPI BAR is at 0x%08x, ", mcp6x_spibaraddr);<br>
/* We hope this has native alignment. We know the SPI interface (well,<br>
* a set of GPIOs that is connected to SPI flash) is at offset 0x530,<br>
* so we expect a size of at least 0x800. Clear the lower bits.<br>
* It is entirely possible that the BAR is 64k big and the low bits are<br>
* reserved for an entirely different purpose.<br>
*/<br>
- mcp_spibaraddr &= ~0x7ff;<br>
- msg_pdbg("after clearing low bits BAR is at 0x%08x\n", mcp_spibaraddr);<br>
+ mcp6x_spibaraddr &= ~0x7ff;<br>
+ msg_pdbg("after clearing low bits BAR is at 0x%08x\n", mcp6x_spibaraddr);<br>
<br>
/* Accessing a NULL pointer BAR is evil. Don't do it. */<br>
- if (mcp_spibaraddr && (buses_supported == CHIP_BUSTYPE_SPI)) {<br>
+ if (mcp6x_spibaraddr && (buses_supported == CHIP_BUSTYPE_SPI)) {<br>
/* Map the BAR. Bytewise/wordwise access at 0x530 and 0x540. */<br>
- mcp_spibar = physmap("MCP67 SPI", mcp_spibaraddr, 0x544);<br>
+ mcp6x_spibar = physmap("Nvidia MCP6x SPI", mcp6x_spibaraddr, 0x544);<br>
<br>
-/* Guessed. If this is correct, migrate to a separate MCP67 SPI driver. */
<br>
-#define MCP67_SPI_CS (1 << 1)<br>
-#define MCP67_SPI_SCK (1 << 2)<br>
-#define MCP67_SPI_MOSI (1 << 3)<br>
-#define MCP67_SPI_MISO (1 << 4)<br>
-#define MCP67_SPI_ENABLE (1 << 0)<br>
-#define MCP67_SPI_IDLE (1 << 8)<br>
-<br>
- status = mmio_readw(mcp_spibar + 0x530);<br>
- msg_pdbg("SPI control is 0x%04x, enable=%i, idle=%i\n",<br>
- status, status & 0x1, (status >> 8) & 0x1);<br>
+ if (mcp6x_spi_init())<br>
+ ret = 1;<br>
+#if 0<br>
/* FIXME: Remove the physunmap once the SPI driver exists. */<br>
- physunmap(mcp_spibar, 0x544);<br>
- } else if (!mcp_spibaraddr && (buses_supported & CHIP_BUSTYPE_SPI)) {<br>
+ physunmap(mcp6x_spibar, 0x544);<br>
+#endif<br>
+ } else if (!mcp6x_spibaraddr && (buses_supported & CHIP_BUSTYPE_SPI)) {<br>
msg_pdbg("Strange. MCP SPI BAR is invalid.\n");<br>
buses_supported &= ~CHIP_BUSTYPE_SPI;
<br>
ret = 1;<br>
- } else if (mcp_spibaraddr && !(buses_supported & CHIP_BUSTYPE_SPI)) {<br>
+ } else if (mcp6x_spibaraddr && !(buses_supported & CHIP_BUSTYPE_SPI)) {<br>
msg_pdbg("Strange. MCP SPI BAR is valid, but chipset apparently"<br>
" doesn't have SPI enabled.\n");<br>
} else {<br>
@@ -1215,8 +1206,7 @@<br>
result = enable_flash_mcp55(dev, name);<br>
break;<br>
case CHIP_BUSTYPE_SPI:<br>
- msg_pinfo("SPI on this chipset is not supported yet.\n");<br>
- buses_supported = CHIP_BUSTYPE_NONE;<br>
+ msg_perr("SPI on this chipset is WIP. DO NOT USE!\n");<br>
break;<br>
default:<br>
msg_pinfo("Something went wrong with bus type detection.\n");<br>
@@ -1241,8 +1231,7 @@<br>
msg_pinfo("LPC on this chipset is not supported yet.\n");<br>
break;<br>
case CHIP_BUSTYPE_SPI:<br>
- msg_pinfo("SPI on this chipset is not supported yet.\n");<br>
- buses_supported = CHIP_BUSTYPE_NONE;<br>
+ msg_perr("SPI on this chipset is WIP. DO NOT USE!\n");<br>
break;<br>
default:<br>
msg_pinfo("Something went wrong with bus type detection.\n");<br>
Index: flashrom-bitbang_spi_nvidia_mcp/mcp6x_spi.c<br>
===================================================================<br>
--- flashrom-bitbang_spi_nvidia_mcp/mcp6x_spi.c (Revision 0)<br>
+++ flashrom-bitbang_spi_nvidia_mcp/mcp6x_spi.c (Revision 0)<br>
@@ -0,0 +1,132 @@<br>
+/*<br>
+ * This file is part of the flashrom project.<br>
+ *<br>
+ * Copyright (C) 2010 Carl-Daniel Hailfinger<br>
+ *<br>
+ * This program is free software; you can redistribute it and/or modify<br>
+ * it under the terms of the GNU General Public License as published by<br>
+ * the Free Software Foundation; version 2 of the License.<br>
+ *<br>
+ * This program is distributed in the hope that it will be useful,<br>
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>
+ * GNU General Public License for more details.<br>
+ *<br>
+ * You should have received a copy of the GNU General Public License<br>
+ * along with this program; if not, write to the Free Software<br>
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA<br>
+ */<br>
+<br>
+/* Driver for the Nvidia MCP6x/MCP7x MCP6X_SPI controller.<br>
+ * Based on clean room reverse engineered docs from<br>
+ * <a href="http://www.flashrom.org/pipermail/flashrom/2009-December/001180.html" target="_blank">http://www.flashrom.org/pipermail/flashrom/2009-December/001180.html</a><br>
+ * created by Michael Karcher.<br>
+ */<br>
+<br>
+#if defined(__i386__) || defined(__x86_64__)<br>
+<br>
+#include <stdint.h><br>
+#include <stdlib.h><br>
+#include <ctype.h><br>
+#include "flash.h"<br>
+<br>
+/* We have two sets of pins, out and in. The numbers for both sets are<br>
+ * independent and are bitshift values, not real pin numbers.<br>
+ */<br>
+<br>
+/* Guessed. */<br>
+#define MCP6X_SPI_CS 1<br>
+#define MCP6X_SPI_SCK 2<br>
+#define MCP6X_SPI_MOSI 3<br>
+#define MCP6X_SPI_MISO 4<br>
+#define MCP6X_SPI_ENABLE 0<br>
+#define MCP6X_SPI_IDLE 8<br>
+<br>
+void *mcp6x_spibar = NULL;<br>
+<br>
+void mcp6x_request_spibus(void)<br>
+{<br>
+ uint8_t byte;<br>
+<br>
+ byte = mmio_readb(mcp6x_spibar + 0x530);<br>
+ byte |= 1 << MCP6X_SPI_ENABLE;<br>
+ mmio_writeb(byte, mcp6x_spibar + 0x530);<br>
+<br>
+ /* Wait until we are allowed to use the SPI bus. */<br>
+ while (!(mmio_readw(mcp6x_spibar + 0x530) & (1 << MCP6X_SPI_IDLE))) ;<br>
+}<br>
+<br>
+void mcp6x_release_spibus(void)<br>
+{<br>
+ uint8_t byte;<br>
+<br>
+ byte = mmio_readb(mcp6x_spibar + 0x530);<br>
+ byte &= ~(1 << MCP6X_SPI_ENABLE);<br>
+ mmio_writeb(byte, mcp6x_spibar + 0x530);<br>
+}<br>
+<br>
+void mcp6x_bitbang_set_cs(int val)<br>
+{<br>
+ uint8_t byte;<br>
+<br>
+ /* Requesting and releasing the SPI bus is handled in here to allow the<br>
+ * chipset to use its own SPI engine for native reads.<br>
+ */<br>
+ if (val == 0)<br>
+ mcp6x_request_spibus();<br>
+<br>
+ byte = mmio_readb(mcp6x_spibar + 0x530);<br>
+ byte &= ~(1 << MCP6X_SPI_CS);<br>
+ byte |= (val << MCP6X_SPI_CS);<br>
+ mmio_writeb(byte, mcp6x_spibar + 0x530);<br>
+<br>
+ if (val == 1)<br>
+ mcp6x_release_spibus();<br>
+}<br>
+<br>
+void mcp6x_bitbang_set_sck(int val)<br>
+{<br>
+ uint8_t byte;<br>
+<br>
+ byte = mmio_readb(mcp6x_spibar + 0x530);<br>
+ byte &= ~(1 << MCP6X_SPI_SCK);<br>
+ byte |= (val << MCP6X_SPI_SCK);<br>
+ mmio_writeb(byte, mcp6x_spibar + 0x530);<br>
+}<br>
+<br>
+void mcp6x_bitbang_set_mosi(int val)<br>
+{<br>
+ uint8_t byte;<br>
+<br>
+ byte = mmio_readb(mcp6x_spibar + 0x530);<br>
+ byte &= ~(1 << MCP6X_SPI_MOSI);<br>
+ byte |= (val << MCP6X_SPI_MOSI);<br>
+ mmio_writeb(byte, mcp6x_spibar + 0x530);<br>
+}<br>
+<br>
+int mcp6x_bitbang_get_miso(void)<br>
+{<br>
+ uint8_t byte;<br>
+<br>
+ byte = mmio_readb(mcp6x_spibar + 0x530);<br>
+ byte = (byte >> MCP6X_SPI_MISO) & 0x1;<br>
+ return byte;<br>
+}<br>
+<br>
+int mcp6x_spi_init(void)<br>
+{<br>
+ uint16_t status;<br>
+<br>
+ status = mmio_readw(mcp6x_spibar + 0x530);<br>
+ msg_pdbg("SPI control is 0x%04x, enable=%i, idle=%i\n",<br>
+ status, (status >> MCP6X_SPI_ENABLE) & 0x1,<br>
+ (status >> MCP6X_SPI_IDLE) & 0x1);<br>
+<br>
+ if (bitbang_spi_init(BITBANG_SPI_MASTER_MCP))<br>
+ return 1;<br>
+ spi_controller = SPI_CONTROLLER_MCP6X_BITBANG;<br>
+<br>
+ return 0;<br>
+}<br>
+<br>
+#endif<br>
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