2010/8/5 Wagner, Helge (GE Intelligent Platforms) <span dir="ltr"><<a href="mailto:Helge.Wagner@ge.com">Helge.Wagner@ge.com</a>></span><br><div class="gmail_quote"><blockquote class="gmail_quote" style="margin: 0pt 0pt 0pt 0.8ex; border-left: 1px solid rgb(204, 204, 204); padding-left: 1ex;">
I have added support for some new intel chipsets.<br></blockquote><div><br>
If only we could have saved you from doing this twice:<br>
<br>
<a href="http://www.flashrom.org/pipermail/flashrom/2010-April/thread.html#2896">http://www.flashrom.org/pipermail/flashrom/2010-April/thread.html#2896</a><br>
<a href="http://patchwork.coreboot.org/patch/1208/">http://patchwork.coreboot.org/patch/1208/</a><br> <br></div><blockquote class="gmail_quote" style="margin: 0pt 0pt 0pt 0.8ex; border-left: 1px solid rgb(204, 204, 204); padding-left: 1ex;">
<br>
(At least) for the QM57 which i have tested an additional patch was<br>
needed as some reserved bits in the "Software Sequencing Flash Control<br>
Register" (SSFC) needs to be programmed to 1 in the QM57.<br></blockquote><blockquote class="gmail_quote" style="margin: 0pt 0pt 0pt 0.8ex; border-left: 1px solid rgb(204, 204, 204); padding-left: 1ex;">
<br>
Signed-off-by: Helge Wagner <<a href="mailto:helge.wagner@ge.com">helge.wagner@ge.com</a>><br></blockquote><blockquote class="gmail_quote" style="margin: 0pt 0pt 0pt 0.8ex; border-left: 1px solid rgb(204, 204, 204); padding-left: 1ex;">
<br>
diff -urN flashrom-0.9.2/chipset_enable.c flashrom/chipset_enable.c<br>
--- flashrom-0.9.2/chipset_enable.c 2010-08-01 01:16:09.000000000<br>
+0200<br>
+++ flashrom/chipset_enable.c 2010-08-05 13:28:29.000000000 +0200<br>
@@ -1011,7 +1011,21 @@<br>
{0x1166, 0x0205, OK, "Broadcom", "HT-1000",<br>
enable_flash_ht1000},<br>
{0x8086, 0x3b00, NT, "Intel", "3400 Desktop",<br>
enable_flash_ich10},<br>
{0x8086, 0x3b01, NT, "Intel", "3400 Mobile",<br>
enable_flash_ich10},<br>
+ {0x8086, 0x3b02, NT, "Intel", "P55",<br>
enable_flash_ich10},<br>
+ {0x8086, 0x3b03, NT, "Intel", "PM55",<br>
enable_flash_ich10},<br>
+ {0x8086, 0x3b06, NT, "Intel", "H55",<br>
enable_flash_ich10},<br>
+ {0x8086, 0x3b07, OK, "Intel", "QM57",<br>
enable_flash_ich10},<br>
+ {0x8086, 0x3b08, NT, "Intel", "H57",<br>
enable_flash_ich10},<br>
+ {0x8086, 0x3b09, NT, "Intel", "HM55",<br>
enable_flash_ich10},<br>
+ {0x8086, 0x3b0a, NT, "Intel", "Q57",<br>
enable_flash_ich10},<br>
+ {0x8086, 0x3b0b, NT, "Intel", "HM57",<br>
enable_flash_ich10},<br>
{0x8086, 0x3b0d, NT, "Intel", "3400 Mobile SFF",<br>
enable_flash_ich10},<br>
+ {0x8086, 0x3b0e, NT, "Intel", "B55",<br>
enable_flash_ich10},<br></blockquote><div><br>See below<br> <br></div><div></div><blockquote class="gmail_quote" style="margin: 0pt 0pt 0pt 0.8ex; border-left: 1px solid rgb(204, 204, 204); padding-left: 1ex;">
+ {0x8086, 0x3b0f, NT, "Intel", "QS57",<br>
enable_flash_ich10},<br>
+ {0x8086, 0x3b12, NT, "Intel", "3400",<br>
enable_flash_ich10},<br>
+ {0x8086, 0x3b14, NT, "Intel", "3420",<br>
enable_flash_ich10},<br>
+ {0x8086, 0x3b16, NT, "Intel", "3450",<br>
enable_flash_ich10},<br>
+ {0x8086, 0x3b1e, NT, "Intel", "B55",<br>
enable_flash_ich10},<br></blockquote><div><br>Thanks for finding/adding "B55": the friendly name for this chipset is empty in forementioned patch (see patchwork).<br>Do you perchance have a verbose log of flashrom (flashrom -V) from that chipset ?<br>
<br></div><blockquote class="gmail_quote" style="margin: 0pt 0pt 0pt 0.8ex; border-left: 1px solid rgb(204, 204, 204); padding-left: 1ex;">
{0x8086, 0x7198, OK, "Intel", "440MX",<br>
enable_flash_piix4},<br>
{0x8086, 0x25a1, OK, "Intel", "6300ESB",<br>
enable_flash_ich_4e},<br>
{0x8086, 0x2670, OK, "Intel", "631xESB/632xESB/3100",<br>
enable_flash_ich_dc},<br>
diff -urN flashrom-0.9.2/ichspi.c flashrom/ichspi.c<br>
--- flashrom-0.9.2/ichspi.c 2010-07-28 00:41:39.000000000 +0200<br>
+++ flashrom/ichspi.c 2010-08-05 13:30:32.000000000 +0200<br>
@@ -560,7 +560,9 @@<br>
}<br>
<br>
/* Assemble SSFS + SSFC */<br>
- temp32 = 0;<br>
+ /* keep reserved bits (23-19,7,0) */<br>
+ temp32 = REGREAD32(ICH9_REG_SSFS);<br>
+ temp32 &= 0xF8008100;<br>
<br>
/* clear error status registers */<br>
temp32 |= (SSFS_CDS + SSFS_FCERR);<br>
<br>
<br>
<br>
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</blockquote></div><br>