<div class="gmail_quote">On Tue, Sep 14, 2010 at 4:59 PM, Carl-Daniel Hailfinger <span dir="ltr"><<a href="mailto:c-d.hailfinger.devel.2006@gmx.net" target="_blank">c-d.hailfinger.devel.2006@gmx.net</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
ICH SPI has the ability to restrict SPI read/write accesses to a given<br>
address range. The low end of the range is configurable by the BIOS (and<br>
by flashrom if the BIOS didn't lock down the flash interface), the high<br>
end of the range is 0xffffff (2^24-1).<br>
This patch checks for an address range restriction and uses the low end<br>
of the allowed range as base for SPI reads. A similar workaround for<br>
REMS/RES opcodes has been committed in r500.<br>
<br>
This fixes read on the Intel D945GCLF mainboard where the stock BIOS<br>
enforces a restricted address range.<br>
Please note that writes need the same fix, but for architectural reasons<br>
that fix will be merged once partial write is available.<br>
<br>
Signed-off-by: Carl-Daniel Hailfinger <<a href="mailto:c-d.hailfinger.devel.2006@gmx.net" target="_blank">c-d.hailfinger.devel.2006@gmx.net</a>><br>
<br>
Index: flashrom-ichspi_read_use_min_addr/spi.c<br>
===================================================================<br>
--- flashrom-ichspi_read_use_min_addr/spi.c (Revision 1165)<br>
+++ flashrom-ichspi_read_use_min_addr/spi.c (Arbeitskopie)<br>
@@ -22,6 +22,7 @@<br>
* Contains the generic SPI framework<br>
*/<br>
<br>
+#include <string.h><br>
#include "flash.h"<br>
#include "flashchips.h"<br>
#include "chipdrivers.h"<br>
@@ -207,6 +208,7 @@<br>
<br>
int spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len)<br>
{<br>
+ int addrbase = 0;<br>
if (!spi_programmer[spi_controller].read) {<br>
msg_perr("%s called, but SPI read is unsupported on this "<br>
"hardware. Please report a bug at "<br>
@@ -214,7 +216,26 @@<br>
return 1;<br>
}<br>
<br>
- return spi_programmer[spi_controller].read(flash, buf, start, len);<br>
+ /* Check if the chip fits between lowest valid and highest possible<br>
+ * address. Highest possible address with the current SPI implementation<br>
+ * means 0xffffff, the highest unsigned 24bit number.<br>
+ */<br>
+ addrbase = spi_get_valid_read_addr();<br>
+ if (addrbase + flash->total_size * 1024 > (1 << 24)) {<br>
+ msg_perr("Flash chip size exceeds the allowed access window. ");<br>
+ msg_perr("Read will probably fail.\n");<br>
+ /* Try to get the best alignment subject to constraints. */<br>
+ addrbase = (1 << 24) - flash->total_size * 1024;<br>
+ }<br>
+ /* Check if alignment is native (at least the largest power of two which<br>
+ * is a factor of the mapped size of the chip).<br>
+ */<br>
+ if (ffs(flash->total_size * 1024) > (ffs(addrbase) ? : 33)) {<br>
+ msg_perr("Flash chip is not aligned natively in the allowed "<br>
+ "access window.\n");<br>
+ msg_perr("Read will probably return garbage.\n");<br>
+ }<br>
+ return spi_programmer[spi_controller].read(flash, buf, addrbase + start, len);<br>
}<br>
<br>
/*<br></blockquote><div><br></div><div>I applied and tested the patch with positive results: <a href="http://paste.flashrom.org/view.php?id=79" target="_blank">http://paste.flashrom.org/view.php?id=79</a></div><div><br>
</div><div>Acked-by: David Hendricks <<a href="mailto:dhendrix@google.com" target="_blank">dhendrix@google.com</a>></div>
<div><br></div></div>-- <br>David Hendricks (dhendrix)<br>Systems Software Engineer, Google Inc.<br>