<div class="gmail_quote">Looks great! I applied your patch against the Chromium OS branch and successfully tested read and write operations on a Cr48.</div><div class="gmail_quote"><br></div><div class="gmail_quote">Acked-by: David Hendricks <<a href="mailto:dhendrix@google.com">dhendrix@google.com</a>></div>
<div class="gmail_quote"><br></div><div class="gmail_quote">On Thu, Mar 3, 2011 at 4:38 PM, Carl-Daniel Hailfinger <span dir="ltr"><<a href="mailto:c-d.hailfinger.devel.2006@gmx.net">c-d.hailfinger.devel.2006@gmx.net</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex;">Various IT85* cleanups and fixes.<br>
<br>
Fix a few typos.<br>
Change the EC memory region mapping name.<br>
Drop unused function parameter.<br>
Use mmio_writeb()/mmio_readb() to get reliable access to volatile memory<br>
locations instead of plain pointer access which gets optimized away by gcc.<br>
Use own it85_* SPI high-level chip read/write functions instead of<br>
relying on unrelated ICH functions.<br>
<br>
AFAICS this should be mergeable both in the chromium tree and vanilla<br>
flashrom.<br>
<br>
Signed-off-by: Carl-Daniel Hailfinger <<a href="mailto:c-d.hailfinger.devel.2006@gmx.net">c-d.hailfinger.devel.2006@gmx.net</a>><br>
<br>
Index: flashrom-it85spi_cleanup/it85spi.c<br>
===================================================================<br>
--- flashrom-it85spi_cleanup/it85spi.c (Revision 1263)<br>
+++ flashrom-it85spi_cleanup/it85spi.c (Arbeitskopie)<br>
@@ -37,7 +37,7 @@<br>
#define MAX_TIMEOUT 100000<br>
#define MAX_TRY 5<br>
<br>
-/* Constans for I/O ports */<br>
+/* Constants for I/O ports */<br>
#define ITE_SUPERIO_PORT1 0x2e<br>
#define ITE_SUPERIO_PORT2 0x4e<br>
<br>
@@ -52,13 +52,14 @@<br>
#define CHIP_CHIP_VER_REG 0x22<br>
<br>
/* These are standard Super I/O 16-bit base address registers */<br>
-#define SHM_IO_BAD0 0x60 /* big-endian, this is high bits */<br>
-#define SHM_IO_BAD1 0x61<br>
+#define SHM_IO_BAR0 0x60 /* big-endian, this is high bits */<br>
+#define SHM_IO_BAR1 0x61<br>
<br>
-/* 8042 keyboard controller uses an input buffer and an output buffer to<br>
- * communicate with host CPU. Both buffers are 1-byte depth. That means the<br>
- * IBF is set to 1 when host CPU sends a command to input buffer (standing on<br>
- * the EC side). IBF is cleared to 0 once the command is read by EC. */<br>
+/* The 8042 keyboard controller uses an input buffer and an output buffer to<br>
+ * communicate with the host CPU. Both buffers are 1-byte depth. That means<br>
+ * IBF is set to 1 when the host CPU sends a command to the input buffer<br>
+ * of the EC. IBF is cleared to 0 once the command is read by the EC.<br>
+ */<br>
#define KB_IBF (1 << 1) /* Input Buffer Full */<br>
#define KB_OBF (1 << 0) /* Output Buffer Full */<br>
<br>
@@ -278,8 +279,8 @@<br>
#ifdef LPC_IO<br>
/* Get LPCPNP of SHM. That's big-endian */<br>
sio_write(superio.port, LDNSEL, 0x0F); /* Set LDN to SHM (0x0F) */<br>
- shm_io_base = (sio_read(superio.port, SHM_IO_BAD0) << 8) +<br>
- sio_read(superio.port, SHM_IO_BAD1);<br>
+ shm_io_base = (sio_read(superio.port, SHM_IO_BAR0) << 8) +<br>
+ sio_read(superio.port, SHM_IO_BAR1);<br>
msg_pdbg("%s():%d shm_io_base=0x%04x\n", __func__, __LINE__,<br>
shm_io_base);<br>
<br>
@@ -296,8 +297,8 @@<br>
INDIRECT_A3(shm_io_base, (base >> 24));<br>
#endif<br>
#ifdef LPC_MEMORY<br>
- base = (chipaddr)programmer_map_flash_region("flash base", 0xFFFFF000,<br>
- 0x1000);<br>
+ base = (chipaddr)programmer_map_flash_region("it85 communication",<br>
+ 0xFFFFF000, 0x1000);<br>
msg_pdbg("%s():%d base=0x%08x\n", __func__, __LINE__,<br>
(unsigned int)base);<br>
ce_high = (unsigned char*)(base + 0xE00); /* 0xFFFFFE00 */<br>
@@ -328,7 +329,7 @@<br>
}<br>
<br>
/* Called by internal_init() */<br>
-int it85xx_probe_spi_flash(const char *name)<br>
+int it85xx_probe_spi_flash(void)<br>
{<br>
int ret;<br>
<br>
@@ -377,14 +378,14 @@<br>
INDIRECT_A1(shm_io_base, (((unsigned long int)ce_low) >> 8) & 0xff);<br>
#endif<br>
#ifdef LPC_MEMORY<br>
- *ce_high = 0;<br>
+ mmio_writeb(0, ce_high);<br>
#endif<br>
for (i = 0; i < writecnt; ++i) {<br>
#ifdef LPC_IO<br>
INDIRECT_WRITE(shm_io_base, writearr[i]);<br>
#endif<br>
#ifdef LPC_MEMORY<br>
- *ce_low = writearr[i];<br>
+ mmio_writeb(writearr[i], ce_low);<br>
#endif<br>
}<br>
for (i = 0; i < readcnt; ++i) {<br>
@@ -392,7 +393,7 @@<br>
readarr[i] = INDIRECT_READ(shm_io_base);<br>
#endif<br>
#ifdef LPC_MEMORY<br>
- readarr[i] = *ce_low;<br>
+ readarr[i] = mmio_readb(ce_low);<br>
#endif<br>
}<br>
#ifdef LPC_IO<br>
@@ -400,10 +401,20 @@<br>
INDIRECT_WRITE(shm_io_base, 0xFF); /* Write anything to this address.*/<br>
#endif<br>
#ifdef LPC_MEMORY<br>
- *ce_high = 0;<br>
+ mmio_writeb(0, ce_high);<br>
#endif<br>
<br>
return 0;<br>
}<br>
<br>
+int it85_spi_read(struct flashchip *flash, uint8_t * buf, int start, int len)<br>
+{<br>
+ return spi_read_chunked(flash, buf, start, len, 64);<br>
+}<br>
+<br>
+int it85_spi_write_256(struct flashchip *flash, uint8_t * buf, int start, int len)<br>
+{<br>
+ return spi_write_chunked(flash, buf, start, len, 64);<br>
+}<br>
+<br>
#endif<br>
Index: flashrom-it85spi_cleanup/spi.c<br>
===================================================================<br>
--- flashrom-it85spi_cleanup/spi.c (Revision 1263)<br>
+++ flashrom-it85spi_cleanup/spi.c (Arbeitskopie)<br>
@@ -58,8 +58,8 @@<br>
{ /* SPI_CONTROLLER_IT85XX */<br>
.command = it85xx_spi_send_command,<br>
.multicommand = default_spi_send_multicommand,<br>
- .read = ich_spi_read,<br>
- .write_256 = ich_spi_write_256,<br>
+ .read = it85_spi_read,<br>
+ .write_256 = it85_spi_write_256,<br>
},<br>
<br>
{ /* SPI_CONTROLLER_IT87XX */<br>
Index: flashrom-it85spi_cleanup/programmer.h<br>
===================================================================<br>
--- flashrom-it85spi_cleanup/programmer.h (Revision 1263)<br>
+++ flashrom-it85spi_cleanup/programmer.h (Arbeitskopie)<br>
@@ -588,9 +588,11 @@<br>
struct superio probe_superio_ite85xx(void);<br>
int it85xx_spi_init(void);<br>
int it85xx_shutdown(void);<br>
-int it85xx_probe_spi_flash(const char *name);<br>
+int it85xx_probe_spi_flash(void);<br>
int it85xx_spi_send_command(unsigned int writecnt, unsigned int readcnt,<br>
const unsigned char *writearr, unsigned char *readarr);<br>
+int it85_spi_read(struct flashchip *flash, uint8_t * buf, int start, int len);<br>
+int it85_spi_write_256(struct flashchip *flash, uint8_t * buf, int start, int len);<br>
<br>
/* it87spi.c */<br>
void enter_conf_mode_ite(uint16_t port);<br>
<font color="#888888"><br>
<br>
--<br>
<a href="http://www.hailfinger.org/" target="_blank">http://www.hailfinger.org/</a><br>
<br>
</font></blockquote></div><br><br clear="all"><br>-- <br>David Hendricks (dhendrix)<br>Systems Software Engineer, Google Inc.<br>