<font size=2 face="sans-serif">Hallo Stefan,</font>
<br>
<br><font size=2 face="sans-serif">Wir könnten eigentlich deutsch sprechen
;). </font>
<br>
<br><font size=2 face="sans-serif">Ja, unsere Kunden benützen auch flashrom.
Wir haben usere EFI shell flashing tool, aber die Kunden benützen das Linux
Shell am liebsten, besonders wenn du viele Clusters/Servers flashen muss.
</font>
<br>
<br><font size=2 face="sans-serif">Stimmt, das SPI interface in « Intel
Chipset Serie 6 » ist fast wie die vorausgegangen. Es gibt ME protection
und special « unlocking sequence » mit special opcodes.</font>
<br>
<br><font size=2 face="sans-serif">Aber mein Problem ist vor diesen Sachen.
« chipset_flash_enable » findet nicht das PCH:</font>
<br><font size=2 face="sans-serif"> «
This chipset supports the following protocols: Non-SPI.
WARNING: No chipset found. Flash detection will most likely
fail. »</font>
<br>
<br><font size=2 face="sans-serif">und das PCH device_id (Vendor ID:0x8086,
Device ID:0x244e ) existiert nicht in das «chipset_enables » stuct. ( mein
PCH heisst Patsburg oder C200 chipset ). </font>
<br>
<br><font size=2 face="sans-serif">Wenn ich « enable_flash_ich10 » Funktion
nötige, es funkioniert auch nicht.</font>
<br><font size=2 face="sans-serif"> Maximum
FWH chip size: 0x0 bytes BIOS Lock Enable:
disabled, BIOS Write Enable: disabled, BIOS_CNTL is 0x0
tried to set 0xdc to 0x1 on ICH10 failed (WARNING ONLY)
Root Complex Register Block address = 0x0
Error accessing ICH RCRB, 0x4000 bytes at 0x00000000
/dev/mem mmap failed: Resource temporarily
unavailableIch werde vielleicht eine neue funktion schreiben ;).</font>
<br><font size=2 face="sans-serif">Vielen Dank.</font>
<br>
<br><font size=2 face="sans-serif">Mit freundlichen Grüßen</font>
<br><font size=2 face="sans-serif">Amine Rebai</font>
<br>
<br>
<br>
<br>
<br><font size=1 color=#5f5f5f face="sans-serif">De :
</font><font size=1 face="sans-serif">Stefan Tauner <stefan.tauner@student.tuwien.ac.at></font>
<br><font size=1 color=#5f5f5f face="sans-serif">A :
</font><font size=1 face="sans-serif">Mohammed-Amine.Rebai@bull.net</font>
<br><font size=1 color=#5f5f5f face="sans-serif">Cc :
</font><font size=1 face="sans-serif">flashrom@flashrom.org</font>
<br><font size=1 color=#5f5f5f face="sans-serif">Date :
</font><font size=1 face="sans-serif">27/05/2011 20:02</font>
<br><font size=1 color=#5f5f5f face="sans-serif">Objet :
</font><font size=1 face="sans-serif">Re: [flashrom]
Intel SandyBridge serie 6 chipsets support</font>
<br>
<hr noshade>
<br>
<br>
<br><tt><font size=2>On Fri, 27 May 2011 14:58:57 +0200<br>
Mohammed-Amine.Rebai@bull.net wrote:<br>
<br>
> Dear Flahsrom representant,<br>
hello!<br>
<br>
> I am a Bios engineer at BULL, a major european server and supercomputer
<br>
> company «www.bull.com » .<br>
> <br>
> First of all, I would like to thank you for the great job you are
doing, <br>
> we use your utility a lot.<br>
nice to hear that, thank you. is it offered to your customers too?<br>
<br>
> I would like to know if you are planning to support the Bios SPI flash
<br>
> flashing on the Intel SandyBridge architecture, especially the Intel
6 <br>
> series chipset/C200/Patsburg platform controller hub?<br>
<br>
the spi interface of the 6 series chipset is very similar to the<br>
previous ones and as long as there is no locking in place (i am talking<br>
about PR0-PR4 and related "security" stuff) it may already work,
have<br>
you tried it?<br>
<br>
in case of locking in place (that might be a requirement in nowadays<br>
chipsets due to the requirement of using the ME) flashrom would not<br>
work yet. i am working on this problem within the scope of my google<br>
summer of code project which should be completed by the end of summer.<br>
dont hold your breath though please ;)<br>
<br>
-- <br>
Kind regards/Mit freundlichen Grüßen, Stefan Tauner<br>
</font></tt>
<br>