<div class="gmail_quote">On Fri, Jan 6, 2012 at 5:12 AM, Raghuramchary Jallipalli <span dir="ltr"><<a href="mailto:Raghuramchary.Jallipalli@lntinfotech.com" target="_blank">Raghuramchary.Jallipalli@lntinfotech.com</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">The force option enable worked and we were able to program the AT25DF321A flash. But the contents are wrong and the board was not able to come up. Please see attached for the verbose output for both read and write.<br>
</blockquote><div><br></div><div>There is a high likelihood that either the Management Engine (ME) or embedded controller (EC) is interfering with Flashrom operation.</div><div><br></div><div>One concern is that flashrom does not appear to set the op.atomic field properly:</div>
<div><div><font face="'courier new', monospace">0x94: 0x0606 (PREOP)</font></div></div><div><div><font face="'courier new', monospace">0x96: 0x0be4 (OPTYPE)</font></div><div><font face="'courier new', monospace">0x98: 0x02030105 (OPMENU)</font></div>
<div><font face="'courier new', monospace">0x9C: 0xff9f3c20 (OPMENU+4)</font></div><div><font face="'courier new', monospace">0xA0: 0x00000000 (BBAR)</font></div><div><font face="'courier new', monospace">0xD0: 0x00000000 (FPB)</font></div>
<div><font face="'courier new', monospace">Reading OPCODES... done</font></div><div><font face="'courier new', monospace">preop0=0x06, preop1=0x06</font></div><div><font face="'courier new', monospace">op[0]=0x05, 0, 0</font></div>
<div><font face="'courier new', monospace">op[1]=0x01, 1, 0</font></div><div><font face="'courier new', monospace">op[2]=0x03, 2, 0</font></div><div><font face="'courier new', monospace">op[3]=0x02, 3, 0</font></div>
<div><font face="'courier new', monospace">op[4]=0x20, 3, 0</font></div><div><font face="'courier new', monospace">op[5]=0x3c, 2, 0</font></div><div><font face="'courier new', monospace">op[6]=0x9f, 0, 0</font></div>
<div><font face="'courier new', monospace">op[7]=0xff, 0, 0</font></div></div><div><br></div><div>The third column shows that none of the opcodes are configured as atomic cycles. Thus, Flashrom does not know to set the SPIC_ACS bit (<a href="http://flashrom.org/trac/flashrom/browser/trunk/ichspi.c#L782" target="_blank">http://flashrom.org/trac/flashrom/browser/trunk/ichspi.c#L782</a>) when processing these opcodes.</div>
<div><br></div><div>If the "atomic" field is not set properly, then it is possible for ME or EC to interfere with flashrom in between write enable (WREN) opcodes such as block erase and program page.</div>
<div><br></div><div>On Fri, Jan 6, 2012 at 5:12 AM, Raghuramchary Jallipalli <span dir="ltr"><<a href="mailto:Raghuramchary.Jallipalli@lntinfotech.com" target="_blank">Raghuramchary.Jallipalli@lntinfotech.com</a>></span> wrote: </div>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">For your info, the board has two flashes(each 4MB) and the bios resides on the second(we have a jumper option to select the flash device). We are confused whether the flashrom selects the correct flash device and program it.<br>
</blockquote><div><br></div><div>Are both ROMs logically present? Or will the jumper only enable one ROM at a given time?</div><div><br></div><div>If there are multiple ROMs present, then Flashrom use the "Hardware Sequencing" method of flashing when it detects the "Number of Components" (NC) > 0 in the flash descriptor region: <a href="http://flashrom.org/trac/flashrom/browser/trunk/ichspi.c#L1742" target="_blank">http://flashrom.org/trac/flashrom/browser/trunk/ichspi.c#L1742</a></div>
<div><br></div><div>See FLMAP0 in the Intel documentation for more details, and ensure the NC field is programmed appropriately for your mainboard configuration.</div><div><br></div></div>-- <br>David Hendricks (dhendrix)<br>
Systems Software Engineer, Google Inc.<br>