<font size=2 face="sans-serif">Hello Stefan,</font>
<br>
<br>
<br><font size=2 face="sans-serif">Thanks for the comments about N25Q128...
(my patch was based on N25Q64)</font>
<br><font size=2 face="sans-serif">I'll try to have a look to the layout
feature (but currently I'm very busy).</font>
<br>
<br><font size=2 face="sans-serif">the main idea is to unlock the regions
from the ME</font>
<br><font size=2 face="sans-serif">Document with datails about ME messages
for X79/C600 are Intel Restricted... :-(</font>
<br><font size=2 face="sans-serif">But seems that ME messages (HMRFPO and
others) used in Maho Bay and Chief River platform are the same,</font>
<br><font size=2 face="sans-serif">and "BIOS Writers Guide" for
these systems (document 490124) is only "Intel Confidential"
(and HMRFPO is described in this document...)</font>
<br><font size=2 face="sans-serif">I hope that Intel will soon set all
these documents available to everybody...</font>
<br>
<br><font size=2 face="sans-serif">note: there are lot of work to do...
first, there's only one IOCTL developed in mei driver (mei driver may be
the best way to interact with ME...)</font>
<br>
<br>
<br>
<br><font size=2 face="sans-serif">Other topic (may be more related to
layout feature): currently, when using flashrom for BIOS upgrade, Serial
Numbers and some other information in DMI are overwritten...</font>
<br><font size=2 face="sans-serif">(seen on Supermicro motherboards)</font>
<br><font size=2 face="sans-serif">I don't have details, but it may be
nice to investigate this issue...</font>
<br>
<br>
<br><font size=2 face="sans-serif">Best regards</font>
<br>
<br><font size=2 face="sans-serif">--</font>
<br><font size=2 face="sans-serif">Fred</font>
<br>
<br>
<br>
<br>
<br>
<br>
<br>
<br>
<br>
<br><font size=1 color=#5f5f5f face="sans-serif">De :
</font><font size=1 face="sans-serif">Stefan Tauner <stefan.tauner@student.tuwien.ac.at></font>
<br><font size=1 color=#5f5f5f face="sans-serif">A :
</font><font size=1 face="sans-serif">frederic.temporelli@bull.net</font>
<br><font size=1 color=#5f5f5f face="sans-serif">Cc :
</font><font size=1 face="sans-serif">flashrom@flashrom.org</font>
<br><font size=1 color=#5f5f5f face="sans-serif">Date :
</font><font size=1 face="sans-serif">07/06/2012 08:02 AM</font>
<br><font size=1 color=#5f5f5f face="sans-serif">Objet :
</font><font size=1 face="sans-serif">Re: [flashrom]
add Numonyx/Micron N25Q128</font>
<br>
<hr noshade>
<br>
<br>
<br><tt><font size=2>On Sat, 9 Jun 2012 14:51:15 +0200<br>
frederic.temporelli@bull.net wrote:<br>
<br>
> Hello<br>
> <br>
> <br>
> Numonyx/Micron N25Q128 is used on new X9 motherboards from Supermicro
(X9DRT, ...)<br>
> <br>
> Specs are availbale on Micron WWW site:<br>
> </font></tt><a href=http://www.micron.com/~/media/Documents/Products/Data%20Sheet/NOR%20Flash/Serial%20NOR/N25Q/N25Q_128_3_Volt_with_boot_sector.pdf><tt><font size=2>http://www.micron.com/~/media/Documents/Products/Data%20Sheet/NOR%20Flash/Serial%20NOR/N25Q/N25Q_128_3_Volt_with_boot_sector.pdf</font></tt></a><tt><font size=2><br>
> <br>
> Following patch add this chip to flashrom. Probe is OK.<br>
> Due to Manageability Engine, some work is required before being able
to test READ/ERASE/WRITE...<br>
> <br>
> =================================================================================<br>
> Signed-off-by: Frederic Temporelli <frederic.temporelli@bull.net><br>
> <br>
> diff -urN flashrom-0.9.5.2-r1540/flashchips.c flashrom-0.9.5.2-r1540-n25q128/flashchips.c<br>
> --- flashrom-0.9.5.2-r1540/flashchips.c 2012-05-20 23:32:32.000000000
+0000<br>
> +++ flashrom-0.9.5.2-r1540-n25q128/flashchips.c 2012-06-09 14:41:07.064141076
+0000<br>
> @@ -5453,6 +5453,37 @@<br>
> },<br>
> <br>
> {<br>
> + .vendor
= "Numonyx",<br>
> + .name
= "N25Q128",<br>
> + .bustype
= BUS_SPI,<br>
> + .manufacture_id
= ST_ID,<br>
> + .model_id
= ST_N25Q128,<br>
> + .total_size
= 16384,<br>
> + .page_size
= 256,<br>
> + .feature_bits
= FEATURE_WRSR_WREN | FEATURE_OTP,<br>
> + .tested
= TEST_OK_PROBE,<br>
> + .probe
= probe_spi_rdid,<br>
> + .probe_timing
= TIMING_ZERO,<br>
> + .block_erasers
=<br>
> + {<br>
> +
{<br>
> +
.eraseblocks = { {4 * 1024, 4096 } },<br>
> +
.block_erase = spi_block_erase_20,<br>
> +
}, {<br>
> +
.eraseblocks = { {64 * 1024, 256} },<br>
> +
.block_erase = spi_block_erase_d8,<br>
> +
}, {<br>
> +
.eraseblocks = { {16 * 1024 * 1024,
1} },<br>
> +
.block_erase = spi_block_erase_c7,<br>
> +
}<br>
> + },<br>
> + .unlock
= spi_disable_blockprotect,<br>
> + .write
= spi_chip_write_256,<br>
> + .read
= spi_chip_read,<br>
> + },<br>
> +<br>
> +<br>
> + {<br>
> .vendor
= "PMC",<br>
> .name
= "Pm25LV010",<br>
> .bustype
= BUS_SPI,<br>
> diff -urN flashrom-0.9.5.2-r1540/flashchips.h flashrom-0.9.5.2-r1540-n25q128/flashchips.h<br>
> --- flashrom-0.9.5.2-r1540/flashchips.h 2012-05-14 01:51:46.000000000
+0000<br>
> +++ flashrom-0.9.5.2-r1540-n25q128/flashchips.h 2012-06-08 20:46:47.225385676
+0000<br>
> @@ -587,6 +587,7 @@<br>
> #define ST_M29W040B 0xE3<br>
> #define ST_M29W512B 0x27<br>
> #define ST_N25Q064
0xBA17<br>
> +#define ST_N25Q128 0xBA18
/* also Numonyx N25Q128 */<br>
> <br>
> #define SYNCMOS_MVC_ID 0x40
/* SyncMOS (SM) and Mosel Vitelic Corporation (MVC) */<br>
> #define MVC_V29C51000T 0x00<br>
> =================================================================================<br>
<br>
hello and thanks for your patch!<br>
this chip is a bit complicated and we cant merge the patch as it is.<br>
they have used the same plane RDID for multiple variants of the chip.<br>
some attributes are not important for flashrom and can be ignored, but<br>
some are very important, namely the boot sector layout. quote from p.52:<br>
<br>
> The N25Q128 is available in the following architecture versions:<br>
> Bottom version, 64 KB uniform sectors plus 8 bottom boot sectors (each
with 16<br>
> subsectors),<br>
> Top version, 64 KB uniform sectors plus 8 top boot sectors (each with
16 subsectors)<br>
> Uniform version, 64 KB uniform sectors without any boot sectors and
subsectors.<br>
<br>
the good news is that this differences can be detected by an extended<br>
RDID command in its 5th byte (1 manufacturer, 2 device, 1 length of the<br>
following extended data, the first EDID byte we want), see table 15.<br>
of this 5th byte we need to look at the first two bits to determine the<br>
architecture, see table 16.<br>
<br>
our current infrastructure (probe_spi_rdid_generic) cant handle that,<br>
but should... so we will plan a change, but please dont expect it to<br>
happen too soon.<br>
<br>
the bad news is that i am not even sure if the subsector erase commands<br>
work as flashrom expects. flashrom wants to use the same erase opcode<br>
for the hole address space, even for non-uniform layouts. this usually<br>
works fine, but afaics it is not specified in the datasheet what<br>
happens if one uses the subsector erase opcode on a non-subsector *on<br>
devices that actually have subsectors* (the emphasis stems from the<br>
fact that it *is* defined, that the subsector erase command is ignore<br>
by the uniform model: "Any Subsector Erase (SSE) instruction in devices<br>
with uniform architecture (meaning no boot sectors with subsectors) is<br>
rejected without having any effects on the device." (p. 98).<br>
<br>
other interesting bits of this chips:<br>
- bit#5 of the status register "is used in conjunction with the Block<br>
Protect (BP3, BP2, BP1, BP0) bits to determine if the protected
area<br>
defined by the Block Protect bits starts from the top or the bottom<br>
of the memory array"<br>
- a flag status register that gives more info than the "legacy spi<br>
status register"<br>
- a non-volatile configuration register to configure dummy clock<br>
cycles, output driver strength and other stuff, and a volatile<br>
register that overrides the nvm settings<br>
<br>
the first two points can be somewhat ignored by us, the generic "write
0<br>
to the status register" is good enough to unlock the device.<br>
<br>
regarding the ME: are you aware of my layout patches, that enable read,<br>
erase and verify on user-definable address ranges? see the patches from<br>
2011-12-25 at </font></tt><a href=http://patchwork.coreboot.org/project/flashrom/list/><tt><font size=2>http://patchwork.coreboot.org/project/flashrom/list/</font></tt></a><tt><font size=2><br>
-- <br>
Kind regards/Mit freundlichen Grüßen, Stefan Tauner<br>
</font></tt>
<br>