I can run flashrom under linux for read, but not yet write.<div>Sandy Bridge / Patsburg C602<br clear="all"><div>When I attempt to use a layout file, it likes it, but ignores it. No complaints, but instead of doing the 4 MB bios, it does the whole flash (8MB).</div>
<div><br></div><div>command line:</div><div><br></div><div><div> ./flashrom -r fll-19-w-bios.bin -c W25Q64 -p internal:laptop=this_is_not_a_laptop -i bios -l layout.flash -o fl-bios.log</div></div><div><br></div><div>layout.flash:</div>
<div><br></div><div><div>00000000:0000ffff desc</div><div>00010000:003fffff me</div><div>00400000:007fffff bios</div></div><div><br></div><div>fl-bios.log:</div><div><br></div><div><div>flashrom v0.9.6.1-r1653 on Linux 3.7.5-201.fc18.x86_64 (x86_64)</div>
<div>flashrom was built with libpci 3.1.10, GCC 4.7.2 20121109 (Red Hat 4.7.2-8), little endian</div><div>Command line (12 args): ./flashroml -r fll-19-w-bios.bin -c W25Q64 -p internal:laptop=this_is_not_a_laptop -i bios -l layout.flash -o fl-bios.log</div>
<div>romlayout 00000000 - 0000ffff named desc</div><div>romlayout 00010000 - 003fffff named me</div><div>romlayout 00400000 - 007fffff named bios</div><div>Using region: "bios".</div><div>Calibrating delay loop... OS timer resolution is 1 usecs, 1781M loops per second, 10 myus = 10 us, 100 myus = 99 us, 1000 myus = 1004 us, 10000 myus = 9992 us, 4 myus = 4 us, OK.</div>
<div>Initializing internal programmer</div><div>No coreboot table found.</div><div>DMI string system-manufacturer: "To be filled by O.E.M."</div><div>DMI string system-product-name: "To be filled by O.E.M."</div>
<div>DMI string system-version: "To be filled by O.E.M."</div><div>DMI string baseboard-manufacturer: "To be filled by O.E.M."</div><div>DMI string baseboard-product-name: "To be filled by O.E.M."</div>
<div>DMI string baseboard-version: "To be filled by O.E.M."</div><div>DMI string chassis-type: "Desktop"</div><div>Found chipset "Intel X79" with PCI ID 8086:1d41. Enabling flash write... </div>
<div>0xfff80000/0xffb80000 FWH IDSEL: 0x0</div><div>0xfff00000/0xffb00000 FWH IDSEL: 0x0</div><div>0xffe80000/0xffa80000 FWH IDSEL: 0x1</div><div>0xffe00000/0xffa00000 FWH IDSEL: 0x1</div><div>0xffd80000/0xff980000 FWH IDSEL: 0x2</div>
<div>0xffd00000/0xff900000 FWH IDSEL: 0x2</div><div>0xffc80000/0xff880000 FWH IDSEL: 0x3</div><div>0xffc00000/0xff800000 FWH IDSEL: 0x3</div><div>0xff700000/0xff300000 FWH IDSEL: 0x4</div><div>0xff600000/0xff200000 FWH IDSEL: 0x5</div>
<div>0xff500000/0xff100000 FWH IDSEL: 0x6</div><div>0xff400000/0xff000000 FWH IDSEL: 0x7</div><div>0xfff80000/0xffb80000 FWH decode enabled</div><div>0xfff00000/0xffb00000 FWH decode enabled</div><div>0xffe80000/0xffa80000 FWH decode enabled</div>
<div>0xffe00000/0xffa00000 FWH decode enabled</div><div>0xffd80000/0xff980000 FWH decode enabled</div><div>0xffd00000/0xff900000 FWH decode enabled</div><div>0xffc80000/0xff880000 FWH decode enabled</div><div>0xffc00000/0xff800000 FWH decode enabled</div>
<div>0xff700000/0xff300000 FWH decode disabled</div><div>0xff600000/0xff200000 FWH decode disabled</div><div>0xff500000/0xff100000 FWH decode disabled</div><div>0xff400000/0xff000000 FWH decode disabled</div><div>Maximum FWH chip size: 0x100000 bytes</div>
<div>BIOS_CNTL = 0x09: BIOS Lock Enable: disabled, BIOS Write Enable: enabled</div><div>Root Complex Register Block address = 0xfed1c000</div><div>GCS = 0xc20: BIOS Interface Lock-Down: disabled, Boot BIOS Straps: 0x3 (SPI)</div>
<div>Top Swap : not enabled</div><div>SPIBAR = 0xfed1c000 + 0x3800</div><div>0x04: 0x6008 (HSFS)</div><div>HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=1, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=0</div><div>Programming OPCODES... </div>
<div>program_opcodes: preop=5006 optype=463b opmenu=05d80302c79f0190</div><div>done</div><div> OP Type Pre-OP</div><div>op[0]: 0x02, write w/ addr, none</div><div>op[1]: 0x03, read w/ addr, none</div>
<div>op[2]: 0xd8, write w/ addr, none</div><div>op[3]: 0x05, read w/o addr, none</div><div>op[4]: 0x90, read w/ addr, none</div><div>op[5]: 0x01, write w/o addr, none</div><div>op[6]: 0x9f, read w/o addr, none</div><div>
op[7]: 0xc7, write w/o addr, none</div><div>Pre-OP 0: 0x06, Pre-OP 1: 0x50</div><div>0x06: 0x0000 (HSFC)</div><div>HSFC: FGO=0, FCYCLE=0, FDBC=0, SME=0</div><div>0x08: 0x007fffc0 (FADDR)</div><div>0x50: 0x0000ffff (FRAP)</div>
<div>BMWAG 0x00, BMRAG 0x00, BRWA 0xff, BRRA 0xff</div><div>0x54: 0x000f0000 FREG0: Flash Descriptor region (0x00000000-0x0000ffff) is read-write.</div><div>0x58: 0x07ff0400 FREG1: BIOS region (0x00400000-0x007fffff) is read-write.</div>
<div>0x5C: 0x03ff0010 FREG2: Management Engine region (0x00010000-0x003fffff) is read-write.</div><div>0x60: 0x00001fff FREG3: Gigabit Ethernet region is unused.</div><div>0x64: 0x00001fff FREG4: Platform Data region is unused.</div>
<div>0x74: 0x00000000 (PR0 is unused)</div><div>0x78: 0x00000000 (PR1 is unused)</div><div>0x7C: 0x00000000 (PR2 is unused)</div><div>0x80: 0x00000000 (PR3 is unused)</div><div>0x84: 0x00000000 (PR4 is unused)</div><div>0x90: 0x84 (SSFS)</div>
<div>SSFS: SCIP=0, FDONE=1, FCERR=0, AEL=0</div><div>0x91: 0xf87f10 (SSFC)</div><div>SSFC: SCGO=0, ACS=0, SPOP=0, COP=1, DBC=63, SME=0, SCF=0</div><div>0x94: 0x5006 (PREOP)</div><div>0x96: 0x463b (OPTYPE)</div><div>
0x98: 0x05d80302 (OPMENU)</div><div>0x9C: 0xc79f0190 (OPMENU+4)</div><div>0xA0: 0x00000000 (BBAR)</div><div>0xC4: 0x00002005 (LVSCC)</div><div>LVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=0</div><div>0xC8: 0x00002005 (UVSCC)</div>
<div>UVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=0</div><div>0xD0: 0x00000000 (FPB)</div><div><br></div><div>Reading flash descriptors mapped by the chipset via FDOC/FDOD... done.</div><div>=== Content Section ===</div>
<div>FLVALSIG 0x0ff0a55a</div><div>FLMAP0 0x02040003</div><div>FLMAP1 0x12100206</div><div>FLMAP2 0x00210020</div><div><br></div><div>--- Details ---</div><div>NR (Number of Regions): 3</div>
<div>FRBA (Flash Region Base Address): 0x040</div><div>NC (Number of Components): 1</div><div>FCBA (Flash Component Base Address): 0x030</div><div>ISL (ICH/PCH Strap Length): 18</div>
<div>FISBA/FPSBA (Flash ICH/PCH Strap Base Address): 0x100</div><div>NM (Number of Masters): 3</div><div>FMBA (Flash Master Base Address): 0x060</div><div>MSL/PSL (MCH/PROC Strap Length): 0</div>
<div>FMSBA (Flash MCH/PROC Strap Base Address): 0x200</div><div><br></div><div>=== Component Section ===</div><div>FLCOMP 0x00100024</div><div>FLILL 0x00000000</div><div><br></div><div>--- Details ---</div><div>
Component 1 density: 8 MB</div><div>Component 2 is not used.</div><div>Read Clock Frequency: 20 MHz</div><div>Read ID and Status Clock Freq.: 20 MHz</div><div>Write and Erase Clock Freq.: 20 MHz</div>
<div>Fast Read is supported.</div><div>Fast Read Clock Frequency: 20 MHz</div><div>No forbidden opcodes.</div><div><br></div><div>=== Region Section ===</div><div>FLREG0 0x000f0000</div><div>FLREG1 0x07ff0400</div>
<div>FLREG2 0x03ff0010</div><div>FLREG3 0x00001fff</div><div><br></div><div>--- Details ---</div><div>Region 0 (Descr.) 0x00000000 - 0x0000ffff</div><div>Region 1 (BIOS ) 0x00400000 - 0x007fffff</div><div>Region 2 (ME ) 0x00010000 - 0x003fffff</div>
<div>Region 3 (GbE ) is unused.</div><div><br></div><div>=== Master Section ===</div><div>FLMSTR1 0xffff0000</div><div>FLMSTR2 0xffff0000</div><div>FLMSTR3 0xffff0118</div><div><br></div><div>--- Details ---</div><div>
Descr. BIOS ME GbE Platf.</div><div>BIOS rw rw rw rw rw</div><div>ME rw rw rw rw rw</div><div>GbE rw rw rw rw rw</div><div><br></div><div>SPI Read Configuration: prefetching enabled, caching enabled, OK.</div>
<div>The following protocols are supported: FWH, SPI.</div><div>Probing for Winbond W25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017</div><div>Found Winbond flash chip "W25Q64" (8192 kB, SPI) at physical address 0xff800000.</div>
<div>Chip status register is 0x00.</div><div>This chip may contain one-time programmable memory. flashrom cannot read</div><div>and may never be able to write it, hence it may not be able to completely</div><div>clone the contents of this chip (see man page for details).</div>
<div>Block protection is disabled.</div><div>Reading flash... done.</div><div>Restoring MMIO space at 0x7f6ced1e68a0</div><div>Restoring MMIO space at 0x7f6ced1e689c</div><div>Restoring MMIO space at 0x7f6ced1e6898</div><div>
Restoring MMIO space at 0x7f6ced1e6896</div><div>Restoring MMIO space at 0x7f6ced1e6894</div><div>Restoring PCI config space for 00:1f:0 reg 0xdc</div></div><div><br></div><div><br></div><div><br></div>-- <br>Ross Amans<br>
Systems Engineer<br>Newisys div of Sanmina<br>5385 Mark Dabling blvd<br>Colorado Springs, CO 80918<br>719-884-8714 (work)<br>719-287-4446 (cell)<br>
</div>
<pre>CONFIDENTIALITY
This e-mail message and any attachments thereto, is intended only for use by the addressee(s) named herein and may contain legally privileged and/or confidential information. If you are not the intended recipient of this e-mail message, you are hereby notified that any dissemination, distribution or copying of this e-mail message, and any attachments thereto, is strictly prohibited. If you have received this e-mail message in error, please immediately notify the sender and permanently delete the original and any copies of this email and any prints thereof.
ABSENT AN EXPRESS STATEMENT TO THE CONTRARY HEREINABOVE, THIS E-MAIL IS NOT INTENDED AS A SUBSTITUTE FOR A WRITING. Notwithstanding the Uniform Electronic Transactions Act or the applicability of any other law of similar substance and effect, absent an express statement to the contrary hereinabove, this e-mail message its contents, and any attachments hereto are not intended to represent an offer or acceptance to enter into a contract and are not otherwise intended to bind the sender, Sanmina Corporation (or any of its subsidiaries), or any other person or entity.