<div dir="ltr"><div><div><div><div><div><div><div><div><div><div></div><div>Before I get started on the review, just a general comment or two.<br></div><div>If you plan to contribute in the future (which I certainly hope you will), please break submissions down into blocks of 5-10 chips. This makes it so much easier for me, and any other reviewers, to quickly check the patch and provide feedback in a timely manner.<br>
</div><div><br>In the last review, I mentioned the Numonyx M45PE series (10, 20, 40, 80, 16), should only have <br>+ .feature_bits = FEATURE_WRSR_WREN, </div>
<div>set when the command is there. It appears I may have been unclear there, because instead of removing just the WREN flag, you removed the whole line (the chips do have a Write Status Register- WRSR).<br><br></div><div>
<br>Continuing the review from Numonyx M45PE16.<br><br></div>Numonyx M25PX80-<br>+ .voltage = {2700, 3600},<br></div>The datasheets I've seen have it as 2.3-3.6V (rev 4 Dec 2008 and Rev B 3/2013)<br>
<br></div><div>+ .tested = TEST_OK_PREW,<br></div>Unless
I'm reading it wrong, it looks like you're adding this chip as a fully
tested one- would you mind supplying some logs showing that it
successfully does these operations? (write logs shouldn't contain all :S
(for skipped blocks) next to the addresses).<br><br></div>Numonyx N25Q00AA13-<br></div>I'll admit I don't really know how this chip works, but it seems there should be a 3rd eraseblock from the description of the memory organization (datasheet is Rev E, 2/12):<br>
<br>Memory Configuration and Block Diagram<br>The memory is a stacked device comprised of four 256Mb chips. Each chip is internally<br>partitioned into two 128Mb segments. Each page of memory can be individually pro-<br>
grammed. Bits are programmed from one through zero. The device is subsector, sector,<br>
or single 256Mb chip erasable, but not page-erasable. Bits are erased from zero through<br>one. The memory is configured as 134,217,728 bytes (8 bits each); 2048 sectors (64KB<br>each); 32,768 subsectors (4KB each); and 524,288 pages (256 bytes each); and 64 OTP<br>
bytes are located outside the main memory array. <br><br></div>You've got:<br>+ .eraseblocks = { {4 * 1024, 32768 } },<br>+ .block_erase = spi_block_erase_20,<br>+ }, {<br>+ .eraseblocks = { {64 * 1024, 2048 } },<br>
+ .block_erase = spi_block_erase_d8,<br><br></div>There's a die erase opcode, which I am unfamiliar with- maybe it handles erasing a single 256Mb chip at a time?<br><br></div>Sanyo LF25FW203A / LE25FW203A-<br>
</div>Thanks so much for getting to the bottom of this chip, and figuring out which chip it actually is.<br><br> .probe = probe_spi_rdid,<br></div><div>Maybe I'm reading the patch wrong, but you appear to be missing the .probe_timing line for this chip.<br>
<br>LE25FW418A, LE25FW808 and LE25FW806 -<br></div><div><div><div><div><div>For the LE25FW806A you included the small sector erase, but left it out for the rest of the chips- any particular reason for this?<br><br></div>
<div><br>I'll cover from Spansion S25FL128S to the end tomorrow.<br></div></div></div></div></div></div><div class="gmail_extra"><br><br><div class="gmail_quote">On Tue, May 21, 2013 at 4:29 AM, Николай Николаев <span dir="ltr"><<a href="mailto:evrinoma@gmail.com" target="_blank">evrinoma@gmail.com</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">A new version patch<br clear="all"><div><br></div><div> Was checked:<br> -functions block erase for all chips<br>
-feature bits for all chips<br> -model_id for all chips<br> -manufacture_id for all chips<br>
-voltage for all chips<br></div><div class="im"><div><br></div>-- <br><div>With best regards Nikolay Nikolaev</div></div><div>С Уважением Николаев Николай</div>
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