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<div class="moz-cite-prefix">Le 26/01/2015 12:52, Pierre-O a écrit :<br>
</div>
<blockquote cite="mid:54C62A7D.9030609@taveo.com" type="cite">
<br>
Le 23/01/2015 19:10, Stefan Tauner a écrit :
<br>
<blockquote type="cite">On Fri, 23 Jan 2015 18:03:10 +0100
<br>
Pierre-O <a class="moz-txt-link-rfc2396E" href="mailto:por@taveo.com"><por@taveo.com></a> wrote:
<br>
<br>
<blockquote type="cite">0x54: 0x01ff0000 FREG0: Flash Descriptor
region (0x00000000-0x001fffff)
<br>
is read-write.
<br>
0x58: 0x07ff0200 FREG1: BIOS region (0x00200000-0x007fffff) is
read-write.
<br>
[…]
<br>
Running OPCODE 0x03 failed at address 0x800000 (payload length
was 64).
<br>
Read operation failed!
<br>
</blockquote>
That's because 0x800000 is not covered by any region... the
chipset
<br>
locks everything not covered automatically.
<br>
<br>
</blockquote>
<br>
Thanks for your help, just missed the 0x800000 address.
<br>
Does it mean my 128Mbits flash is showed like a 64Mbits by
controller due to BIOS given information ?
<br>
My BIOS fits 64Mbits anyway, can I tell flashrom to read found
regions only ?
<br>
<br>
Best regards,
<br>
<br>
</blockquote>
<br>
By the way, when trying to write (passing valid regions via a layout
file),<br>
rom / bios sizes difference seems to be a problem too :<br>
<br>
<b><small>flashrom v0.9.7-r1869 on Linux 3.13.0-24-generic (x86_64)<br>
flashrom is free software, get the source code at
<a class="moz-txt-link-freetext" href="http://www.flashrom.org">http://www.flashrom.org</a><br>
<br>
flashrom was built with libpci 3.2.1, GCC 4.8.2, little endian<br>
Command line (9 args): flashrom -V -p internal -c N25Q128..3E -w
LFFF-verbose.bin -l LFFF.layout<br>
romlayout 00000000 - 001fffff named desc<br>
romlayout 00200000 - 007fffff named bios<br>
Calibrating delay loop... OS timer resolution is 1 usecs, 863M
loops per second, 10 myus = 10 us, 100 myus = 104 us, 1000 myus
= 1023 us, 10000 myus = 10017 us, 4 myus = 4 us, OK.<br>
Initializing internal programmer<br>
No coreboot table found.<br>
Using Internal DMI decoder.<br>
DMI string chassis-type: "Desktop"<br>
DMI string system-manufacturer: "Insyde"<br>
DMI string system-product-name: "MohonPeak"<br>
DMI string system-version: "TBD by OEM"<br>
DMI string baseboard-manufacturer: "Type2 - Board Vendor Name1"<br>
DMI string baseboard-product-name: "Type2 - Board Product Name1"<br>
DMI string baseboard-version: "Type2 - Board Version"<br>
Found chipset "Intel Avoton/Rangeley" with PCI ID 8086:1f38.<br>
This chipset is marked as untested. If you are using an
up-to-date version<br>
of flashrom *and* were (not) able to successfully update your
firmware with it,<br>
then please email a report to <a class="moz-txt-link-abbreviated" href="mailto:flashrom@flashrom.org">flashrom@flashrom.org</a> including a
verbose (-V) log.<br>
Thank you!<br>
Enabling flash write... Root Complex Register Block address =
0xfed1c000<br>
GCS = 0x40000c01: BIOS Interface Lock-Down: enabled, Boot BIOS
Straps: 0x3 (SPI)<br>
Top Swap: not enabled<br>
0xfff80000/0xffb80000 FWH IDSEL: 0x0<br>
0xfff00000/0xffb00000 FWH IDSEL: 0x0<br>
0xffe80000/0xffa80000 FWH IDSEL: 0x1<br>
0xffe00000/0xffa00000 FWH IDSEL: 0x1<br>
0xffd80000/0xff980000 FWH IDSEL: 0x2<br>
0xffd00000/0xff900000 FWH IDSEL: 0x2<br>
0xffc80000/0xff880000 FWH IDSEL: 0x3<br>
0xffc00000/0xff800000 FWH IDSEL: 0x3<br>
0xfff80000/0xffb80000 FWH decode enabled<br>
0xfff00000/0xffb00000 FWH decode enabled<br>
0xffe80000/0xffa80000 FWH decode enabled<br>
0xffe00000/0xffa00000 FWH decode enabled<br>
0xffd80000/0xff980000 FWH decode enabled<br>
0xffd00000/0xff900000 FWH decode enabled<br>
0xffc80000/0xff880000 FWH decode enabled<br>
0xffc00000/0xff800000 FWH decode enabled<br>
0xff700000/0xff300000 FWH decode enabled<br>
0xff600000/0xff200000 FWH decode enabled<br>
0xff500000/0xff100000 FWH decode enabled<br>
0xff400000/0xff000000 FWH decode enabled<br>
Maximum FWH chip size: 0x100000 bytes<br>
SPI_BASE_ADDRESS = 0xfed01000<br>
SPI Read Configuration: prefetching disabled, caching enabled,<br>
BIOS_CNTL = 0x01: BIOS Lock Enable: disabled, BIOS Write Enable:
enabled<br>
0x04: 0x6018 (HSFS)<br>
HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=3, SCIP=0, FDOPSS=1,
FDV=1, FLOCKDN=0<br>
Programming OPCODES... done<br>
0x06: 0x0004 (HSFC)<br>
HSFC: FGO=0, FCYCLE=2, FDBC=0, SME=0<br>
0x50: 0x0000ffff (FRAP)<br>
BMWAG 0x00, BMRAG 0x00, BRWA 0xff, BRRA 0xff<br>
0x54: 0x01ff0000 FREG0: Flash Descriptor region
(0x00000000-0x001fffff) is read-write.<br>
0x58: 0x07ff0200 FREG1: BIOS region (0x00200000-0x007fffff) is
read-write.<br>
0x90: 0x84 (SSFS)<br>
SSFS: SCIP=0, FDONE=1, FCERR=0, AEL=0<br>
0x91: 0xf80000 (SSFC)<br>
SSFC: SCGO=0, ACS=0, SPOP=0, COP=0, DBC=0, SME=0, SCF=0<br>
0x94: 0x5006 (PREOP)<br>
0x96: 0x463b (OPTYPE)<br>
0x98: 0x05d80302 (OPMENU)<br>
0x9C: 0xc79f0190 (OPMENU+4)<br>
0xC4: 0x0080d807 (LVSCC)<br>
LVSCC: BES=0x3, WG=1, WSR=0, WEWS=0, EO=0xd8, VCL=1<br>
0xC8: 0x0000d807 (UVSCC)<br>
UVSCC: BES=0x3, WG=1, WSR=0, WEWS=0, EO=0xd8<br>
0xD0: 0x00000000 (FPB)<br>
OK.<br>
The following protocols are supported: FWH, SPI.<br>
Probing for Micron/Numonyx/ST N25Q128..3E, 16384 kB:
probe_spi_rdid_generic: id1 0x20, id2 0xba18<br>
Found Micron/Numonyx/ST flash chip "N25Q128..3E" (16384 kB, SPI)
mapped at physical address 0x00000000ff000000.<br>
Chip status register is 0x02.<br>
Chip status register: Status Register Write Disable (SRWD, SRP,
...) is not set<br>
Chip status register: Block Protect 3 (BP3) is not set<br>
Chip status register: Top/Bottom (TB) is top<br>
Chip status register: Block Protect 2 (BP2) is not set<br>
Chip status register: Block Protect 1 (BP1) is not set<br>
Chip status register: Block Protect 0 (BP0) is not set<br>
Chip status register: Write Enable Latch (WEL) is set<br>
Chip status register: Write In Progress (WIP/BUSY) is not set<br>
This chip may contain one-time programmable memory. flashrom
cannot read<br>
and may never be able to write it, hence it may not be able to
completely<br>
clone the contents of this chip (see man page for details).<br>
Error: Image size (8388608 B) doesn't match the flash chip's
size (16777216 B)!<br>
Restoring MMIO space at 0x7f53cdfb309c<br>
Restoring MMIO space at 0x7f53cdfb3098<br>
Restoring MMIO space at 0x7f53cdfb3096<br>
Restoring MMIO space at 0x7f53cdfb3094<br>
Restoring MMIO space at 0x7f53cdfb30fc</small></b><br>
<br>
Any option / work around for this ?<br>
<br>
Best regards,<br>
<br>
<pre class="moz-signature" cols="72">--
Pierre-Olivier Roumier
TAVEO Engineering
</pre>
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