| 1 | /* |
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| 2 | * This file is part of the flashrom project. |
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| 3 | * |
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| 4 | * Copyright (C) 2007, 2008 Carl-Daniel Hailfinger |
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| 5 | * |
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| 6 | * This program is free software; you can redistribute it and/or modify |
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| 7 | * it under the terms of the GNU General Public License as published by |
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| 8 | * the Free Software Foundation; version 2 of the License. |
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| 9 | * |
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| 10 | * This program is distributed in the hope that it will be useful, |
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| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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| 13 | * GNU General Public License for more details. |
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| 14 | * |
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| 15 | * You should have received a copy of the GNU General Public License |
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| 16 | * along with this program; if not, write to the Free Software |
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| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
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| 18 | */ |
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| 19 | |
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| 20 | #ifndef __SPI_H__ |
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| 21 | #define __SPI_H__ 1 |
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| 22 | |
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| 23 | /* |
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| 24 | * Contains the generic SPI headers |
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| 25 | */ |
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| 26 | |
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| 27 | /* Read Electronic ID */ |
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| 28 | #define JEDEC_RDID 0x9f |
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| 29 | #define JEDEC_RDID_OUTSIZE 0x01 |
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| 30 | /* INSIZE may be 0x04 for some chips*/ |
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| 31 | #define JEDEC_RDID_INSIZE 0x03 |
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| 32 | |
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| 33 | /* AT25F512A has bit 3 as don't care bit in commands */ |
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| 34 | #define AT25F512A_RDID 0x15 /* 0x15 or 0x1d */ |
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| 35 | #define AT25F512A_RDID_OUTSIZE 0x01 |
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| 36 | #define AT25F512A_RDID_INSIZE 0x02 |
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| 37 | |
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| 38 | /* Read Electronic Manufacturer Signature */ |
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| 39 | #define JEDEC_REMS 0x90 |
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| 40 | #define JEDEC_REMS_OUTSIZE 0x04 |
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| 41 | #define JEDEC_REMS_INSIZE 0x02 |
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| 42 | |
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| 43 | /* Read Serial Flash Discoverable Parameters (SFDP) */ |
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| 44 | #define JEDEC_SFDP 0x5a |
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| 45 | #define JEDEC_SFDP_OUTSIZE 0x05 /* 8b op, 24b addr, 8b dummy */ |
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| 46 | /* JEDEC_SFDP_INSIZE : any length */ |
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| 47 | |
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| 48 | /* Read Electronic Signature */ |
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| 49 | #define JEDEC_RES 0xab |
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| 50 | #define JEDEC_RES_OUTSIZE 0x04 |
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| 51 | /* INSIZE may be 0x02 for some chips*/ |
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| 52 | #define JEDEC_RES_INSIZE 0x01 |
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| 53 | |
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| 54 | /* Write Enable */ |
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| 55 | #define JEDEC_WREN 0x06 |
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| 56 | #define JEDEC_WREN_OUTSIZE 0x01 |
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| 57 | #define JEDEC_WREN_INSIZE 0x00 |
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| 58 | |
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| 59 | /* Write Disable */ |
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| 60 | #define JEDEC_WRDI 0x04 |
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| 61 | #define JEDEC_WRDI_OUTSIZE 0x01 |
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| 62 | #define JEDEC_WRDI_INSIZE 0x00 |
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| 63 | |
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| 64 | /* Chip Erase 0x60 is supported by Macronix/SST chips. */ |
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| 65 | #define JEDEC_CE_60 0x60 |
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| 66 | #define JEDEC_CE_60_OUTSIZE 0x01 |
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| 67 | #define JEDEC_CE_60_INSIZE 0x00 |
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| 68 | |
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| 69 | /* Chip Erase 0xc7 is supported by SST/ST/EON/Macronix chips. */ |
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| 70 | #define JEDEC_CE_C7 0xc7 |
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| 71 | #define JEDEC_CE_C7_OUTSIZE 0x01 |
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| 72 | #define JEDEC_CE_C7_INSIZE 0x00 |
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| 73 | |
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| 74 | /* Block Erase 0x52 is supported by SST and old Atmel chips. */ |
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| 75 | #define JEDEC_BE_52 0x52 |
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| 76 | #define JEDEC_BE_52_OUTSIZE 0x04 |
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| 77 | #define JEDEC_BE_52_INSIZE 0x00 |
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| 78 | |
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| 79 | /* Block Erase 0xd8 is supported by EON/Macronix chips. */ |
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| 80 | #define JEDEC_BE_D8 0xd8 |
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| 81 | #define JEDEC_BE_D8_OUTSIZE 0x04 |
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| 82 | #define JEDEC_BE_D8_INSIZE 0x00 |
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| 83 | |
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| 84 | /* Block Erase 0xd7 is supported by PMC chips. */ |
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| 85 | #define JEDEC_BE_D7 0xd7 |
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| 86 | #define JEDEC_BE_D7_OUTSIZE 0x04 |
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| 87 | #define JEDEC_BE_D7_INSIZE 0x00 |
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| 88 | |
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| 89 | /* Sector Erase 0x20 is supported by Macronix/SST chips. */ |
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| 90 | #define JEDEC_SE 0x20 |
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| 91 | #define JEDEC_SE_OUTSIZE 0x04 |
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| 92 | #define JEDEC_SE_INSIZE 0x00 |
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| 93 | |
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| 94 | /* Read Status Register */ |
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| 95 | #define JEDEC_RDSR 0x05 |
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| 96 | #define JEDEC_RDSR_OUTSIZE 0x01 |
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| 97 | #define JEDEC_RDSR_INSIZE 0x01 |
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| 98 | |
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| 99 | /* Status Register Bits */ |
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| 100 | #define SPI_SR_WIP (0x01 << 0) |
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| 101 | #define SPI_SR_WEL (0x01 << 1) |
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| 102 | #define SPI_SR_AAI (0x01 << 6) |
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| 103 | |
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| 104 | /* Write Status Enable */ |
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| 105 | #define JEDEC_EWSR 0x50 |
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| 106 | #define JEDEC_EWSR_OUTSIZE 0x01 |
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| 107 | #define JEDEC_EWSR_INSIZE 0x00 |
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| 108 | |
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| 109 | /* Write Status Register */ |
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| 110 | #define JEDEC_WRSR 0x01 |
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| 111 | #define JEDEC_WRSR_OUTSIZE 0x02 |
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| 112 | #define JEDEC_WRSR_INSIZE 0x00 |
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| 113 | |
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| 114 | /* Read the memory */ |
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| 115 | #define JEDEC_READ 0x03 |
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| 116 | #define JEDEC_READ_OUTSIZE 0x04 |
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| 117 | /* JEDEC_READ_INSIZE : any length */ |
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| 118 | |
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| 119 | /* Write memory byte */ |
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| 120 | #define JEDEC_BYTE_PROGRAM 0x02 |
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| 121 | #define JEDEC_BYTE_PROGRAM_OUTSIZE 0x05 |
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| 122 | #define JEDEC_BYTE_PROGRAM_INSIZE 0x00 |
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| 123 | |
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| 124 | /* Write AAI word (SST25VF080B) */ |
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| 125 | #define JEDEC_AAI_WORD_PROGRAM 0xad |
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| 126 | #define JEDEC_AAI_WORD_PROGRAM_OUTSIZE 0x06 |
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| 127 | #define JEDEC_AAI_WORD_PROGRAM_CONT_OUTSIZE 0x03 |
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| 128 | #define JEDEC_AAI_WORD_PROGRAM_INSIZE 0x00 |
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| 129 | |
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| 130 | /* Error codes */ |
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| 131 | #define SPI_GENERIC_ERROR -1 |
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| 132 | #define SPI_INVALID_OPCODE -2 |
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| 133 | #define SPI_INVALID_ADDRESS -3 |
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| 134 | #define SPI_INVALID_LENGTH -4 |
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| 135 | #define SPI_FLASHROM_BUG -5 |
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| 136 | #define SPI_PROGRAMMER_ERROR -6 |
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| 137 | |
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| 138 | #endif /* !__SPI_H__ */ |
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