Changeset 1112
- Timestamp:
- 07/28/10 00:41:39 (19 months ago)
- Location:
- trunk
- Files:
-
- 34 edited
- 1 copied
-
atahpt.c (modified) (1 diff)
-
bitbang_spi.c (modified) (1 diff)
-
board_enable.c (modified) (1 diff)
-
buspirate_spi.c (modified) (1 diff)
-
cbtable.c (modified) (1 diff)
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chipset_enable.c (modified) (1 diff)
-
cli_classic.c (modified) (1 diff)
-
dediprog.c (modified) (1 diff)
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dmi.c (modified) (1 diff)
-
drkaiser.c (modified) (1 diff)
-
dummyflasher.c (modified) (1 diff)
-
flash.h (modified) (8 diffs)
-
flashrom.c (modified) (1 diff)
-
ft2232_spi.c (modified) (1 diff)
-
gfxnvidia.c (modified) (1 diff)
-
ichspi.c (modified) (1 diff)
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internal.c (modified) (1 diff)
-
it87spi.c (modified) (1 diff)
-
layout.c (modified) (1 diff)
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nic3com.c (modified) (1 diff)
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nicnatsemi.c (modified) (1 diff)
-
nicrealtek.c (modified) (1 diff)
-
pcidev.c (modified) (1 diff)
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print.c (modified) (1 diff)
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print_wiki.c (modified) (1 diff)
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processor_enable.c (modified) (1 diff)
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programmer.h (copied) (copied from trunk/flash.h) (11 diffs)
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rayer_spi.c (modified) (1 diff)
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satasii.c (modified) (1 diff)
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sb600spi.c (modified) (1 diff)
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serial.c (modified) (2 diffs)
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serprog.c (modified) (2 diffs)
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spi.c (modified) (1 diff)
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spi25.c (modified) (1 diff)
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wbsio_spi.c (modified) (1 diff)
Legend:
- Unmodified
- Added
- Removed
-
trunk/atahpt.c
r1070 r1112 23 23 #include <sys/types.h> 24 24 #include "flash.h" 25 #include "programmer.h" 25 26 26 27 #define BIOS_ROM_ADDR 0x90 -
trunk/bitbang_spi.c
r1092 r1112 25 25 #include "flash.h" 26 26 #include "chipdrivers.h" 27 #include "programmer.h" 27 28 #include "spi.h" 28 29 -
trunk/board_enable.c
r1109 r1112 27 27 #include <string.h> 28 28 #include "flash.h" 29 #include "programmer.h" 29 30 30 31 #if defined(__i386__) || defined(__x86_64__) -
trunk/buspirate_spi.c
r1082 r1112 25 25 #include "flash.h" 26 26 #include "chipdrivers.h" 27 #include "programmer.h" 27 28 #include "spi.h" 28 29 -
trunk/cbtable.c
r1021 r1112 29 29 #include <string.h> 30 30 #include "flash.h" 31 #include "programmer.h" 31 32 #include "coreboot_tables.h" 32 33 -
trunk/chipset_enable.c
r1111 r1112 33 33 #include <unistd.h> 34 34 #include "flash.h" 35 #include "programmer.h" 35 36 36 37 #define NOT_DONE_YET 1 -
trunk/cli_classic.c
r1079 r1112 31 31 #include "flash.h" 32 32 #include "flashchips.h" 33 #include "programmer.h" 33 34 34 35 static void cli_classic_usage(const char *name) -
trunk/dediprog.c
r1068 r1112 22 22 #include "flash.h" 23 23 #include "chipdrivers.h" 24 #include "programmer.h" 24 25 #include "spi.h" 25 26 -
trunk/dmi.c
r1068 r1112 24 24 25 25 #include "flash.h" 26 #include "programmer.h" 26 27 27 28 int has_dmi_support = 0; -
trunk/drkaiser.c
r1111 r1112 21 21 #include <stdlib.h> 22 22 #include "flash.h" 23 #include "programmer.h" 23 24 24 25 #define PCI_VENDOR_ID_DRKAISER 0x1803 -
trunk/dummyflasher.c
r1082 r1112 25 25 #include "flash.h" 26 26 #include "chipdrivers.h" 27 #include "programmer.h" 27 28 28 29 static void tolower_string(char *str) -
trunk/flash.h
r1111 r1112 36 36 typedef unsigned long chipaddr; 37 37 38 enum programmer {39 #if CONFIG_INTERNAL == 140 PROGRAMMER_INTERNAL,41 #endif42 #if CONFIG_DUMMY == 143 PROGRAMMER_DUMMY,44 #endif45 #if CONFIG_NIC3COM == 146 PROGRAMMER_NIC3COM,47 #endif48 #if CONFIG_NICREALTEK == 149 PROGRAMMER_NICREALTEK,50 PROGRAMMER_NICREALTEK2,51 #endif52 #if CONFIG_NICNATSEMI == 153 PROGRAMMER_NICNATSEMI,54 #endif55 #if CONFIG_GFXNVIDIA == 156 PROGRAMMER_GFXNVIDIA,57 #endif58 #if CONFIG_DRKAISER == 159 PROGRAMMER_DRKAISER,60 #endif61 #if CONFIG_SATASII == 162 PROGRAMMER_SATASII,63 #endif64 #if CONFIG_ATAHPT == 165 PROGRAMMER_ATAHPT,66 #endif67 #if CONFIG_INTERNAL == 168 #if defined(__i386__) || defined(__x86_64__)69 PROGRAMMER_IT87SPI,70 #endif71 #endif72 #if CONFIG_FT2232_SPI == 173 PROGRAMMER_FT2232_SPI,74 #endif75 #if CONFIG_SERPROG == 176 PROGRAMMER_SERPROG,77 #endif78 #if CONFIG_BUSPIRATE_SPI == 179 PROGRAMMER_BUSPIRATE_SPI,80 #endif81 #if CONFIG_DEDIPROG == 182 PROGRAMMER_DEDIPROG,83 #endif84 #if CONFIG_RAYER_SPI == 185 PROGRAMMER_RAYER_SPI,86 #endif87 PROGRAMMER_INVALID /* This must always be the last entry. */88 };89 90 extern enum programmer programmer;91 92 struct programmer_entry {93 const char *vendor;94 const char *name;95 96 int (*init) (void);97 int (*shutdown) (void);98 99 void * (*map_flash_region) (const char *descr, unsigned long phys_addr,100 size_t len);101 void (*unmap_flash_region) (void *virt_addr, size_t len);102 103 void (*chip_writeb) (uint8_t val, chipaddr addr);104 void (*chip_writew) (uint16_t val, chipaddr addr);105 void (*chip_writel) (uint32_t val, chipaddr addr);106 void (*chip_writen) (uint8_t *buf, chipaddr addr, size_t len);107 uint8_t (*chip_readb) (const chipaddr addr);108 uint16_t (*chip_readw) (const chipaddr addr);109 uint32_t (*chip_readl) (const chipaddr addr);110 void (*chip_readn) (uint8_t *buf, const chipaddr addr, size_t len);111 void (*delay) (int usecs);112 };113 114 extern const struct programmer_entry programmer_table[];115 116 38 int register_shutdown(void (*function) (void *data), void *data); 117 118 int programmer_init(char *param);119 int programmer_shutdown(void);120 39 void *programmer_map_flash_region(const char *descr, unsigned long phys_addr, 121 40 size_t len); … … 131 50 void programmer_delay(int usecs); 132 51 133 enum bitbang_spi_master_type {134 BITBANG_SPI_INVALID = 0, /* This must always be the first entry. */135 #if CONFIG_RAYER_SPI == 1136 BITBANG_SPI_MASTER_RAYER,137 #endif138 };139 140 struct bitbang_spi_master {141 enum bitbang_spi_master_type type;142 143 /* Note that CS# is active low, so val=0 means the chip is active. */144 void (*set_cs) (int val);145 void (*set_sck) (int val);146 void (*set_mosi) (int val);147 int (*get_miso) (void);148 };149 150 52 #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) 151 53 … … 264 166 extern struct flashchip flashchips[]; 265 167 266 #if CONFIG_INTERNAL == 1267 struct penable {268 uint16_t vendor_id;269 uint16_t device_id;270 int status;271 const char *vendor_name;272 const char *device_name;273 int (*doit) (struct pci_dev *dev, const char *name);274 };275 276 extern const struct penable chipset_enables[];277 278 struct board_pciid_enable {279 /* Any device, but make it sensible, like the ISA bridge. */280 uint16_t first_vendor;281 uint16_t first_device;282 uint16_t first_card_vendor;283 uint16_t first_card_device;284 285 /* Any device, but make it sensible, like286 * the host bridge. May be NULL.287 */288 uint16_t second_vendor;289 uint16_t second_device;290 uint16_t second_card_vendor;291 uint16_t second_card_device;292 293 /* Pattern to match DMI entries */294 const char *dmi_pattern;295 296 /* The vendor / part name from the coreboot table. */297 const char *lb_vendor;298 const char *lb_part;299 300 const char *vendor_name;301 const char *board_name;302 303 int max_rom_decode_parallel;304 int status;305 int (*enable) (void);306 };307 308 extern const struct board_pciid_enable board_pciid_enables[];309 310 struct board_info {311 const char *vendor;312 const char *name;313 const int working;314 #ifdef CONFIG_PRINT_WIKI315 const char *url;316 const char *note;317 #endif318 };319 320 extern const struct board_info boards_known[];321 extern const struct board_info laptops_known[];322 323 #endif324 325 /* udelay.c */326 void myusec_delay(int usecs);327 void myusec_calibrate_delay(void);328 void internal_delay(int usecs);329 330 #if NEED_PCI == 1331 /* pcidev.c */332 333 extern uint32_t io_base_addr;334 extern struct pci_access *pacc;335 extern struct pci_dev *pcidev_dev;336 struct pcidev_status {337 uint16_t vendor_id;338 uint16_t device_id;339 int status;340 const char *vendor_name;341 const char *device_name;342 };343 uint32_t pcidev_validate(struct pci_dev *dev, uint32_t bar, const struct pcidev_status *devs);344 uint32_t pcidev_init(uint16_t vendor_id, uint32_t bar, const struct pcidev_status *devs);345 #endif346 347 168 /* print.c */ 348 169 char *flashbuses_to_text(enum chipbustype bustype); 349 170 void print_supported(void); 350 #if CONFIG_NIC3COM+CONFIG_NICREALTEK+CONFIG_NICNATSEMI+CONFIG_GFXNVIDIA+CONFIG_DRKAISER+CONFIG_SATASII+CONFIG_ATAHPT >= 1351 void print_supported_pcidevs(const struct pcidev_status *devs);352 #endif353 171 void print_supported_wiki(void); 354 355 /* board_enable.c */356 void w836xx_ext_enter(uint16_t port);357 void w836xx_ext_leave(uint16_t port);358 int it8705f_write_enable(uint8_t port);359 uint8_t sio_read(uint16_t port, uint8_t reg);360 void sio_write(uint16_t port, uint8_t reg, uint8_t data);361 void sio_mask(uint16_t port, uint8_t reg, uint8_t data, uint8_t mask);362 int board_flash_enable(const char *vendor, const char *part);363 364 /* chipset_enable.c */365 int chipset_flash_enable(void);366 367 /* processor_enable.c */368 int processor_flash_enable(void);369 370 /* physmap.c */371 void *physmap(const char *descr, unsigned long phys_addr, size_t len);372 void *physmap_try_ro(const char *descr, unsigned long phys_addr, size_t len);373 void physunmap(void *virt_addr, size_t len);374 int setup_cpu_msr(int cpu);375 void cleanup_cpu_msr(void);376 377 /* cbtable.c */378 void lb_vendor_dev_from_string(char *boardstring);379 int coreboot_init(void);380 extern char *lb_part, *lb_vendor;381 extern int partvendor_from_cbtable;382 383 /* dmi.c */384 extern int has_dmi_support;385 void dmi_init(void);386 int dmi_match(const char *pattern);387 388 /* internal.c */389 #if NEED_PCI == 1390 struct superio {391 uint16_t vendor;392 uint16_t port;393 uint16_t model;394 };395 extern struct superio superio;396 #define SUPERIO_VENDOR_NONE 0x0397 #define SUPERIO_VENDOR_ITE 0x1398 struct pci_dev *pci_dev_find_filter(struct pci_filter filter);399 struct pci_dev *pci_dev_find_vendorclass(uint16_t vendor, uint16_t class);400 struct pci_dev *pci_dev_find(uint16_t vendor, uint16_t device);401 struct pci_dev *pci_card_find(uint16_t vendor, uint16_t device,402 uint16_t card_vendor, uint16_t card_device);403 #endif404 void get_io_perms(void);405 void release_io_perms(void);406 #if CONFIG_INTERNAL == 1407 extern int is_laptop;408 extern int force_boardenable;409 extern int force_boardmismatch;410 void probe_superio(void);411 int internal_init(void);412 int internal_shutdown(void);413 void internal_chip_writeb(uint8_t val, chipaddr addr);414 void internal_chip_writew(uint16_t val, chipaddr addr);415 void internal_chip_writel(uint32_t val, chipaddr addr);416 uint8_t internal_chip_readb(const chipaddr addr);417 uint16_t internal_chip_readw(const chipaddr addr);418 uint32_t internal_chip_readl(const chipaddr addr);419 void internal_chip_readn(uint8_t *buf, const chipaddr addr, size_t len);420 #endif421 422 /* hwaccess.c */423 void mmio_writeb(uint8_t val, void *addr);424 void mmio_writew(uint16_t val, void *addr);425 void mmio_writel(uint32_t val, void *addr);426 uint8_t mmio_readb(void *addr);427 uint16_t mmio_readw(void *addr);428 uint32_t mmio_readl(void *addr);429 void mmio_le_writeb(uint8_t val, void *addr);430 void mmio_le_writew(uint16_t val, void *addr);431 void mmio_le_writel(uint32_t val, void *addr);432 uint8_t mmio_le_readb(void *addr);433 uint16_t mmio_le_readw(void *addr);434 uint32_t mmio_le_readl(void *addr);435 #define pci_mmio_writeb mmio_le_writeb436 #define pci_mmio_writew mmio_le_writew437 #define pci_mmio_writel mmio_le_writel438 #define pci_mmio_readb mmio_le_readb439 #define pci_mmio_readw mmio_le_readw440 #define pci_mmio_readl mmio_le_readl441 442 /* programmer.c */443 int noop_shutdown(void);444 void *fallback_map(const char *descr, unsigned long phys_addr, size_t len);445 void fallback_unmap(void *virt_addr, size_t len);446 uint8_t noop_chip_readb(const chipaddr addr);447 void noop_chip_writeb(uint8_t val, chipaddr addr);448 void fallback_chip_writew(uint16_t val, chipaddr addr);449 void fallback_chip_writel(uint32_t val, chipaddr addr);450 void fallback_chip_writen(uint8_t *buf, chipaddr addr, size_t len);451 uint16_t fallback_chip_readw(const chipaddr addr);452 uint32_t fallback_chip_readl(const chipaddr addr);453 void fallback_chip_readn(uint8_t *buf, const chipaddr addr, size_t len);454 455 /* dummyflasher.c */456 #if CONFIG_DUMMY == 1457 int dummy_init(void);458 int dummy_shutdown(void);459 void *dummy_map(const char *descr, unsigned long phys_addr, size_t len);460 void dummy_unmap(void *virt_addr, size_t len);461 void dummy_chip_writeb(uint8_t val, chipaddr addr);462 void dummy_chip_writew(uint16_t val, chipaddr addr);463 void dummy_chip_writel(uint32_t val, chipaddr addr);464 void dummy_chip_writen(uint8_t *buf, chipaddr addr, size_t len);465 uint8_t dummy_chip_readb(const chipaddr addr);466 uint16_t dummy_chip_readw(const chipaddr addr);467 uint32_t dummy_chip_readl(const chipaddr addr);468 void dummy_chip_readn(uint8_t *buf, const chipaddr addr, size_t len);469 int dummy_spi_send_command(unsigned int writecnt, unsigned int readcnt,470 const unsigned char *writearr, unsigned char *readarr);471 int dummy_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len);472 int dummy_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len);473 #endif474 475 /* nic3com.c */476 #if CONFIG_NIC3COM == 1477 int nic3com_init(void);478 int nic3com_shutdown(void);479 void nic3com_chip_writeb(uint8_t val, chipaddr addr);480 uint8_t nic3com_chip_readb(const chipaddr addr);481 extern const struct pcidev_status nics_3com[];482 #endif483 484 /* gfxnvidia.c */485 #if CONFIG_GFXNVIDIA == 1486 int gfxnvidia_init(void);487 int gfxnvidia_shutdown(void);488 void gfxnvidia_chip_writeb(uint8_t val, chipaddr addr);489 uint8_t gfxnvidia_chip_readb(const chipaddr addr);490 extern const struct pcidev_status gfx_nvidia[];491 #endif492 493 /* drkaiser.c */494 #if CONFIG_DRKAISER == 1495 int drkaiser_init(void);496 int drkaiser_shutdown(void);497 void drkaiser_chip_writeb(uint8_t val, chipaddr addr);498 uint8_t drkaiser_chip_readb(const chipaddr addr);499 extern const struct pcidev_status drkaiser_pcidev[];500 #endif501 502 /* nicrealtek.c */503 #if CONFIG_NICREALTEK == 1504 int nicrealtek_init(void);505 int nicsmc1211_init(void);506 int nicrealtek_shutdown(void);507 void nicrealtek_chip_writeb(uint8_t val, chipaddr addr);508 uint8_t nicrealtek_chip_readb(const chipaddr addr);509 extern const struct pcidev_status nics_realtek[];510 extern const struct pcidev_status nics_realteksmc1211[];511 #endif512 513 /* nicnatsemi.c */514 #if CONFIG_NICNATSEMI == 1515 int nicnatsemi_init(void);516 int nicnatsemi_shutdown(void);517 void nicnatsemi_chip_writeb(uint8_t val, chipaddr addr);518 uint8_t nicnatsemi_chip_readb(const chipaddr addr);519 extern const struct pcidev_status nics_natsemi[];520 #endif521 522 /* satasii.c */523 #if CONFIG_SATASII == 1524 int satasii_init(void);525 int satasii_shutdown(void);526 void satasii_chip_writeb(uint8_t val, chipaddr addr);527 uint8_t satasii_chip_readb(const chipaddr addr);528 extern const struct pcidev_status satas_sii[];529 #endif530 531 /* atahpt.c */532 #if CONFIG_ATAHPT == 1533 int atahpt_init(void);534 int atahpt_shutdown(void);535 void atahpt_chip_writeb(uint8_t val, chipaddr addr);536 uint8_t atahpt_chip_readb(const chipaddr addr);537 extern const struct pcidev_status ata_hpt[];538 #endif539 540 /* ft2232_spi.c */541 #define FTDI_FT2232H 0x6010542 #define FTDI_FT4232H 0x6011543 int ft2232_spi_init(void);544 int ft2232_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr);545 int ft2232_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len);546 int ft2232_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len);547 548 /* rayer_spi.c */549 #if CONFIG_RAYER_SPI == 1550 int rayer_spi_init(void);551 #endif552 553 /* bitbang_spi.c */554 int bitbang_spi_init(const struct bitbang_spi_master *master, int halfperiod);555 int bitbang_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr);556 int bitbang_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len);557 int bitbang_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len);558 559 /* buspirate_spi.c */560 struct buspirate_spispeeds {561 const char *name;562 const int speed;563 };564 int buspirate_spi_init(void);565 int buspirate_spi_shutdown(void);566 int buspirate_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr);567 int buspirate_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len);568 int buspirate_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len);569 570 /* dediprog.c */571 int dediprog_init(void);572 int dediprog_shutdown(void);573 int dediprog_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr);574 int dediprog_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len);575 172 576 173 /* flashrom.c */ … … 581 178 }; 582 179 extern enum chipbustype buses_supported; 583 struct decode_sizes {584 uint32_t parallel;585 uint32_t lpc;586 uint32_t fwh;587 uint32_t spi;588 };589 extern struct decode_sizes max_rom_decode;590 extern int programmer_may_write;591 extern unsigned long flashbase;592 180 extern int verbose; 593 181 extern const char * const flashrom_version; … … 598 186 struct flashchip *probe_flash(struct flashchip *first_flash, int force); 599 187 int read_flash_to_file(struct flashchip *flash, char *filename); 600 void check_chip_supported(struct flashchip *flash);601 int check_max_decode(enum chipbustype buses, uint32_t size);602 188 int min(int a, int b); 603 189 int max(int a, int b); 604 190 char *extract_param(char **haystack, char *needle, char *delim); 605 char *extract_programmer_param(char *param_name);606 191 int check_erased_range(struct flashchip *flash, int start, int len); 607 192 int verify_range(struct flashchip *flash, uint8_t *cmpbuf, int start, int len, char *message); … … 643 228 644 229 /* layout.c */ 645 int show_id(uint8_t *bios, int size, int force);646 230 int read_romlayout(char *name); 647 231 int find_romentry(char *name); … … 649 233 650 234 /* spi.c */ 651 enum spi_controller {652 SPI_CONTROLLER_NONE,653 #if CONFIG_INTERNAL == 1654 #if defined(__i386__) || defined(__x86_64__)655 SPI_CONTROLLER_ICH7,656 SPI_CONTROLLER_ICH9,657 SPI_CONTROLLER_IT87XX,658 SPI_CONTROLLER_SB600,659 SPI_CONTROLLER_VIA,660 SPI_CONTROLLER_WBSIO,661 #endif662 #endif663 #if CONFIG_FT2232_SPI == 1664 SPI_CONTROLLER_FT2232,665 #endif666 #if CONFIG_DUMMY == 1667 SPI_CONTROLLER_DUMMY,668 #endif669 #if CONFIG_BUSPIRATE_SPI == 1670 SPI_CONTROLLER_BUSPIRATE,671 #endif672 #if CONFIG_DEDIPROG == 1673 SPI_CONTROLLER_DEDIPROG,674 #endif675 #if CONFIG_RAYER_SPI == 1676 SPI_CONTROLLER_RAYER,677 #endif678 SPI_CONTROLLER_INVALID /* This must always be the last entry. */679 };680 extern const int spi_programmer_count;681 235 struct spi_command { 682 236 unsigned int writecnt; … … 685 239 unsigned char *readarr; 686 240 }; 687 struct spi_programmer {688 int (*command)(unsigned int writecnt, unsigned int readcnt,689 const unsigned char *writearr, unsigned char *readarr);690 int (*multicommand)(struct spi_command *cmds);691 692 /* Optimized functions for this programmer */693 int (*read)(struct flashchip *flash, uint8_t *buf, int start, int len);694 int (*write_256)(struct flashchip *flash, uint8_t *buf, int start, int len);695 };696 697 extern enum spi_controller spi_controller;698 extern const struct spi_programmer spi_programmer[];699 241 int spi_send_command(unsigned int writecnt, unsigned int readcnt, 700 242 const unsigned char *writearr, unsigned char *readarr); 701 243 int spi_send_multicommand(struct spi_command *cmds); 702 int default_spi_send_command(unsigned int writecnt, unsigned int readcnt,703 const unsigned char *writearr, unsigned char *readarr);704 int default_spi_send_multicommand(struct spi_command *cmds);705 244 uint32_t spi_get_valid_read_addr(void); 706 245 707 /* ichspi.c */708 #if CONFIG_INTERNAL == 1709 extern uint32_t ichspi_bbar;710 int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb,711 int ich_generation);712 int via_init_spi(struct pci_dev *dev);713 int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt,714 const unsigned char *writearr, unsigned char *readarr);715 int ich_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len);716 int ich_spi_write_256(struct flashchip *flash, uint8_t * buf, int start, int len);717 int ich_spi_send_multicommand(struct spi_command *cmds);718 #endif719 720 /* it87spi.c */721 void enter_conf_mode_ite(uint16_t port);722 void exit_conf_mode_ite(uint16_t port);723 struct superio probe_superio_ite(void);724 int init_superio_ite(void);725 int it87spi_init(void);726 int it8716f_spi_send_command(unsigned int writecnt, unsigned int readcnt,727 const unsigned char *writearr, unsigned char *readarr);728 int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len);729 int it8716f_spi_chip_write_256(struct flashchip *flash, uint8_t *buf, int start, int len);730 731 /* sb600spi.c */732 #if CONFIG_INTERNAL == 1733 int sb600_probe_spi(struct pci_dev *dev);734 int sb600_spi_send_command(unsigned int writecnt, unsigned int readcnt,735 const unsigned char *writearr, unsigned char *readarr);736 int sb600_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len);737 int sb600_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len);738 #endif739 740 /* wbsio_spi.c */741 #if CONFIG_INTERNAL == 1742 int wbsio_check_for_spi(void);743 int wbsio_spi_send_command(unsigned int writecnt, unsigned int readcnt,744 const unsigned char *writearr, unsigned char *readarr);745 int wbsio_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len);746 #endif747 748 /* serprog.c */749 int serprog_init(void);750 int serprog_shutdown(void);751 void serprog_chip_writeb(uint8_t val, chipaddr addr);752 uint8_t serprog_chip_readb(const chipaddr addr);753 void serprog_chip_readn(uint8_t *buf, const chipaddr addr, size_t len);754 void serprog_delay(int delay);755 756 /* serial.c */757 #if _WIN32758 typedef HANDLE fdtype;759 #else760 typedef int fdtype;761 #endif762 763 void sp_flush_incoming(void);764 fdtype sp_openserport(char *dev, unsigned int baud);765 void __attribute__((noreturn)) sp_die(char *msg);766 extern fdtype sp_fd;767 int serialport_shutdown(void);768 int serialport_write(unsigned char *buf, unsigned int writecnt);769 int serialport_read(unsigned char *buf, unsigned int readcnt);770 771 246 #endif /* !__FLASH_H__ */ -
trunk/flashrom.c
r1093 r1112 34 34 #include "flash.h" 35 35 #include "flashchips.h" 36 #include "programmer.h" 36 37 37 38 const char * const flashrom_version = FLASHROM_VERSION; -
trunk/ft2232_spi.c
r1082 r1112 28 28 #include "flash.h" 29 29 #include "chipdrivers.h" 30 #include "programmer.h" 30 31 #include "spi.h" 31 32 #include <ftdi.h> -
trunk/gfxnvidia.c
r1111 r1112 23 23 #include <sys/types.h> 24 24 #include "flash.h" 25 #include "programmer.h" 25 26 26 27 #define PCI_VENDOR_ID_NVIDIA 0x10de -
trunk/ichspi.c
r1098 r1112 39 39 #include "flash.h" 40 40 #include "chipdrivers.h" 41 #include "programmer.h" 41 42 #include "spi.h" 42 43 -
trunk/internal.c
r1073 r1112 24 24 #include <sys/types.h> 25 25 #include "flash.h" 26 #include "programmer.h" 26 27 27 28 #if NEED_PCI == 1 -
trunk/it87spi.c
r1082 r1112 30 30 #include "flash.h" 31 31 #include "chipdrivers.h" 32 #include "programmer.h" 32 33 #include "spi.h" 33 34 -
trunk/layout.c
r1068 r1112 24 24 #include <ctype.h> 25 25 #include "flash.h" 26 #include "programmer.h" 26 27 27 28 #if CONFIG_INTERNAL == 1 -
trunk/nic3com.c
r1070 r1112 23 23 #include <stdlib.h> 24 24 #include "flash.h" 25 #include "programmer.h" 25 26 26 27 #define BIOS_ROM_ADDR 0x04 -
trunk/nicnatsemi.c
r1095 r1112 23 23 #include <stdlib.h> 24 24 #include "flash.h" 25 #include "programmer.h" 25 26 26 27 #define PCI_VENDOR_ID_NATSEMI 0x100b -
trunk/nicrealtek.c
r1070 r1112 23 23 #include <stdlib.h> 24 24 #include "flash.h" 25 #include "programmer.h" 25 26 26 27 #define PCI_VENDOR_ID_REALTEK 0x10ec -
trunk/pcidev.c
r1072 r1112 23 23 #include <sys/types.h> 24 24 #include "flash.h" 25 #include "programmer.h" 25 26 26 27 uint32_t io_base_addr; -
trunk/print.c
r1109 r1112 25 25 #include "flash.h" 26 26 #include "flashchips.h" 27 #include "programmer.h" 27 28 28 29 /* -
trunk/print_wiki.c
r1095 r1112 26 26 #include "flash.h" 27 27 #include "flashchips.h" 28 #include "programmer.h" 28 29 29 30 static const char * const wiki_header = "= Supported devices =\n\n\ -
trunk/processor_enable.c
r1031 r1112 23 23 24 24 #include "flash.h" 25 #include "programmer.h" 25 26 26 27 #if defined(__i386__) || defined(__x86_64__) -
trunk/programmer.h
r1111 r1112 22 22 */ 23 23 24 #ifndef __FLASH_H__ 25 #define __FLASH_H__ 1 26 27 #include <stdint.h> 28 #include <stddef.h> 29 #include "hwaccess.h" 30 #ifdef _WIN32 31 #include <windows.h> 32 #undef min 33 #undef max 34 #endif 35 36 typedef unsigned long chipaddr; 24 #ifndef __PROGRAMMER_H__ 25 #define __PROGRAMMER_H__ 1 37 26 38 27 enum programmer { … … 114 103 extern const struct programmer_entry programmer_table[]; 115 104 116 int register_shutdown(void (*function) (void *data), void *data);117 118 105 int programmer_init(char *param); 119 106 int programmer_shutdown(void); 120 void *programmer_map_flash_region(const char *descr, unsigned long phys_addr,121 size_t len);122 void programmer_unmap_flash_region(void *virt_addr, size_t len);123 void chip_writeb(uint8_t val, chipaddr addr);124 void chip_writew(uint16_t val, chipaddr addr);125 void chip_writel(uint32_t val, chipaddr addr);126 void chip_writen(uint8_t *buf, chipaddr addr, size_t len);127 uint8_t chip_readb(const chipaddr addr);128 uint16_t chip_readw(const chipaddr addr);129 uint32_t chip_readl(const chipaddr addr);130 void chip_readn(uint8_t *buf, const chipaddr addr, size_t len);131 void programmer_delay(int usecs);132 107 133 108 enum bitbang_spi_master_type { … … 147 122 int (*get_miso) (void); 148 123 }; 149 150 #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))151 152 enum chipbustype {153 CHIP_BUSTYPE_NONE = 0,154 CHIP_BUSTYPE_PARALLEL = 1 << 0,155 CHIP_BUSTYPE_LPC = 1 << 1,156 CHIP_BUSTYPE_FWH = 1 << 2,157 CHIP_BUSTYPE_SPI = 1 << 3,158 CHIP_BUSTYPE_NONSPI = CHIP_BUSTYPE_PARALLEL | CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH,159 CHIP_BUSTYPE_UNKNOWN = CHIP_BUSTYPE_PARALLEL | CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI,160 };161 162 /*163 * How many different contiguous runs of erase blocks with one size each do164 * we have for a given erase function?165 */166 #define NUM_ERASEREGIONS 5167 168 /*169 * How many different erase functions do we have per chip?170 */171 #define NUM_ERASEFUNCTIONS 5172 173 #define FEATURE_REGISTERMAP (1 << 0)174 #define FEATURE_BYTEWRITES (1 << 1)175 #define FEATURE_LONG_RESET (0 << 4)176 #define FEATURE_SHORT_RESET (1 << 4)177 #define FEATURE_EITHER_RESET FEATURE_LONG_RESET178 #define FEATURE_ADDR_FULL (0 << 2)179 #define FEATURE_ADDR_MASK (3 << 2)180 #define FEATURE_ADDR_2AA (1 << 2)181 #define FEATURE_ADDR_AAA (2 << 2)182 #define FEATURE_ADDR_SHIFTED (1 << 5)183 184 struct flashchip {185 const char *vendor;186 const char *name;187 188 enum chipbustype bustype;189 190 /*191 * With 32bit manufacture_id and model_id we can cover IDs up to192 * (including) the 4th bank of JEDEC JEP106W Standard Manufacturer's193 * Identification code.194 */195 uint32_t manufacture_id;196 uint32_t model_id;197 198 int total_size;199 int page_size;200 int feature_bits;201 202 /*203 * Indicate if flashrom has been tested with this flash chip and if204 * everything worked correctly.205 */206 uint32_t tested;207 208 int (*probe) (struct flashchip *flash);209 210 /* Delay after "enter/exit ID mode" commands in microseconds. */211 int probe_timing;212 213 /*214 * Erase blocks and associated erase function. Any chip erase function215 * is stored as chip-sized virtual block together with said function.216 */217 struct block_eraser {218 struct eraseblock{219 unsigned int size; /* Eraseblock size */220 unsigned int count; /* Number of contiguous blocks with that size */221 } eraseblocks[NUM_ERASEREGIONS];222 int (*block_erase) (struct flashchip *flash, unsigned int blockaddr, unsigned int blocklen);223 } block_erasers[NUM_ERASEFUNCTIONS];224 225 int (*printlock) (struct flashchip *flash);226 int (*unlock) (struct flashchip *flash);227 int (*write) (struct flashchip *flash, uint8_t *buf);228 int (*read) (struct flashchip *flash, uint8_t *buf, int start, int len);229 230 /* Some flash devices have an additional register space. */231 chipaddr virtual_memory;232 chipaddr virtual_registers;233 };234 235 #define TEST_UNTESTED 0236 237 #define TEST_OK_PROBE (1 << 0)238 #define TEST_OK_READ (1 << 1)239 #define TEST_OK_ERASE (1 << 2)240 #define TEST_OK_WRITE (1 << 3)241 #define TEST_OK_PR (TEST_OK_PROBE | TEST_OK_READ)242 #define TEST_OK_PRE (TEST_OK_PROBE | TEST_OK_READ | TEST_OK_ERASE)243 #define TEST_OK_PRW (TEST_OK_PROBE | TEST_OK_READ | TEST_OK_WRITE)244 #define TEST_OK_PREW (TEST_OK_PROBE | TEST_OK_READ | TEST_OK_ERASE | TEST_OK_WRITE)245 #define TEST_OK_MASK 0x0f246 247 #define TEST_BAD_PROBE (1 << 4)248 #define TEST_BAD_READ (1 << 5)249 #define TEST_BAD_ERASE (1 << 6)250 #define TEST_BAD_WRITE (1 << 7)251 #define TEST_BAD_PREW (TEST_BAD_PROBE | TEST_BAD_READ | TEST_BAD_ERASE | TEST_BAD_WRITE)252 #define TEST_BAD_MASK 0xf0253 254 /* Timing used in probe routines. ZERO is -2 to differentiate between an unset255 * field and zero delay.256 *257 * SPI devices will always have zero delay and ignore this field.258 */259 #define TIMING_FIXME -1260 /* this is intentionally same value as fixme */261 #define TIMING_IGNORED -1262 #define TIMING_ZERO -2263 264 extern struct flashchip flashchips[];265 124 266 125 #if CONFIG_INTERNAL == 1 … … 320 179 extern const struct board_info boards_known[]; 321 180 extern const struct board_info laptops_known[]; 322 323 181 #endif 324 182 … … 330 188 #if NEED_PCI == 1 331 189 /* pcidev.c */ 332 333 190 extern uint32_t io_base_addr; 334 191 extern struct pci_access *pacc; … … 346 203 347 204 /* print.c */ 348 char *flashbuses_to_text(enum chipbustype bustype);349 void print_supported(void);350 205 #if CONFIG_NIC3COM+CONFIG_NICREALTEK+CONFIG_NICNATSEMI+CONFIG_GFXNVIDIA+CONFIG_DRKAISER+CONFIG_SATASII+CONFIG_ATAHPT >= 1 351 206 void print_supported_pcidevs(const struct pcidev_status *devs); 352 207 #endif 353 void print_supported_wiki(void);354 208 355 209 /* board_enable.c */ … … 575 429 576 430 /* flashrom.c */ 577 enum write_granularity {578 write_gran_1bit,579 write_gran_1byte,580 write_gran_256bytes,581 };582 extern enum chipbustype buses_supported;583 431 struct decode_sizes { 584 432 uint32_t parallel; … … 590 438 extern int programmer_may_write; 591 439 extern unsigned long flashbase; 592 extern int verbose;593 extern const char * const flashrom_version;594 extern char *chip_to_probe;595 void map_flash_registers(struct flashchip *flash);596 int read_memmapped(struct flashchip *flash, uint8_t *buf, int start, int len);597 int erase_flash(struct flashchip *flash);598 struct flashchip *probe_flash(struct flashchip *first_flash, int force);599 int read_flash_to_file(struct flashchip *flash, char *filename);600 440 void check_chip_supported(struct flashchip *flash); 601 441 int check_max_decode(enum chipbustype buses, uint32_t size); 602 int min(int a, int b);603 int max(int a, int b);604 char *extract_param(char **haystack, char *needle, char *delim);605 442 char *extract_programmer_param(char *param_name); 606 int check_erased_range(struct flashchip *flash, int start, int len);607 int verify_range(struct flashchip *flash, uint8_t *cmpbuf, int start, int len, char *message);608 int need_erase(uint8_t *have, uint8_t *want, int len, enum write_granularity gran);609 char *strcat_realloc(char *dest, const char *src);610 void print_version(void);611 void print_banner(void);612 int selfcheck(void);613 int doit(struct flashchip *flash, int force, char *filename, int read_it, int write_it, int erase_it, int verify_it);614 615 #define OK 0616 #define NT 1 /* Not tested */617 618 /* Something happened that shouldn't happen, but we can go on */619 #define ERROR_NONFATAL 0x100620 621 /* cli_output.c */622 /* Let gcc and clang check for correct printf-style format strings. */623 int print(int type, const char *fmt, ...) __attribute__((format(printf, 2, 3)));624 #define MSG_ERROR 0625 #define MSG_INFO 1626 #define MSG_DEBUG 2627 #define MSG_BARF 3628 #define msg_gerr(...) print(MSG_ERROR, __VA_ARGS__) /* general errors */629 #define msg_perr(...) print(MSG_ERROR, __VA_ARGS__) /* programmer errors */630 #define msg_cerr(...) print(MSG_ERROR, __VA_ARGS__) /* chip errors */631 #define msg_ginfo(...) print(MSG_INFO, __VA_ARGS__) /* general info */632 #define msg_pinfo(...) print(MSG_INFO, __VA_ARGS__) /* programmer info */633 #define msg_cinfo(...) print(MSG_INFO, __VA_ARGS__) /* chip info */634 #define msg_gdbg(...) print(MSG_DEBUG, __VA_ARGS__) /* general debug */635 #define msg_pdbg(...) print(MSG_DEBUG, __VA_ARGS__) /* programmer debug */636 #define msg_cdbg(...) print(MSG_DEBUG, __VA_ARGS__) /* chip debug */637 #define msg_gspew(...) print(MSG_BARF, __VA_ARGS__) /* general debug barf */638 #define msg_pspew(...) print(MSG_BARF, __VA_ARGS__) /* programmer debug barf */639 #define msg_cspew(...) print(MSG_BARF, __VA_ARGS__) /* chip debug barf */640 641 /* cli_classic.c */642 int cli_classic(int argc, char *argv[]);643 443 644 444 /* layout.c */ 645 445 int show_id(uint8_t *bios, int size, int force); 646 int read_romlayout(char *name);647 int find_romentry(char *name);648 int handle_romentries(uint8_t *buffer, struct flashchip *flash);649 446 650 447 /* spi.c */ … … 679 476 }; 680 477 extern const int spi_programmer_count; 681 struct spi_command {682 unsigned int writecnt;683 unsigned int readcnt;684 const unsigned char *writearr;685 unsigned char *readarr;686 };687 478 struct spi_programmer { 688 479 int (*command)(unsigned int writecnt, unsigned int readcnt, … … 697 488 extern enum spi_controller spi_controller; 698 489 extern const struct spi_programmer spi_programmer[]; 699 int spi_send_command(unsigned int writecnt, unsigned int readcnt,700 const unsigned char *writearr, unsigned char *readarr);701 int spi_send_multicommand(struct spi_command *cmds);702 490 int default_spi_send_command(unsigned int writecnt, unsigned int readcnt, 703 491 const unsigned char *writearr, unsigned char *readarr); 704 492 int default_spi_send_multicommand(struct spi_command *cmds); 705 uint32_t spi_get_valid_read_addr(void);706 493 707 494 /* ichspi.c */ … … 769 556 int serialport_read(unsigned char *buf, unsigned int readcnt); 770 557 771 #endif /* !__ FLASH_H__ */558 #endif /* !__PROGRAMMER_H__ */ -
trunk/rayer_spi.c
r1093 r1112 32 32 33 33 #include "flash.h" 34 #include "programmer.h" 34 35 35 36 /* We have two sets of pins, out and in. The numbers for both sets are -
trunk/satasii.c
r1111 r1112 23 23 #include <stdlib.h> 24 24 #include "flash.h" 25 #include "programmer.h" 25 26 26 27 #define PCI_VENDOR_ID_SII 0x1095 -
trunk/sb600spi.c
r1099 r1112 26 26 #include "flash.h" 27 27 #include "chipdrivers.h" 28 #include "programmer.h" 28 29 #include "spi.h" 29 30 -
trunk/serial.c
r933 r1112 23 23 #include <stdlib.h> 24 24 #include <unistd.h> 25 #include "flash.h"26 25 #include <string.h> 27 26 #include <ctype.h> … … 36 35 #include <termios.h> 37 36 #endif 37 #include "flash.h" 38 #include "programmer.h" 38 39 39 40 fdtype sp_fd; -
trunk/serprog.c
r1072 r1112 23 23 #include <stdlib.h> 24 24 #include <unistd.h> 25 #include "flash.h"26 25 #include <string.h> 27 26 #include <ctype.h> … … 37 36 #include <inttypes.h> 38 37 #include <termios.h> 38 #include "flash.h" 39 #include "programmer.h" 39 40 40 41 #define MSGHEADER "serprog:" -
trunk/spi.c
r1093 r1112 26 26 #include "flashchips.h" 27 27 #include "chipdrivers.h" 28 #include "programmer.h" 28 29 #include "spi.h" 29 30 -
trunk/spi25.c
r1096 r1112 27 27 #include "flashchips.h" 28 28 #include "chipdrivers.h" 29 #include "programmer.h" 29 30 #include "spi.h" 30 31 -
trunk/wbsio_spi.c
r1081 r1112 23 23 #include "flash.h" 24 24 #include "chipdrivers.h" 25 #include "programmer.h" 25 26 #include "spi.h" 26 27
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