Changeset 1405

Timestamp:

08/06/11 14:45:21 (10 months ago)

Author:

stefanct

Message:

Clear byte 0x92 of the LPC bridge for all CK804 (and MCP51) chipsets

The OEM BIOS on the EPoX EP-8PA7I and a number of other boards clear
byte 0x92 in the LPC bridge configuration space. Do the same for
all CK804 chips, assuming this to be some sort of chipset-generic
write-enable.

Currently the same chipset enable is used for MCP51 (nForce 430).
There have been reports of successful writes with its variations
(e.g. A8N-LA (Nagami-GL8E)), but they were not tagged as OK. Due to
the new "unsupported chipset"-message we will get success reports in
the case this patch does not break anything on the MCP51-based boards.

See also:
http://www.flashrom.org/pipermail/flashrom/2011-July/007252.html
 http://patchwork.coreboot.org/patch/3176/

Signed-off-by: Jonathan Kollasch <jakllsch@…>
Acked-by: Joshua Roys <roysjosh@…>
Acked-by: Stefan Tauner <stefan.tauner@…>

File:

• trunk/chipset_enable.c (modified) (1 diff)

trunk/chipset_enable.c

@@ -801 +801 @@
 {
         uint8_t old, new;
+
+        pci_write_byte(dev, 0x92, 0x00);
+        if (pci_read_byte(dev, 0x92) != 0x00) {
+                msg_pinfo("Setting register 0x%x to 0x%x on %s failed "
+                          "(WARNING ONLY).\n", 0x92, 0x00, name);
+        }
 
         old = pci_read_byte(dev, 0x88);