Changeset 1463 for trunk/chipset_enable.c
- Timestamp:
- 11/10/11 00:40:00 (6 months ago)
- File:
-
- 1 edited
-
trunk/chipset_enable.c (modified) (15 diffs)
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- Added
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trunk/chipset_enable.c
r1461 r1463 214 214 uint16_t xbcs = 0x4e; /* X-Bus Chip Select register. */ 215 215 216 buses_supported = BUS_PARALLEL;216 internal_buses_supported = BUS_PARALLEL; 217 217 218 218 old = pci_read_word(dev, xbcs); … … 304 304 * FB_DEC_EN2. 305 305 */ 306 buses_supported = BUS_FWH;306 internal_buses_supported = BUS_FWH; 307 307 return enable_flash_ich(dev, name, 0x4e); 308 308 } … … 413 413 414 414 /* If we're called by enable_flash_ich_dc_spi, it will override 415 * buses_supported anyway.415 * internal_buses_supported anyway. 416 416 */ 417 buses_supported = BUS_FWH;417 internal_buses_supported = BUS_FWH; 418 418 return enable_flash_ich(dev, name, 0xdc); 419 419 } … … 435 435 rpci_write_byte(dev, 0xd9, new); 436 436 437 buses_supported = BUS_FWH;437 internal_buses_supported = BUS_FWH; 438 438 return 0; 439 439 } … … 469 469 if (bnt & 0x02) { 470 470 /* If strapped to LPC, no SPI initialization is required */ 471 buses_supported = BUS_FWH;471 internal_buses_supported = BUS_FWH; 472 472 return 0; 473 473 } 474 474 475 475 /* This adds BUS_SPI */ 476 buses_supported = BUS_SPI;477 476 if (ich_init_spi(dev, tmp, rcrb, 7) != 0) { 478 477 if (!ret) … … 557 556 * on ICH7 when the southbridge is strapped to LPC 558 557 */ 559 buses_supported = BUS_FWH;558 internal_buses_supported = BUS_FWH; 560 559 if (ich_generation == CHIPSET_ICH7) { 561 560 if (bbs == 0x03) { … … 565 564 } else { 566 565 /* Disable LPC/FWH if strapped to PCI or SPI */ 567 buses_supported = 0;566 internal_buses_supported = BUS_NONE; 568 567 } 569 568 } … … 670 669 #define CS5530_ENABLE_SA20 (1 << 6) 671 670 672 buses_supported = BUS_PARALLEL;671 internal_buses_supported = BUS_PARALLEL; 673 672 /* Decode 0x000E0000-0x000FFFFF (128 kB), not just 64 kB, and 674 673 * decode 0xFF000000-0xFFFFFFFF (16 MB), not just 256 kB. … … 823 822 } 824 823 825 buses_supported = BUS_LPC | BUS_FWH;824 internal_buses_supported = BUS_LPC | BUS_FWH; 826 825 827 826 ret = sb600_probe_spi(dev); … … 917 916 uint8_t tmp; 918 917 919 buses_supported = BUS_PARALLEL;918 internal_buses_supported = BUS_PARALLEL; 920 919 921 920 tmp = INB(0xc06); … … 1017 1016 case 0x0: 1018 1017 ret = enable_flash_mcp55(dev, name); 1019 buses_supported = BUS_LPC;1018 internal_buses_supported = BUS_LPC; 1020 1019 msg_pdbg("Flash bus type is LPC\n"); 1021 1020 break; … … 1025 1024 * Do we really want to disable LPC in this case? 1026 1025 */ 1027 buses_supported = BUS_NONE;1026 internal_buses_supported = BUS_NONE; 1028 1027 msg_pdbg("Flash bus type is SPI\n"); 1029 1028 msg_pinfo("SPI on this chipset is WIP. Please report any " … … 1033 1032 default: 1034 1033 /* Should not happen. */ 1035 buses_supported = BUS_NONE;1034 internal_buses_supported = BUS_NONE; 1036 1035 msg_pdbg("Flash bus type is unknown (none)\n"); 1037 1036 msg_pinfo("Something went wrong with bus type detection.\n"); … … 1326 1325 int ret = -2; /* Nothing! */ 1327 1326 int i; 1328 char *s;1329 1327 1330 1328 /* Now let's try to find the chipset we have... */ … … 1378 1376 } 1379 1377 1380 s = flashbuses_to_text(buses_supported);1381 msg_pinfo("This chipset supports the following protocols: %s.\n", s);1382 free(s);1383 1384 1378 return ret; 1385 1379 }
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