Changeset 985


Ignore:
Timestamp:
03/26/10 00:18:41 (23 months ago)
Author:
uwe
Message:

Polish the flashrom code comments and outputs a bit.

  • Fix a number of typos (found via ispell).
  • Use correct vendor names (as per their websites) consistently.

Signed-off-by: Uwe Hermann <uwe@…>
Acked-by: Uwe Hermann <uwe@…>

Location:
trunk
Files:
10 edited

Legend:

Unmodified
Added
Removed

  • trunk/README

    r963 r985  
    122122  #flashrom at irc.freenode.net 
    123123 
    124 The Mailing list addess is 
     124The mailing list address is 
    125125 
    126126  flashrom@flashrom.org 

  • trunk/board_enable.c

    r983 r985  
    342342 
    343343/** 
    344  * Suited for Asus M2V-MX: VIA K8M890 + VT8237A + IT8716F 
     344 * Suited for ASUS M2V-MX: VIA K8M890 + VT8237A + IT8716F 
    345345 */ 
    346346static int via_vt823x_gpio5_raise(const char *name) 
    … …  
    351351 
    352352/** 
    353  * Suited for VIAs EPIA N & NL. 
     353 * Suited for VIA EPIA N & NL. 
    354354 */ 
    355355static int via_vt823x_gpio9_raise(const char *name) 
    … …  
    359359 
    360360/** 
    361  * Suited for VIAs EPIA M and MII, and maybe other CLE266 based EPIAs. 
     361 * Suited for VIA EPIA M and MII, and maybe other CLE266 based EPIAs. 
    362362 * 
    363363 * We don't need to do this for EPIA M when using coreboot, GPIO15 is never 
    … …  
    485485 
    486486/** 
    487  * Suited for Shuttle FN25 (SN25P): AMD S939 + Nvidia CK804 (nForce4). 
     487 * Suited for Shuttle FN25 (SN25P): AMD S939 + NVIDIA CK804 (nForce4). 
    488488 */ 
    489489static int board_shuttle_fn25(const char *name) 
    … …  
    533533            default: 
    534534                fprintf(stderr, 
    535                         "\nERROR: no nVidia LPC/SMBus controller found.\n"); 
     535                        "\nERROR: no NVIDIA LPC/SMBus controller found.\n"); 
    536536                return -1; 
    537537            } 
    … …  
    554554/** 
    555555 * Suited for ASUS A8N-LA: nVidia MCP51. 
    556  * Suited for ASUS M2NBP-VM CSM: nVidia MCP51. 
     556 * Suited for ASUS M2NBP-VM CSM: NVIDIA MCP51. 
    557557 */ 
    558558static int nvidia_mcp_gpio0_raise(const char *name) 
    … …  
    570570 
    571571/** 
    572  * Suited for MSI K8N Neo4: nVidia CK804. 
    573  * Suited for MSI K8N GM2-L: nVidia MCP51. 
     572 * Suited for MSI K8N Neo4: NVIDIA CK804. 
     573 * Suited for MSI K8N GM2-L: NVIDIA MCP51. 
    574574 */ 
    575575static int nvidia_mcp_gpio2_raise(const char *name) 
    … …  
    644644 
    645645/** 
    646  * Helper function to raise/drop a given gpo line on intel PIIX4{,E,M} 
     646 * Helper function to raise/drop a given gpo line on Intel PIIX4{,E,M}. 
    647647 */ 
    648648static int intel_piix4_gpo_set(unsigned int gpo, int raise) 
    … …  
    732732 
    733733/** 
    734  * Set a GPIO line on a given intel ICH LPC controller. 
     734 * Set a GPIO line on a given Intel ICH LPC controller. 
    735735 */ 
    736736static int intel_ich_gpio_set(int gpio, int raise) 
    737737{ 
    738         /* table mapping the different intel ICH LPC chipsets. */ 
     738        /* Table mapping the different Intel ICH LPC chipsets. */ 
    739739        static struct { 
    740740                uint16_t id; 
    … …  
    802802        } 
    803803 
    804         /* According to the datasheets, all intel ICHs have the gpio bar 5:1 
    805            strapped to zero. From some mobile ich9 version on, this becomes 
     804        /* According to the datasheets, all Intel ICHs have the GPIO bar 5:1 
     805           strapped to zero. From some mobile ICH9 version on, this becomes 
    806806           6:1. The mask below catches all. */ 
    807807        base = pci_read_word(dev, intel_ich_gpio_table[i].base_reg) & 0xFFC0; 
    … …  
    950950/** 
    951951 * Suited for: 
    952  * - Asus P4B266LM (Sony Vaio PCV-RX650): socket478 + 845D + ICH2. 
    953  * - Asus P4C800-E Deluxe: socket478 + 875P + ICH5. 
    954  * - Asus P4P800-E Deluxe: Intel socket478 + 865PE + ICH5R. 
     952 * - ASUS P4B266LM (Sony Vaio PCV-RX650): socket478 + 845D + ICH2. 
     953 * - ASUS P4C800-E Deluxe: socket478 + 875P + ICH5. 
     954 * - ASUS P4P800-E Deluxe: Intel socket478 + 865PE + ICH5R. 
    955955 */ 
    956956static int intel_ich_gpio21_raise(const char *name) 
    … …  
    961961/** 
    962962 * Suited for: 
    963  *  - Asus P4B266: socket478 + intel 845D + ICH2. 
    964  *  - Asus P4B533-E: socket478 + 845E + ICH4 
    965  *  - Asus P4B-MX variant in HP Vectra VL420 SFF: socket478 + 845D + ICH2 
     963 *  - ASUS P4B266: socket478 + Intel 845D + ICH2. 
     964 *  - ASUS P4B533-E: socket478 + 845E + ICH4 
     965 *  - ASUS P4B-MX variant in HP Vectra VL420 SFF: socket478 + 845D + ICH2 
    966966 */ 
    967967static int intel_ich_gpio22_raise(const char *name) 
    … …  
    987987/** 
    988988 * Suited for: 
    989  * - Dell Poweredge 1850: Intel PPGA604 + E7520 + ICH5R. 
     989 * - Dell PowerEdge 1850: Intel PPGA604 + E7520 + ICH5R. 
    990990 * - ASRock P4i65GV: Intel Socket478 + 865GV + ICH5R. 
    991991 */ 
    … …  
    11981198 
    11991199/** 
    1200  * Suited for Asus A7V8X: VIA KT400 + VT8235 + IT8703F-A 
     1200 * Suited for ASUS A7V8X: VIA KT400 + VT8235 + IT8703F-A 
    12011201 */ 
    12021202static int board_asus_a7v8x(const char *name) 
    … …  
    12921292/** 
    12931293 * Suited for: 
    1294  * - Asus A7V600-X: VIA KT600 + VT8237 + IT8712F 
    1295  * - Asus A7V8X-X: VIA KT400 + VT8235 + IT8712F 
     1294 * - ASUS A7V600-X: VIA KT600 + VT8237 + IT8712F 
     1295 * - ASUS A7V8X-X: VIA KT400 + VT8235 + IT8712F 
    12961296 */ 
    12971297static int it8712f_gpio3_1_raise(const char *name) 
    … …  
    13201320 * If PCI IDs are not sufficient for board matching, the match can be further 
    13211321 * constrained by a string that has to be present in the DMI database for 
    1322  * the baseboard or the system entry. The pattern is matched by case sensitve 
     1322 * the baseboard or the system entry. The pattern is matched by case sensitive 
    13231323 * substring match, unless it is anchored to the beginning (with a ^ in front) 
    13241324 * or the end (with a $ at the end). Both anchors may be specified at the 

  • trunk/coreboot_tables.h

    r586 r985  
    2828 * from the firmware to the loaded OS image.  Primarily this 
    2929 * is expected to be information that cannot be discovered by 
    30  * other means, such as quering the hardware directly. 
     30 * other means, such as querying the hardware directly. 
    3131 * 
    3232 * All of the information should be Position Independent Data.   
    3333 * That is it should be safe to relocated any of the information 
    34  * without it's meaning/correctnes changing.   For table that 
     34 * without it's meaning/correctness changing.   For table that 
    3535 * can reasonably be used on multiple architectures the data 
    3636 * size should be fixed.  This should ease the transition between 
    … …  
    4949 * long term compatibility burden as table entries which are 
    5050 * irrelevant or have been replaced by better alternatives may be 
    51  * dropped.  Of course it is polite and expidite to include extra 
     51 * dropped.  Of course it is polite and expedite to include extra 
    5252 * table entries and be backwards compatible, but it is not required. 
    5353 */ 
    … …  
    7979}; 
    8080 
    81 /* Every entry in the boot enviroment list will correspond to a boot 
     81/* Every entry in the boot environment list will correspond to a boot 
    8282 * info record.  Encoding both type and size.  The type is obviously 
    8383 * so you can tell what it is.  The size allows you to skip that 
    84  * boot enviroment record if you don't know what it easy.  This allows 
     84 * boot environment record if you don't know what it easy.  This allows 
    8585 * forward compatibility with records not yet defined. 
    8686 */ 

  • trunk/flashchips.c

    r984 r985  
    11341134 
    11351135        /* The next two chip definitions have top/bottom boot blocks, but has no 
    1136         device differenciation between the two */ 
     1136        device differentiation between the two */ 
    11371137        { 
    11381138                .vendor         = "AMIC", 

  • trunk/flashrom.8

    r983 r985  
    175175.SH PROGRAMMER SPECIFIC INFO 
    176176Some programmer drivers accept further parameters to set programmer-specific 
    177 parameters. These parameters are seperated from the programmer name by a 
     177parameters. These parameters are separated from the programmer name by a 
    178178colon. While some programmers take arguments at fixed positions, other 
    179179programmers use a key/value interface in which the key and value is separated 
    … …  
    299299.TP 
    300300.BR "buspiratespi " programmer 
    301 A required dev parameter specifyies the Bus Pirate device node and an optional 
    302 spispeed parameter specifyies the frequency of the SPI bus. The parameter 
     301A required dev parameter specifies the Bus Pirate device node and an optional 
     302spispeed parameter specifies the frequency of the SPI bus. The parameter 
    303303delimiter is a comma. Syntax is 
    304304.sp 

  • trunk/ichspi.c

    r914 r985  
    537537        /* clear error status registers */ 
    538538        temp32 |= (SSFS_CDS + SSFS_FCERR); 
    539         /* USE 20 MhZ */ 
     539        /* Use 20 MHz */ 
    540540        temp32 |= SSFC_SCF_20MHZ; 
    541541 

  • trunk/jedec.c

    r982 r985  
    346346 
    347347retry: 
    348         /* Issue JEDEC Start Program comand */ 
     348        /* Issue JEDEC Start Program command */ 
    349349        start_program_jedec_common(flash, mask); 
    350350 

  • trunk/serprog-protocol.txt

    r656 r985  
    4747                cmd 8 support: byte 1 bit 0, and so on. 
    4848        0x04 (Q_SERBUF): 
    49                 If the programmer has guaranteedly working flow control, 
     49                If the programmer has a guaranteed working flow control, 
    5050                it should return a big bogus value - eg 0xFFFF. 
    5151        0x05 (Q_BUSTYPE): 
    … …  
    5454        0x06 (Q_CHIPSIZE): 
    5555                Only applicable to parallel programmers. 
    56                 An LPC/FHW/SPI-programmer can report this as not supported in the command bitmap. 
     56                An LPC/FWH/SPI-programmer can report this as not supported in the command bitmap. 
    5757        0x08 (Q_WRNMAXLEN): 
    5858                If a programmer reports a bigger maximum write-n length than the serial buffer size, 

  • trunk/serprog.c

    r853 r985  
    6767static uint8_t sp_cmdmap[32]; 
    6868 
    69 /* sp_prev_was_write used to detect writes with continouous addresses 
     69/* sp_prev_was_write used to detect writes with contiguous addresses 
    7070        and combine them to write-n's */ 
    7171static int sp_prev_was_write = 0; 
    … …  
    139139} 
    140140 
    141 /* Synchronize: a bit tricky algorhytm that tries to (and in my tests has * 
     141/* Synchronize: a bit tricky algorithm that tries to (and in my tests has * 
    142142 * always succeeded in) bring the serial protocol to known waiting-for-   * 
    143143 * command state - uses nonblocking read - rest of the driver uses        * 
    … …  
    535535                sp_execute_opbuf(); 
    536536                /* If this happens in the mid of an page load the page load * 
    537                  * will propably fail.                                      */ 
     537                 * will probably fail.                                      */ 
    538538                msg_pdbg(MSGHEADER "Warning: executed operation buffer due to size reasons\n"); 
    539539        } 
    … …  
    590590} 
    591591 
    592 /* Local version that really does the job, doesnt care of max_read_n. */ 
     592/* Local version that really does the job, doesn't care of max_read_n. */ 
    593593static void sp_do_read_n(uint8_t * buf, const chipaddr addr, size_t len) 
    594594{ 

  • trunk/stm50flw0x0x.c

    r982 r985  
    5050         * of chip. 
    5151         * 
    52          * Sometimes, the BIOS does this for you; so you propably 
     52         * Sometimes, the BIOS does this for you; so you probably 
    5353         * don't need to worry about that. 
    5454         */ 
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