Difference between revisions of "BBB"

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(Created page with "= flashrom on the BeagleBone Black = '''This page is WIP.''' Required packages: the usual suspects. * build-essential * libpci-dev == Enabling SPI0 == Create a file <code>B...")
 
Line 8: Line 8:
 
== Enabling SPI0 ==
 
== Enabling SPI0 ==
  
Create a file <code>BB-SPI0-01-00A0.dts</code> with the following contents:
+
Tested with a BBB rev.c and its default installation (Linux 3.8.13-bone47).
 +
 
 +
Create a file <code>BB-SPI0-00A0.dts</code> with the following contents:
 
  <nowiki>
 
  <nowiki>
 +
/*
 +
* Copyright (C) 2013 CircuitCo
 +
* Copyright (C) 2014 Stefan Tauner
 +
*
 +
* Virtual cape for SPI0 of the BBB + 2 GPIO pins permanent high
 +
*
 +
* This program is free software; you can redistribute it and/or modify
 +
* it under the terms of the GNU General Public License version 2 as
 +
* published by the Free Software Foundation.
 +
*/
 
/dts-v1/;
 
/dts-v1/;
 
/plugin/;
 
/plugin/;
  
 
/ {
 
/ {
    compatible = "ti,beaglebone", "ti,beaglebone-black";
+
compatible = "ti,beaglebone", "ti,beaglebone-black";
 +
 
 +
/* identification */
 +
part-number = "BB-SPI0";
 +
version = "00A0";
 +
 
 +
/* state the resources this cape uses */
 +
exclusive-use =
 +
/* the pin header uses */
 +
"P9.17", /* SPI0 CS0 */
 +
"P9.18", /* SPI0 DI/MISO */
 +
"P9.21", /* SPI0 DO/MOSI */
 +
"P9.22", /* SPI0 SCLK */
 +
/* Use P9.23, P9.25 */
 +
"P9.23", /* GPIO1_17 */
 +
"P9.25", /* GPIO3_21 */
 +
/* the hardware ip uses */
 +
"spi0";
 +
 
 +
fragment@0 {
 +
target = <&am33xx_pinmux>;
 +
__overlay__ {
 +
/* default state has all gpios released and mode set to uart1 */
 +
bb_spi0_pins: pinmux_bb_spi0_pins {
 +
pinctrl-single,pins = <
 +
0x150 0x30 /* spi0_sclk, INPUT_PULLUP | MODE0 */
 +
0x154 0x30 /* spi0_d0, INPUT_PULLUP | MODE0 */
 +
0x158 0x10 /* spi0_d1, OUTPUT_PULLUP | MODE0 */
 +
0x15c 0x10 /* spi0_cs0, OUTPUT_PULLUP | MODE0 */
 +
0x044 0x10 /* gpmc_a1, OUTPUT_PULLUP | MODE0 */
 +
0x1AC 0x10 /* mcasp0_ahclkx, OUTPUT_PULLUP | MODE0 */
 +
>;
 +
};
 +
};
 +
};
  
    /* identification */
+
fragment@1 {
    part-number = "spi0pinmux";
+
target = <&spi0>; /* spi0 is numbered correctly */
 +
__overlay__ {
 +
#address-cells = <1>;
 +
#size-cells = <0>;
  
    fragment@0 {
+
status = "okay";
        target = <&am33xx_pinmux>;
+
pinctrl-names = "default";
        __overlay__ {
+
pinctrl-0 = <&bb_spi0_pins>;
            spi0_pins_s0: spi0_pins_s0 {
 
                pinctrl-single,pins = <
 
                  0x150 0x30  /* spi0_sclk, INPUT_PULLUP | MODE0 */
 
                  0x154 0x30  /* spi0_d0, INPUT_PULLUP | MODE0 */
 
                  0x158 0x10  /* spi0_d1, OUTPUT_PULLUP | MODE0 */
 
                  0x15c 0x10  /* spi0_cs0, OUTPUT_PULLUP | MODE0 */
 
                >;
 
            };
 
        };
 
    };
 
  
    fragment@1 {
 
        target = <&spi0>;
 
        __overlay__ {
 
            #address-cells = <1>;
 
            #size-cells = <0>;
 
  
            status = "okay";
+
channel@0 {
            pinctrl-names = "default";
+
#address-cells = <1>;
            pinctrl-0 = <&spi0_pins_s0>;
+
#size-cells = <0>;
  
            spidev@0 {
+
compatible = "spidev";
                spi-max-frequency = <24000000>;
+
 
                reg = <0>;
+
reg = <0>;
                compatible = "linux,spidev";
+
spi-max-frequency = <16000000>;
            };
+
spi-cpha;
        };
+
};
    };
+
 
 +
/* channel@1 {
 +
#address-cells = <1>;
 +
#size-cells = <0>;
 +
 
 +
compatible = "spidev";
 +
 
 +
reg = <1>;
 +
spi-max-frequency = <16000000>;
 +
}; */
 +
};
 +
};
 
};
 
};
 
</nowiki>
 
</nowiki>
  
 
Compile it with
 
Compile it with
  dtc -O dtb -o BB-SPI0-01-00A0.dtbo -b 0 -@ BB-SPI0-01-00A0.dts
+
  dtc -O dtb -o BB-SPI0-00A0.dtbo -b 0 -@ BB-SPI0-00A0.dts
 
and copy the result to <code>/lib/firmware</code>:
 
and copy the result to <code>/lib/firmware</code>:
  cp BB-SPI0-01-00A0.dtbo /lib/firmware/
+
  cp BB-SPI0-00A0.dtbo /lib/firmware/
  
Then enable this overlay:
+
Then test this overlay:
  echo BB-SPI0-01 > /sys/devices/bone_capemgr.*/slots
+
  echo BB-SPI0 > /sys/devices/bone_capemgr.*/slots
 
and check that it has worked:
 
and check that it has worked:
 
  ls -al /dev/spidev1.*
 
  ls -al /dev/spidev1.*
  
To make this persistent you have to edit <code>/boot/uboot/uEnv.txt</code> by appending
+
To make this persistent you have to...
optargs=quiet drm.debug=7 capemgr.enable_partno=BB-SPI0-01
+
 
 +
1. edit <code>/boot/uboot/uEnv.txt</code> by appending <code>capemgr.enable_partno=BB-SPI0</code> to the <code>optargs</code> directive (if it is not there already just add a line with <code>optargs=capemgr.enable_partno=BB-SPI0</code>).
 +
 
 +
2. update the initrd (e.g. with <code>/opt/scripts/tools/update_initrd.sh)
 +
 
 +
3. reboot

Revision as of 15:12, 17 October 2014

flashrom on the BeagleBone Black

This page is WIP.

Required packages: the usual suspects.

  • build-essential
  • libpci-dev

Enabling SPI0

Tested with a BBB rev.c and its default installation (Linux 3.8.13-bone47).

Create a file BB-SPI0-00A0.dts with the following contents:

/*
 * Copyright (C) 2013 CircuitCo
 * Copyright (C) 2014 Stefan Tauner
 *
 * Virtual cape for SPI0 of the BBB + 2 GPIO pins permanent high
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
/dts-v1/;
/plugin/;

/ {
	compatible = "ti,beaglebone", "ti,beaglebone-black";

	/* identification */
	part-number = "BB-SPI0";
	version = "00A0";

	/* state the resources this cape uses */
	exclusive-use =
		/* the pin header uses */
		"P9.17",	/* SPI0 CS0 */
		"P9.18",	/* SPI0 DI/MISO */
		"P9.21",	/* SPI0 DO/MOSI */
		"P9.22",	/* SPI0 SCLK */
		/* Use P9.23, P9.25 */
		"P9.23",	/* GPIO1_17 */
		"P9.25",	/* GPIO3_21 */
		/* the hardware ip uses */
		"spi0";

	fragment@0 {
		target = <&am33xx_pinmux>;
		__overlay__ {
			/* default state has all gpios released and mode set to uart1 */
			bb_spi0_pins: pinmux_bb_spi0_pins {
				pinctrl-single,pins = <
					0x150 0x30	/* spi0_sclk, INPUT_PULLUP | MODE0 */
					0x154 0x30	/* spi0_d0, INPUT_PULLUP | MODE0 */
					0x158 0x10	/* spi0_d1, OUTPUT_PULLUP | MODE0 */
					0x15c 0x10	/* spi0_cs0, OUTPUT_PULLUP | MODE0 */
					0x044 0x10	/* gpmc_a1, OUTPUT_PULLUP | MODE0 */
					0x1AC 0x10	/* mcasp0_ahclkx, OUTPUT_PULLUP | MODE0 */
				>;
			};
		};
	};

	fragment@1 {
		target = <&spi0>;	/* spi0 is numbered correctly */
		__overlay__ {
			#address-cells = <1>;
			#size-cells = <0>;

			status = "okay";
			pinctrl-names = "default";
			pinctrl-0 = <&bb_spi0_pins>;


			channel@0 {
				#address-cells = <1>;
				#size-cells = <0>;

				compatible = "spidev";

				reg = <0>;
				spi-max-frequency = <16000000>;
				spi-cpha;
			};

/*			channel@1 {
				#address-cells = <1>;
				#size-cells = <0>;

				compatible = "spidev";

				reg = <1>;
				spi-max-frequency = <16000000>;
			}; */
		};
	};
};

Compile it with

dtc -O dtb -o BB-SPI0-00A0.dtbo -b 0 -@ BB-SPI0-00A0.dts

and copy the result to /lib/firmware:

cp BB-SPI0-00A0.dtbo /lib/firmware/

Then test this overlay:

echo BB-SPI0 > /sys/devices/bone_capemgr.*/slots

and check that it has worked:

ls -al /dev/spidev1.*

To make this persistent you have to...

1. edit /boot/uboot/uEnv.txt by appending capemgr.enable_partno=BB-SPI0 to the optargs directive (if it is not there already just add a line with optargs=capemgr.enable_partno=BB-SPI0).

2. update the initrd (e.g. with /opt/scripts/tools/update_initrd.sh)

3. reboot