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The system host communicates with 8051 via ECPCMD, ECPARG1, ECPARG2, and ECPARG3 registers in EC space offset 10h, 11h, 12h and 13h. A non-zero value of PCMD will cause the 8051 P0IE.0 interrupt to take place informing the 8051 firmware, and the 8051 firmware will take the responsibility to carry this command.


  • 01h Query 8051 Status
  • 02h Idle
  • 03h Power down
  • 04h Init flash write - The 8051 should return OK status to grant host system to write flash. After the completion of this command, the 8051 should enter IDLE mode or reset condition (set EC_PXCFG bit 0 = 1) to prevent from 8051 fetching instruction code.
  • entry : argument_1 - if 01 - update all flash content, including 8051 code region.

if 02 - update system BIOS, not including 8051 code region.

  • exit cmd 00h argument_1 if 00h: OK, the host can write flash now.

if 01h: Error, no AC Adapter (the AC should be plugged during update flash). if 02h: Error, unknown condition.


There are two memory address segments that are decoded by KB38xx/39xx

  1. 000Y_0000h ~ 000F_FFFFh, where Y is selectable to C/E/Fh in register LFMSM(FE91h)
  2. FFXX_0000h~FFFF_FFFFh, where XX is selectable to FE/FC/F8/F0/E0/C0/80h in register LFMSM(FE91h).