[flashrom] [RFC] National Semiconductor DP83815 NIC patch

[Andrew Morgan]

On 07/06/10 22:19, Carl-Daniel Hailfinger wrote:
> Can you reformat this comment (and the other identical comment) a bit?
> Please make sure to take care of the 80 column limit, start each line
> with an asterisk and align the asterisks, similar to this:
>
> 	/*
> 	 * comment
> 	 * more comment
> 	 * even more comment
> 	 */
>
>
> Ah yes, and while I know I suggested this wording, I'd like to rephrase
> it a bit. Sorry.
>
> "The datasheet requires 32 bit accesses to this register, but it seems
> that requirement might only apply if the register is memory mapped. Bit
> 8-31 of this register are apparently don't care, and if this register is
> I/O port mapped 8 bit accesses to the lowest byte of the register seem
> to work fine. Due to that, we ignore the advice in the data sheet."
>
> Note to you: It would be an interesting experiment to replace the OUTB
> with an OUTL, and compare write/read reliability if the high 24 bits are
> 1 or 0. This is not needed before I commit, but hey... maybe it helps
> you and the soldering is OK after all.
>
> Sorry for the nitpicks in the second review round. I think the patch
> looks really good, and plan to apply it later tonight.
>
> Regards,
> Carl-Daniel
>
>    

Here's the next patch, hopefully it is ok. I did try to think of more 
descriptive text for the comment, then got busy testing the code out 
instead.

I have removed one line:

max_rom_decode.parallel = 65536;

As it shouldn't have been there anyway. I don't believe this is a 
requirement as the NIC chip has more address lines than are required for 
64K and there are tracks on the PCB leading to the boot ROM socket for 
those address lines.

I had a quick try replacing OUTB with OUTL and that doesn't seem to 
work, even probe doesn't work then, lots of "probe_jedec_common: id1 
0xff, id2 0xff".

Patch attached.

-- 

Andrew.

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