[flashrom] [PATCH] ICH SPI address window for reads
c-d.hailfinger.devel.2006 at gmx.net
Wed Sep 15 02:14:11 CEST 2010
On 15.09.2010 02:06, David Hendricks wrote:
> On Tue, Sep 14, 2010 at 4:59 PM, Carl-Daniel Hailfinger <
> c-d.hailfinger.devel.2006 at gmx.net> wrote:
>> ICH SPI has the ability to restrict SPI read/write accesses to a given
>> address range. The low end of the range is configurable by the BIOS (and
>> by flashrom if the BIOS didn't lock down the flash interface), the high
>> end of the range is 0xffffff (2^24-1).
>> This patch checks for an address range restriction and uses the low end
>> of the allowed range as base for SPI reads. A similar workaround for
>> REMS/RES opcodes has been committed in r500.
>> This fixes read on the Intel D945GCLF mainboard where the stock BIOS
>> enforces a restricted address range.
>> Please note that writes need the same fix, but for architectural reasons
>> that fix will be merged once partial write is available.
>> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
> I applied and tested the patch with positive results:
> Acked-by: David Hendricks <dhendrix at google.com>
Thanks for the review and test, committed in r1170.
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