[flashrom] [PATCH 3/8] ichspi: don't touch the nonexistent(?) BBAR register on ICH8

[Stefan Tauner]

There is no sign of BBAR (BIOS Base Address Configuration Register)
in the public datasheet (or specification update) of the ICH8. Also,
the offset of that register has changed between ICH7 (SPIBAR + 50h)
and ICH9 (SPIBAR + A0h), so we have no clue if or where it is on
ICH8. Better don't try to touch it at all and assume/hope it is 0.

---

Until now we implicitly accessed it via the ICH9 offset. I think
this is an evident sign that the naming of the spi controller types
in ichspi.c (SPI_CONTROLLER_VIA, SPI_CONTROLLER_ICH7,
SPI_CONTROLLER_ICH9) might not cut it and we should think about
introducing a special ICH8 one, even if its struct is identical to
the ICH9. having most of the ICH8 code path guarded/controlled by
SPI_CONTROLLER_ICH7 or SPI_CONTROLLER_ICH9 (depending on which is
more similar in one situation), is an open invitation to similar
bugs because one easily forgets that ICH8 is very special.

Signed-off-by: Stefan Tauner <stefan.tauner at student.tuwien.ac.at>
---
 ichspi.c |   25 ++++++++++++-------------
 1 files changed, 12 insertions(+), 13 deletions(-)

diff --git a/ichspi.c b/ichspi.c
index 343a0af..d51a6b2 100644
--- a/ichspi.c
+++ b/ichspi.c
@@ -558,20 +558,19 @@ static int program_opcodes(OPCODES *op, int enable_undo)
  * Try to set BBAR (BIOS Base Address Register), but read back the value in case
  * it didn't stick.
  */
-static void ich_set_bbar(uint32_t min_addr)
+static void ich_set_bbar(int ich_generation, uint32_t min_addr)
 {
 	int bbar_off;
-	switch (spi_programmer->type) {
-	case SPI_CONTROLLER_ICH7:
-	case SPI_CONTROLLER_VIA:
+	switch (ich_generation) {
+	case 7:
 		bbar_off = 0x50;
 		break;
-	case SPI_CONTROLLER_ICH9:
+	case 8:
+		msg_perr("BBAR offset is unknown on ICH8!\n");
+		return;
+	default:		/* Future version might behave the same */
 		bbar_off = ICH9_REG_BBAR;
 		break;
-	default:
-		msg_perr("Unknown chipset for BBAR setting!\n");
-		return;
 	}
 	
 	ichspi_bbar = mmio_readl(ich_spibar + bbar_off) & ~BBAR_MASK;
@@ -589,6 +588,8 @@ static void ich_set_bbar(uint32_t min_addr)
 	 */
 	if (ichspi_bbar != min_addr)
 		msg_perr("Setting BBAR failed!\n");
+	else
+		msg_pspew("Setting BBAR succeeded!\n");
 }
 
 /* Read len bytes from the fdata/spid register into the data array.
@@ -657,11 +658,6 @@ static int ich_init_opcodes(void)
 		msg_pdbg("Programming OPCODES... ");
 		curopcodes_done = &O_ST_M25P;
 		rc = program_opcodes(curopcodes_done, 1);
-		/* Technically not part of opcode init, but it allows opcodes
-		 * to run without transaction errors by setting the lowest
-		 * allowed address to zero.
-		 */
-		ich_set_bbar(0);
 	}
 
 	if (rc) {
@@ -1268,6 +1264,7 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb,
 			msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n");
 			ichspi_lock = 1;
 		}
+		ich_set_bbar(ich_generation, 0);
 		ich_init_opcodes();
 		break;
 	case SPI_CONTROLLER_ICH9:
@@ -1349,6 +1346,7 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb,
 
 			tmp = mmio_readl(ich_spibar + ICH9_REG_FPB);
 			msg_pdbg("0xD0: 0x%08x (FPB)\n", tmp);
+			ich_set_bbar(ich_generation, 0);
 		}
 
 		msg_pdbg("\n");
@@ -1439,6 +1437,7 @@ int via_init_spi(struct pci_dev *dev)
 		ichspi_lock = 1;
 	}
 
+	ich_set_bbar(7, 0);
 	ich_init_opcodes();
 
 	return 0;
-- 
1.7.1