[flashrom] [PATCH] Check class for nvidia southbridge

[Carl-Daniel Hailfinger]

Hi Yinghai,

maybe you remember what the CK804 A01 comment mentioned in the mail
below refers to.

The chipset_enable.c code we're referring to is available at
http://www.flashrom.org/trac/flashrom/browser/trunk/chipset_enable.c

Michael, I would mask with the PCI class with 0xff00 and allow all bridges.

Regards,
Carl-Daniel

Am 13.03.2012 22:29 schrieb Michael Karcher:
> On dual-socket mainboards, there are two nvidia southbridge chips (one
> per socket).  The south bridge really used as south bridge has the
> device class of the ISA/LPC bridge device set to 0x0601 [ISA Bridge],
> while the other one has a device class in the 0x05xx range [RAM stuff].
>
> This will select the correct south bridge for the chipset enable, and
> removes the hack that the 0x361 device needed to be ignored to get rid
> of the secondary south bridge on the Tyan S2915 / HP xw9400.
>
> The CK804 entry with the ID 10de:00d3 (which triggers on the secondary
> south bridge of the L1N64) has the comment
>   /* Slave, should not be here, to fix known bug for A01. */
> Does anyone still remember what this 7 year old comment is trying to tell
> us? What is "A01"? A chipset revision? What class does this device
> have in "A01"? Will the class-must-be-0601-check break "it"?
>
> Signed-off-by: Michael Karcher <flashrom at mkarcher.dialup.fu-berlin.de>
> ---
>  chipset_enable.c |   22 +++++++++++++---------
>  1 files changed, 13 insertions(+), 9 deletions(-)
>
> diff --git a/chipset_enable.c b/chipset_enable.c
> index 0aba1e0..adf2e0d 100644
> --- a/chipset_enable.c
> +++ b/chipset_enable.c
> @@ -906,6 +906,12 @@ static int enable_flash_ck804(struct pci_dev *dev, const char *name)
>  {
>  	uint8_t old, new;
>  
> +	if (pci_read_word(dev, PCI_CLASS_DEVICE) != 0x0601) {
> +		/* output is followed by "OK - searching for ...\n" */
> +		msg_pinfo(" Seems to be a secondary south bridge, ");
> +		return NOT_DONE_YET;
> +	}
> +
>  	pci_write_byte(dev, 0x92, 0x00);
>  	if (pci_read_byte(dev, 0x92) != 0x00) {
>  		msg_pinfo("Setting register 0x%x to 0x%x on %s failed "
> @@ -995,6 +1001,12 @@ static int enable_flash_mcp55(struct pci_dev *dev, const char *name)
>  	uint8_t old, new, val;
>  	uint16_t wordval;
>  
> +	if (pci_read_word(dev, PCI_CLASS_DEVICE) != 0x0601) {
> +		/* output is followed by "OK - searching for ...\n" */
> +		msg_pinfo(" Seems to be a secondary south bridge, ");
> +		return NOT_DONE_YET;
> +	}
> +
>  	/* Set the 0-16 MB enable bits. */
>  	val = pci_read_byte(dev, 0x88);
>  	val |= 0xff;		/* 256K */
> @@ -1207,15 +1219,7 @@ const struct penable chipset_enables[] = {
>  	{0x10de, 0x0262, NT, "NVIDIA", "MCP51",		enable_flash_ck804},
>  	{0x10de, 0x0263, NT, "NVIDIA", "MCP51",		enable_flash_ck804},
>  	{0x10de, 0x0360, OK, "NVIDIA", "MCP55",		enable_flash_mcp55}, /* M57SLI*/
> -	/* 10de:0361 is present in Tyan S2915 OEM systems, but not connected to
> -	 * the flash chip. Instead, 10de:0364 is connected to the flash chip.
> -	 * Until we have PCI device class matching or some fallback mechanism,
> -	 * this is needed to get flashrom working on Tyan S2915 and maybe other
> -	 * dual-MCP55 boards.
> -	 */
> -#if 0
> -	{0x10de, 0x0361, NT, "NVIDIA", "MCP55",		enable_flash_mcp55}, /* LPC */
> -#endif
> +	{0x10de, 0x0361, OK, "NVIDIA", "MCP55",		enable_flash_mcp55}, /* LPC */
>  	{0x10de, 0x0362, OK, "NVIDIA", "MCP55",		enable_flash_mcp55}, /* LPC */
>  	{0x10de, 0x0363, OK, "NVIDIA", "MCP55",		enable_flash_mcp55}, /* LPC */
>  	{0x10de, 0x0364, OK, "NVIDIA", "MCP55",		enable_flash_mcp55}, /* LPC */


-- 
http://www.hailfinger.org/