[flashrom] [PATCH 03/10] Add return code to rmmio_writel

[Niklas Söderlund]

Signed-off-by: Niklas Söderlund <niso at kth.se>
---
 hwaccess.c   |  3 ++-
 ichspi.c     | 29 +++++++++++++++++++----------
 programmer.h |  2 +-
 sb600spi.c   |  5 +++--
 4 files changed, 25 insertions(+), 14 deletions(-)

diff --git a/hwaccess.c b/hwaccess.c
index a386998..e156647 100644
--- a/hwaccess.c
+++ b/hwaccess.c
@@ -250,10 +250,11 @@ int rmmio_writew(uint16_t val, void *addr)
 	return 0;
 }
 
-void rmmio_writel(uint32_t val, void *addr)
+int rmmio_writel(uint32_t val, void *addr)
 {
 	register_undo_mmio_writel(addr);
 	mmio_writel(val, addr);
+	return 0;
 }
 
 void rmmio_le_writeb(uint8_t val, void *addr)
diff --git a/ichspi.c b/ichspi.c
index 1dcff5b..9dfe4ff 100644
--- a/ichspi.c
+++ b/ichspi.c
@@ -598,7 +598,7 @@ static int ich_missing_opcodes()
  * Try to set BBAR (BIOS Base Address Register), but read back the value in case
  * it didn't stick.
  */
-static void ich_set_bbar(uint32_t min_addr)
+static int ich_set_bbar(uint32_t min_addr)
 {
 	int bbar_off;
 	switch (ich_generation) {
@@ -607,7 +607,7 @@ static void ich_set_bbar(uint32_t min_addr)
 		break;
 	case CHIPSET_ICH8:
 		msg_perr("BBAR offset is unknown on ICH8!\n");
-		return;
+		return 1;
 	case CHIPSET_ICH9:
 	default:		/* Future version might behave the same */
 		bbar_off = ICH9_REG_BBAR;
@@ -621,7 +621,8 @@ static void ich_set_bbar(uint32_t min_addr)
 	}
 	min_addr &= BBAR_MASK;
 	ichspi_bbar |= min_addr;
-	rmmio_writel(ichspi_bbar, ich_spibar + bbar_off);
+	if (rmmio_writel(ichspi_bbar, ich_spibar + bbar_off))
+		return 1;
 	ichspi_bbar = mmio_readl(ich_spibar + bbar_off) & BBAR_MASK;
 
 	/* We don't have any option except complaining. And if the write
@@ -630,6 +631,7 @@ static void ich_set_bbar(uint32_t min_addr)
 	if (ichspi_bbar != min_addr)
 		msg_perr("Setting BBAR to 0x%08x failed! New value: 0x%08x.\n",
 			 min_addr, ichspi_bbar);
+	return 0;
 }
 
 /* Read len bytes from the fdata/spid register into the data array.
@@ -1493,7 +1495,7 @@ static int ich9_handle_pr(int i)
 
 /* Set/Clear the read and write protection enable bits of PR register @i
  * according to @read_prot and @write_prot. */
-static void ich9_set_pr(int i, int read_prot, int write_prot)
+static int ich9_set_pr(int i, int read_prot, int write_prot)
 {
 	void *addr = ich_spibar + ICH9_REG_PR0 + (i * 4);
 	uint32_t old = mmio_readl(addr);
@@ -1507,11 +1509,14 @@ static void ich9_set_pr(int i, int read_prot, int write_prot)
 		new |= (1 << PR_WP_OFF);
 	if (old == new) {
 		msg_gspew(" already.\n");
-		return;
+		return 0;
 	}
 	msg_gspew(", trying to set it to 0x%08x ", new);
-	rmmio_writel(new, addr);
+	if (rmmio_writel(new, addr))
+		return 1;
 	msg_gspew("resulted in 0x%08x.\n", mmio_readl(addr));
+
+	return 0;
 }
 
 static const struct spi_programmer spi_programmer_ich7 = {
@@ -1622,7 +1627,8 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb,
 			ichspi_lock = 1;
 		}
 		ich_init_opcodes();
-		ich_set_bbar(0);
+		if (ich_set_bbar(0))
+			return 1;
 		register_spi_programmer(&spi_programmer_ich7);
 		break;
 	case CHIPSET_ICH8:
@@ -1710,7 +1716,8 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb,
 		for (i = 0; i < 5; i++) {
 			/* if not locked down try to disable PR locks first */
 			if (!ichspi_lock)
-				ich9_set_pr(i, 0, 0);
+				if (ich9_set_pr(i, 0, 0))
+					return 1;
 			ich_spi_rw_restricted |= ich9_handle_pr(i);
 		}
 
@@ -1768,7 +1775,8 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb,
 				tmp = mmio_readl(ich_spibar + ICH9_REG_FPB);
 				msg_pdbg("0xD0: 0x%08x (FPB)\n", tmp);
 			}
-			ich_set_bbar(0);
+			if (ich_set_bbar(0))
+				return 1;
 		}
 
 		msg_pdbg("\n");
@@ -1884,7 +1892,8 @@ int via_init_spi(struct pci_dev *dev, uint32_t mmio_base)
 		ichspi_lock = 1;
 	}
 
-	ich_set_bbar(0);
+	if (ich_set_bbar(0))
+		return 1;
 	ich_init_opcodes();
 
 	return 0;
diff --git a/programmer.h b/programmer.h
index 317f51f..b8538a3 100644
--- a/programmer.h
+++ b/programmer.h
@@ -349,7 +349,7 @@ uint32_t mmio_le_readl(void *addr);
 #define pci_mmio_readl mmio_le_readl
 int rmmio_writeb(uint8_t val, void *addr);
 int rmmio_writew(uint16_t val, void *addr);
-void rmmio_writel(uint32_t val, void *addr);
+int rmmio_writel(uint32_t val, void *addr);
 void rmmio_le_writeb(uint8_t val, void *addr);
 void rmmio_le_writew(uint16_t val, void *addr);
 void rmmio_le_writel(uint32_t val, void *addr);
diff --git a/sb600spi.c b/sb600spi.c
index 4668da0..05752c9 100644
--- a/sb600spi.c
+++ b/sb600spi.c
@@ -319,8 +319,9 @@ static int handle_speed(struct pci_dev *dev)
 			msg_pdbg("Fast Reads are %sabled\n", fast_read ? "en" : "dis");
 			if (fast_read) {
 				msg_pdbg("Disabling them temporarily.\n");
-				rmmio_writel(mmio_readl(sb600_spibar + 0x00) & ~(0x1 << 18),
-					     sb600_spibar + 0x00);
+				if (rmmio_writel(mmio_readl(sb600_spibar + 0x00) & ~(0x1 << 18),
+					     sb600_spibar + 0x00))
+					return 1;
 			}
 		}
 		tmp = (mmio_readb(sb600_spibar + 0xd) >> 4) & 0x3;
-- 
1.8.3.4